mediatek/mt7601u/mt7601u.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  */
0006
0007 #ifndef MT7601U_H
0008 #define MT7601U_H
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/kernel.h>
0012 #include <linux/device.h>
0013 #include <linux/mutex.h>
0014 #include <linux/usb.h>
0015 #include <linux/completion.h>
0016 #include <net/mac80211.h>
0017 #include <linux/debugfs.h>
0018 #include <linux/average.h>
0019
0020 #include "regs.h"
0021
0022 #define MT_CALIBRATE_INTERVAL       (4 * HZ)
0023
0024 #define MT_FREQ_CAL_INIT_DELAY      (30 * HZ)
0025 #define MT_FREQ_CAL_CHECK_INTERVAL  (10 * HZ)
0026 #define MT_FREQ_CAL_ADJ_INTERVAL    (HZ / 2)
0027
0028 #define MT_BBP_REG_VERSION      0x00
0029
0030 #define MT_USB_AGGR_SIZE_LIMIT      28 /* * 1024B */
0031 #define MT_USB_AGGR_TIMEOUT     0x80 /* * 33ns */
0032 #define MT_RX_ORDER         3
0033 #define MT_RX_URB_SIZE          (PAGE_SIZE << MT_RX_ORDER)
0034
0035 struct mt7601u_dma_buf {
0036     struct urb *urb;
0037     void *buf;
0038     dma_addr_t dma;
0039     size_t len;
0040 };
0041
0042 struct mt7601u_mcu {
0043     struct mutex mutex;
0044
0045     u8 msg_seq;
0046
0047     struct mt7601u_dma_buf resp;
0048     struct completion resp_cmpl;
0049 };
0050
0051 struct mt7601u_freq_cal {
0052     struct delayed_work work;
0053     u8 freq;
0054     bool enabled;
0055     bool adjusting;
0056 };
0057
0058 struct mac_stats {
0059     u64 rx_stat[6];
0060     u64 tx_stat[6];
0061     u64 aggr_stat[2];
0062     u64 aggr_n[32];
0063     u64 zero_len_del[2];
0064 };
0065
0066 #define N_RX_ENTRIES    16
0067 struct mt7601u_rx_queue {
0068     struct mt7601u_dev *dev;
0069
0070     struct mt7601u_dma_buf_rx {
0071         struct urb *urb;
0072         struct page *p;
0073     } e[N_RX_ENTRIES];
0074
0075     unsigned int start;
0076     unsigned int end;
0077     unsigned int entries;
0078     unsigned int pending;
0079 };
0080
0081 #define N_TX_ENTRIES    64
0082
0083 struct mt7601u_tx_queue {
0084     struct mt7601u_dev *dev;
0085
0086     struct mt7601u_dma_buf_tx {
0087         struct urb *urb;
0088         struct sk_buff *skb;
0089     } e[N_TX_ENTRIES];
0090
0091     unsigned int start;
0092     unsigned int end;
0093     unsigned int entries;
0094     unsigned int used;
0095     unsigned int fifo_seq;
0096 };
0097
0098 /* WCID allocation:
0099  *     0: mcast wcid
0100  *     1: bssid wcid
0101  *  1...: STAs
0102  * ...7e: group wcids
0103  *    7f: reserved
0104  */
0105 #define N_WCIDS     128
0106 #define GROUP_WCID(idx) (N_WCIDS - 2 - idx)
0107
0108 struct mt7601u_eeprom_params;
0109
0110 #define MT_EE_TEMPERATURE_SLOPE     39
0111 #define MT_FREQ_OFFSET_INVALID      -128
0112
0113 enum mt_temp_mode {
0114     MT_TEMP_MODE_NORMAL,
0115     MT_TEMP_MODE_HIGH,
0116     MT_TEMP_MODE_LOW,
0117 };
0118
0119 enum mt_bw {
0120     MT_BW_20,
0121     MT_BW_40,
0122 };
0123
0124 enum {
0125     MT7601U_STATE_INITIALIZED,
0126     MT7601U_STATE_REMOVED,
0127     MT7601U_STATE_WLAN_RUNNING,
0128     MT7601U_STATE_MCU_RUNNING,
0129     MT7601U_STATE_SCANNING,
0130     MT7601U_STATE_READING_STATS,
0131     MT7601U_STATE_MORE_STATS,
0132 };
0133
0134 DECLARE_EWMA(rssi, 10, 4);
0135
0136 /**
0137  * struct mt7601u_dev - adapter structure
0138  * @lock:       protects @wcid->tx_rate.
0139  * @mac_lock:       locks out mac80211's tx status and rx paths.
0140  * @tx_lock:        protects @tx_q and changes of MT7601U_STATE_*_STATS
0141  *          flags in @state.
0142  * @rx_lock:        protects @rx_q.
0143  * @con_mon_lock:   protects @ap_bssid, @bcn_*, @avg_rssi.
0144  * @mutex:      ensures exclusive access from mac80211 callbacks.
0145  * @vendor_req_mutex:   protects @vend_buf, ensures atomicity of read/write
0146  *          accesses
0147  * @reg_atomic_mutex:   ensures atomicity of indirect register accesses
0148  *          (accesses to RF and BBP).
0149  * @hw_atomic_mutex:    ensures exclusive access to HW during critical
0150  *          operations (power management, channel switch).
0151  */
0152 struct mt7601u_dev {
0153     struct ieee80211_hw *hw;
0154     struct device *dev;
0155
0156     unsigned long state;
0157
0158     struct mutex mutex;
0159
0160     unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG];
0161
0162     struct cfg80211_chan_def chandef;
0163     struct ieee80211_supported_band *sband_2g;
0164
0165     struct mt7601u_mcu mcu;
0166
0167     struct delayed_work cal_work;
0168     struct delayed_work mac_work;
0169
0170     struct workqueue_struct *stat_wq;
0171     struct delayed_work stat_work;
0172
0173     struct mt76_wcid *mon_wcid;
0174     struct mt76_wcid __rcu *wcid[N_WCIDS];
0175
0176     spinlock_t lock;
0177     spinlock_t mac_lock;
0178
0179     const u16 *beacon_offsets;
0180
0181     u8 macaddr[ETH_ALEN];
0182     struct mt7601u_eeprom_params *ee;
0183
0184     struct mutex vendor_req_mutex;
0185     void *vend_buf;
0186
0187     struct mutex reg_atomic_mutex;
0188     struct mutex hw_atomic_mutex;
0189
0190     u32 rxfilter;
0191     u32 debugfs_reg;
0192
0193     u8 out_eps[8];
0194     u8 in_eps[8];
0195     u16 out_max_packet;
0196     u16 in_max_packet;
0197
0198     /* TX */
0199     spinlock_t tx_lock;
0200     struct tasklet_struct tx_tasklet;
0201     struct mt7601u_tx_queue *tx_q;
0202     struct sk_buff_head tx_skb_done;
0203
0204     atomic_t avg_ampdu_len;
0205
0206     /* RX */
0207     spinlock_t rx_lock;
0208     struct tasklet_struct rx_tasklet;
0209     struct mt7601u_rx_queue rx_q;
0210
0211     /* Connection monitoring things */
0212     spinlock_t con_mon_lock;
0213     u8 ap_bssid[ETH_ALEN];
0214
0215     s8 bcn_freq_off;
0216     u8 bcn_phy_mode;
0217
0218     struct ewma_rssi avg_rssi;
0219
0220     u8 agc_save;
0221
0222     struct mt7601u_freq_cal freq_cal;
0223
0224     bool tssi_read_trig;
0225
0226     s8 tssi_init;
0227     s8 tssi_init_hvga;
0228     s16 tssi_init_hvga_offset_db;
0229
0230     int prev_pwr_diff;
0231
0232     enum mt_temp_mode temp_mode;
0233     int curr_temp;
0234     int dpd_temp;
0235     s8 raw_temp;
0236     bool pll_lock_protect;
0237
0238     u8 bw;
0239     bool chan_ext_below;
0240
0241     /* PA mode */
0242     u32 rf_pa_mode[2];
0243
0244     struct mac_stats stats;
0245 };
0246
0247 struct mt7601u_tssi_params {
0248     char tssi0;
0249     int trgt_power;
0250 };
0251
0252 struct mt76_wcid {
0253     u8 idx;
0254     u8 hw_key_idx;
0255
0256     u16 tx_rate;
0257     bool tx_rate_set;
0258     u8 tx_rate_nss;
0259 };
0260
0261 struct mt76_vif {
0262     u8 idx;
0263
0264     struct mt76_wcid group_wcid;
0265 };
0266
0267 struct mt76_sta {
0268     struct mt76_wcid wcid;
0269     u16 agg_ssn[IEEE80211_NUM_TIDS];
0270 };
0271
0272 struct mt76_reg_pair {
0273     u32 reg;
0274     u32 value;
0275 };
0276
0277 struct mt7601u_rxwi;
0278
0279 extern const struct ieee80211_ops mt7601u_ops;
0280
0281 void mt7601u_init_debugfs(struct mt7601u_dev *dev);
0282
0283 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
0284 void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val);
0285 u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
0286 u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
0287 void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset,
0288              const void *data, int len);
0289
0290 int mt7601u_wait_asic_ready(struct mt7601u_dev *dev);
0291 bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
0292            int timeout);
0293 bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
0294             int timeout);
0295
0296 /* Compatibility with mt76 */
0297 #define mt76_rmw_field(_dev, _reg, _field, _val)    \
0298     mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
0299
0300 static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset)
0301 {
0302     return mt7601u_rr(dev, offset);
0303 }
0304
0305 static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val)
0306 {
0307     return mt7601u_wr(dev, offset, val);
0308 }
0309
0310 static inline u32
0311 mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val)
0312 {
0313     return mt7601u_rmw(dev, offset, mask, val);
0314 }
0315
0316 static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val)
0317 {
0318     return mt76_rmw(dev, offset, 0, val);
0319 }
0320
0321 static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val)
0322 {
0323     return mt76_rmw(dev, offset, val, 0);
0324 }
0325
0326 int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base,
0327                 const struct mt76_reg_pair *data, int len);
0328 int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset,
0329                  const u32 *data, int n);
0330 void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr);
0331
0332 /* Init */
0333 struct mt7601u_dev *mt7601u_alloc_device(struct device *dev);
0334 int mt7601u_init_hardware(struct mt7601u_dev *dev);
0335 int mt7601u_register_device(struct mt7601u_dev *dev);
0336 void mt7601u_cleanup(struct mt7601u_dev *dev);
0337
0338 int mt7601u_mac_start(struct mt7601u_dev *dev);
0339 void mt7601u_mac_stop(struct mt7601u_dev *dev);
0340
0341 /* PHY */
0342 int mt7601u_phy_init(struct mt7601u_dev *dev);
0343 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev);
0344 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path);
0345 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path);
0346 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw);
0347 void mt7601u_agc_save(struct mt7601u_dev *dev);
0348 void mt7601u_agc_restore(struct mt7601u_dev *dev);
0349 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,
0350                 struct cfg80211_chan_def *chandef);
0351 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev);
0352 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,
0353              struct mt7601u_rxwi *rxwi, u16 rate);
0354 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,
0355                    struct ieee80211_bss_conf *info);
0356
0357 /* MAC */
0358 void mt7601u_mac_work(struct work_struct *work);
0359 void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot,
0360                 int ht_mode);
0361 void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb);
0362 void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval);
0363 void
0364 mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
0365 void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev);
0366
0367 /* TX */
0368 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
0369         struct sk_buff *skb);
0370 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0371             unsigned int link_id, u16 queue,
0372             const struct ieee80211_tx_queue_params *params);
0373 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb);
0374 void mt7601u_tx_stat(struct work_struct *work);
0375
0376 /* util */
0377 void mt76_remove_hdr_pad(struct sk_buff *skb);
0378 int mt76_insert_hdr_pad(struct sk_buff *skb);
0379
0380 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below);
0381
0382 static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below)
0383 {
0384     return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below);
0385 }
0386
0387 int mt7601u_dma_init(struct mt7601u_dev *dev);
0388 void mt7601u_dma_cleanup(struct mt7601u_dev *dev);
0389
0390 int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb,
0391                struct mt76_wcid *wcid, int hw_q);
0392
0393 #endif