mediatek/mt7601u/mac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  */
0006
0007 #ifndef __MT76_MAC_H
0008 #define __MT76_MAC_H
0009
0010 struct mt76_tx_status {
0011     u8 valid:1;
0012     u8 success:1;
0013     u8 aggr:1;
0014     u8 ack_req:1;
0015     u8 is_probe:1;
0016     u8 wcid;
0017     u8 pktid;
0018     u8 retry;
0019     u16 rate;
0020 } __packed __aligned(2);
0021
0022 /* Note: values in original "RSSI" and "SNR" fields are not actually what they
0023  *   are called for MT7601U, names used by this driver are educated guesses
0024  *   (see vendor mac/ral_omac.c).
0025  */
0026 struct mt7601u_rxwi {
0027     __le32 rxinfo;
0028
0029     __le32 ctl;
0030
0031     __le16 frag_sn;
0032     __le16 rate;
0033
0034     u8 unknown;
0035     u8 zero[3];
0036
0037     u8 snr;
0038     u8 ant;
0039     u8 gain;
0040     u8 freq_off;
0041
0042     __le32 resv2;
0043     __le32 expert_ant;
0044 } __packed __aligned(4);
0045
0046 #define MT_RXINFO_BA            BIT(0)
0047 #define MT_RXINFO_DATA          BIT(1)
0048 #define MT_RXINFO_NULL          BIT(2)
0049 #define MT_RXINFO_FRAG          BIT(3)
0050 #define MT_RXINFO_U2M           BIT(4)
0051 #define MT_RXINFO_MULTICAST     BIT(5)
0052 #define MT_RXINFO_BROADCAST     BIT(6)
0053 #define MT_RXINFO_MYBSS         BIT(7)
0054 #define MT_RXINFO_CRCERR        BIT(8)
0055 #define MT_RXINFO_ICVERR        BIT(9)
0056 #define MT_RXINFO_MICERR        BIT(10)
0057 #define MT_RXINFO_AMSDU         BIT(11)
0058 #define MT_RXINFO_HTC           BIT(12)
0059 #define MT_RXINFO_RSSI          BIT(13)
0060 #define MT_RXINFO_L2PAD         BIT(14)
0061 #define MT_RXINFO_AMPDU         BIT(15)
0062 #define MT_RXINFO_DECRYPT       BIT(16)
0063 #define MT_RXINFO_BSSIDX3       BIT(17)
0064 #define MT_RXINFO_WAPI_KEY      BIT(18)
0065 #define MT_RXINFO_PN_LEN        GENMASK(21, 19)
0066 #define MT_RXINFO_SW_PKT_80211      BIT(22)
0067 #define MT_RXINFO_TCP_SUM_BYPASS    BIT(28)
0068 #define MT_RXINFO_IP_SUM_BYPASS     BIT(29)
0069 #define MT_RXINFO_TCP_SUM_ERR       BIT(30)
0070 #define MT_RXINFO_IP_SUM_ERR        BIT(31)
0071
0072 #define MT_RXWI_CTL_WCID        GENMASK(7, 0)
0073 #define MT_RXWI_CTL_KEY_IDX     GENMASK(9, 8)
0074 #define MT_RXWI_CTL_BSS_IDX     GENMASK(12, 10)
0075 #define MT_RXWI_CTL_UDF         GENMASK(15, 13)
0076 #define MT_RXWI_CTL_MPDU_LEN        GENMASK(27, 16)
0077 #define MT_RXWI_CTL_TID         GENMASK(31, 28)
0078
0079 #define MT_RXWI_FRAG            GENMASK(3, 0)
0080 #define MT_RXWI_SN          GENMASK(15, 4)
0081
0082 #define MT_RXWI_RATE_MCS        GENMASK(6, 0)
0083 #define MT_RXWI_RATE_BW         BIT(7)
0084 #define MT_RXWI_RATE_SGI        BIT(8)
0085 #define MT_RXWI_RATE_STBC       GENMASK(10, 9)
0086 #define MT_RXWI_RATE_ETXBF      BIT(11)
0087 #define MT_RXWI_RATE_SND        BIT(12)
0088 #define MT_RXWI_RATE_ITXBF      BIT(13)
0089 #define MT_RXWI_RATE_PHY        GENMASK(15, 14)
0090
0091 #define MT_RXWI_GAIN_RSSI_VAL       GENMASK(5, 0)
0092 #define MT_RXWI_GAIN_RSSI_LNA_ID    GENMASK(7, 6)
0093 #define MT_RXWI_ANT_AUX_LNA     BIT(7)
0094
0095 #define MT_RXWI_EANT_ENC_ANT_ID     GENMASK(7, 0)
0096
0097 enum mt76_phy_type {
0098     MT_PHY_TYPE_CCK,
0099     MT_PHY_TYPE_OFDM,
0100     MT_PHY_TYPE_HT,
0101     MT_PHY_TYPE_HT_GF,
0102 };
0103
0104 enum mt76_phy_bandwidth {
0105     MT_PHY_BW_20,
0106     MT_PHY_BW_40,
0107 };
0108
0109 struct mt76_txwi {
0110     __le16 flags;
0111     __le16 rate_ctl;
0112
0113     u8 ack_ctl;
0114     u8 wcid;
0115     __le16 len_ctl;
0116
0117     __le32 iv;
0118
0119     __le32 eiv;
0120
0121     u8 aid;
0122     u8 txstream;
0123     __le16 ctl;
0124 } __packed __aligned(4);
0125
0126 #define MT_TXWI_FLAGS_FRAG      BIT(0)
0127 #define MT_TXWI_FLAGS_MMPS      BIT(1)
0128 #define MT_TXWI_FLAGS_CFACK     BIT(2)
0129 #define MT_TXWI_FLAGS_TS        BIT(3)
0130 #define MT_TXWI_FLAGS_AMPDU     BIT(4)
0131 #define MT_TXWI_FLAGS_MPDU_DENSITY  GENMASK(7, 5)
0132 #define MT_TXWI_FLAGS_TXOP      GENMASK(9, 8)
0133 #define MT_TXWI_FLAGS_CWMIN     GENMASK(12, 10)
0134 #define MT_TXWI_FLAGS_NO_RATE_FALLBACK  BIT(13)
0135 #define MT_TXWI_FLAGS_TX_RPT        BIT(14)
0136 #define MT_TXWI_FLAGS_TX_RATE_LUT   BIT(15)
0137
0138 #define MT_TXWI_RATE_MCS        GENMASK(6, 0)
0139 #define MT_TXWI_RATE_BW         BIT(7)
0140 #define MT_TXWI_RATE_SGI        BIT(8)
0141 #define MT_TXWI_RATE_STBC       GENMASK(10, 9)
0142 #define MT_TXWI_RATE_PHY_MODE       GENMASK(15, 14)
0143
0144 #define MT_TXWI_ACK_CTL_REQ     BIT(0)
0145 #define MT_TXWI_ACK_CTL_NSEQ        BIT(1)
0146 #define MT_TXWI_ACK_CTL_BA_WINDOW   GENMASK(7, 2)
0147
0148 #define MT_TXWI_LEN_BYTE_CNT        GENMASK(11, 0)
0149 #define MT_TXWI_LEN_PKTID       GENMASK(15, 12)
0150
0151 #define MT_TXWI_CTL_TX_POWER_ADJ    GENMASK(3, 0)
0152 #define MT_TXWI_CTL_CHAN_CHECK_PKT  BIT(4)
0153 #define MT_TXWI_CTL_PIFS_REV        BIT(6)
0154
0155 u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb,
0156             u8 *data, void *rxi);
0157 int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx,
0158               struct ieee80211_key_conf *key);
0159 void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid,
0160                 const struct ieee80211_tx_rate *rate);
0161
0162 int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx,
0163                   struct ieee80211_key_conf *key);
0164 u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev,
0165              const struct ieee80211_tx_rate *rate, u8 *nss_val);
0166 struct mt76_tx_status
0167 mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev);
0168 void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat);
0169 void mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *addr);
0170
0171 #endif