mediatek/mt7601u/initvals.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * (c) Copyright 2002-2010, Ralink Technology, Inc.
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  */
0006
0007 #ifndef __MT7601U_INITVALS_H
0008 #define __MT7601U_INITVALS_H
0009
0010 static const struct mt76_reg_pair bbp_common_vals[] = {
0011     {  65,  0x2c },
0012     {  66,  0x38 },
0013     {  68,  0x0b },
0014     {  69,  0x12 },
0015     {  70,  0x0a },
0016     {  73,  0x10 },
0017     {  81,  0x37 },
0018     {  82,  0x62 },
0019     {  83,  0x6a },
0020     {  84,  0x99 },
0021     {  86,  0x00 },
0022     {  91,  0x04 },
0023     {  92,  0x00 },
0024     { 103,  0x00 },
0025     { 105,  0x05 },
0026     { 106,  0x35 },
0027 };
0028
0029 static const struct mt76_reg_pair bbp_chip_vals[] = {
0030     {   1, 0x04 },  {   4, 0x40 },  {  20, 0x06 },  {  31, 0x08 },
0031     /* CCK Tx Control */
0032     { 178, 0xff },
0033     /* AGC/Sync controls */
0034     {  66, 0x14 },  {  68, 0x8b },  {  69, 0x12 },  {  70, 0x09 },
0035     {  73, 0x11 },  {  75, 0x60 },  {  76, 0x44 },  {  84, 0x9a },
0036     {  86, 0x38 },  {  91, 0x07 },  {  92, 0x02 },
0037     /* Rx Path Controls */
0038     {  99, 0x50 },  { 101, 0x00 },  { 103, 0xc0 },  { 104, 0x92 },
0039     { 105, 0x3c },  { 106, 0x03 },  { 128, 0x12 },
0040     /* Change RXWI content: Gain Report */
0041     { 142, 0x04 },  { 143, 0x37 },
0042     /* Change RXWI content: Antenna Report */
0043     { 142, 0x03 },  { 143, 0x99 },
0044     /* Calibration Index Register */
0045     /* CCK Receiver Control */
0046     { 160, 0xeb },  { 161, 0xc4 },  { 162, 0x77 },  { 163, 0xf9 },
0047     { 164, 0x88 },  { 165, 0x80 },  { 166, 0xff },  { 167, 0xe4 },
0048     /* Added AGC controls - these AGC/GLRT registers are accessed
0049      * through R195 and R196.
0050      */
0051     { 195, 0x00 },  { 196, 0x00 },
0052     { 195, 0x01 },  { 196, 0x04 },
0053     { 195, 0x02 },  { 196, 0x20 },
0054     { 195, 0x03 },  { 196, 0x0a },
0055     { 195, 0x06 },  { 196, 0x16 },
0056     { 195, 0x07 },  { 196, 0x05 },
0057     { 195, 0x08 },  { 196, 0x37 },
0058     { 195, 0x0a },  { 196, 0x15 },
0059     { 195, 0x0b },  { 196, 0x17 },
0060     { 195, 0x0c },  { 196, 0x06 },
0061     { 195, 0x0d },  { 196, 0x09 },
0062     { 195, 0x0e },  { 196, 0x05 },
0063     { 195, 0x0f },  { 196, 0x09 },
0064     { 195, 0x10 },  { 196, 0x20 },
0065     { 195, 0x20 },  { 196, 0x17 },
0066     { 195, 0x21 },  { 196, 0x06 },
0067     { 195, 0x22 },  { 196, 0x09 },
0068     { 195, 0x23 },  { 196, 0x17 },
0069     { 195, 0x24 },  { 196, 0x06 },
0070     { 195, 0x25 },  { 196, 0x09 },
0071     { 195, 0x26 },  { 196, 0x17 },
0072     { 195, 0x27 },  { 196, 0x06 },
0073     { 195, 0x28 },  { 196, 0x09 },
0074     { 195, 0x29 },  { 196, 0x05 },
0075     { 195, 0x2a },  { 196, 0x09 },
0076     { 195, 0x80 },  { 196, 0x8b },
0077     { 195, 0x81 },  { 196, 0x12 },
0078     { 195, 0x82 },  { 196, 0x09 },
0079     { 195, 0x83 },  { 196, 0x17 },
0080     { 195, 0x84 },  { 196, 0x11 },
0081     { 195, 0x85 },  { 196, 0x00 },
0082     { 195, 0x86 },  { 196, 0x00 },
0083     { 195, 0x87 },  { 196, 0x18 },
0084     { 195, 0x88 },  { 196, 0x60 },
0085     { 195, 0x89 },  { 196, 0x44 },
0086     { 195, 0x8a },  { 196, 0x8b },
0087     { 195, 0x8b },  { 196, 0x8b },
0088     { 195, 0x8c },  { 196, 0x8b },
0089     { 195, 0x8d },  { 196, 0x8b },
0090     { 195, 0x8e },  { 196, 0x09 },
0091     { 195, 0x8f },  { 196, 0x09 },
0092     { 195, 0x90 },  { 196, 0x09 },
0093     { 195, 0x91 },  { 196, 0x09 },
0094     { 195, 0x92 },  { 196, 0x11 },
0095     { 195, 0x93 },  { 196, 0x11 },
0096     { 195, 0x94 },  { 196, 0x11 },
0097     { 195, 0x95 },  { 196, 0x11 },
0098     /* PPAD */
0099     {  47, 0x80 },  {  60, 0x80 },  { 150, 0xd2 },  { 151, 0x32 },
0100     { 152, 0x23 },  { 153, 0x41 },  { 154, 0x00 },  { 155, 0x4f },
0101     { 253, 0x7e },  { 195, 0x30 },  { 196, 0x32 },  { 195, 0x31 },
0102     { 196, 0x23 },  { 195, 0x32 },  { 196, 0x45 },  { 195, 0x35 },
0103     { 196, 0x4a },  { 195, 0x36 },  { 196, 0x5a },  { 195, 0x37 },
0104     { 196, 0x5a },
0105 };
0106
0107 static const struct mt76_reg_pair mac_common_vals[] = {
0108     { MT_LEGACY_BASIC_RATE,     0x0000013f },
0109     { MT_HT_BASIC_RATE,     0x00008003 },
0110     { MT_MAC_SYS_CTRL,      0x00000000 },
0111     { MT_RX_FILTR_CFG,      0x00017f97 },
0112     { MT_BKOFF_SLOT_CFG,        0x00000209 },
0113     { MT_TX_SW_CFG0,        0x00000000 },
0114     { MT_TX_SW_CFG1,        0x00080606 },
0115     { MT_TX_LINK_CFG,       0x00001020 },
0116     { MT_TX_TIMEOUT_CFG,        0x000a2090 },
0117     { MT_MAX_LEN_CFG,       0x00003fff },
0118     { MT_PBF_TX_MAX_PCNT,       0x1fbf1f1f },
0119     { MT_PBF_RX_MAX_PCNT,       0x0000009f },
0120     { MT_TX_RETRY_CFG,      0x47d01f0f },
0121     { MT_AUTO_RSP_CFG,      0x00000013 },
0122     { MT_CCK_PROT_CFG,      0x05740003 },
0123     { MT_OFDM_PROT_CFG,     0x05740003 },
0124     { MT_MM40_PROT_CFG,     0x03f44084 },
0125     { MT_GF20_PROT_CFG,     0x01744004 },
0126     { MT_GF40_PROT_CFG,     0x03f44084 },
0127     { MT_MM20_PROT_CFG,     0x01744004 },
0128     { MT_TXOP_CTRL_CFG,     0x0000583f },
0129     { MT_TX_RTS_CFG,        0x01092b20 },
0130     { MT_EXP_ACK_TIME,      0x002400ca },
0131     { MT_TXOP_HLDR_ET,      0x00000002 },
0132     { MT_XIFS_TIME_CFG,     0x33a41010 },
0133     { MT_PWR_PIN_CFG,       0x00000000 },
0134     { MT_PN_PAD_MODE,       0x00000001 },
0135 };
0136
0137 static const struct mt76_reg_pair mac_chip_vals[] = {
0138     { MT_TSO_CTRL,          0x00006050 },
0139     { MT_BCN_OFFSET(0),     0x18100800 },
0140     { MT_BCN_OFFSET(1),     0x38302820 },
0141     { MT_PBF_SYS_CTRL,      0x00080c00 },
0142     { MT_PBF_CFG,           0x7f723c1f },
0143     { MT_FCE_PSE_CTRL,      0x00000001 },
0144     { MT_PAUSE_ENABLE_CONTROL1, 0x00000000 },
0145     { MT_TX0_RF_GAIN_CORR,      0x003b0005 },
0146     { MT_TX0_RF_GAIN_ATTEN,     0x00006900 },
0147     { MT_TX0_BB_GAIN_ATTEN,     0x00000400 },
0148     { MT_TX_ALC_VGA3,       0x00060006 },
0149     { MT_TX_SW_CFG0,        0x00000402 },
0150     { MT_TX_SW_CFG1,        0x00000000 },
0151     { MT_TX_SW_CFG2,        0x00000000 },
0152     { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
0153     { MT_FCE_CSO,           0x0000030f },
0154     { MT_FCE_PARAMETERS,        0x00256f0f },
0155 };
0156
0157 #endif