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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * (c) Copyright 2002-2010, Ralink Technology, Inc.
0004  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0005  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0006  */
0007 
0008 #include "mt7601u.h"
0009 #include "eeprom.h"
0010 #include "trace.h"
0011 #include "mcu.h"
0012 
0013 #include "initvals.h"
0014 
0015 static void
0016 mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable)
0017 {
0018     int i;
0019 
0020     /* Note: we don't turn off WLAN_CLK because that makes the device
0021      *   not respond properly on the probe path.
0022      *   In case anyone (PSM?) wants to use this function we can
0023      *   bring the clock stuff back and fixup the probe path.
0024      */
0025 
0026     if (enable)
0027         val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
0028             MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
0029     else
0030         val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
0031 
0032     mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
0033     udelay(20);
0034 
0035     if (enable) {
0036         set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
0037     } else {
0038         clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
0039         return;
0040     }
0041 
0042     for (i = 200; i; i--) {
0043         val = mt7601u_rr(dev, MT_CMB_CTRL);
0044 
0045         if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD)
0046             break;
0047 
0048         udelay(20);
0049     }
0050 
0051     /* Note: vendor driver tries to disable/enable wlan here and retry
0052      *       but the code which does it is so buggy it must have never
0053      *       triggered, so don't bother.
0054      */
0055     if (!i)
0056         dev_err(dev->dev, "Error: PLL and XTAL check failed!\n");
0057 }
0058 
0059 static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset)
0060 {
0061     u32 val;
0062 
0063     mutex_lock(&dev->hw_atomic_mutex);
0064 
0065     val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
0066 
0067     if (reset) {
0068         val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
0069         val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
0070 
0071         if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
0072             val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
0073                 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
0074             mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
0075             udelay(20);
0076 
0077             val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
0078                  MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
0079         }
0080     }
0081 
0082     mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
0083     udelay(20);
0084 
0085     mt7601u_set_wlan_state(dev, val, enable);
0086 
0087     mutex_unlock(&dev->hw_atomic_mutex);
0088 }
0089 
0090 static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev)
0091 {
0092     mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
0093                       MT_MAC_SYS_CTRL_RESET_BBP));
0094     mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
0095     msleep(1);
0096     mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
0097 }
0098 
0099 static void mt7601u_init_usb_dma(struct mt7601u_dev *dev)
0100 {
0101     u32 val;
0102 
0103     val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |
0104           FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT,
0105              MT_USB_AGGR_SIZE_LIMIT) |
0106           MT_USB_DMA_CFG_RX_BULK_EN |
0107           MT_USB_DMA_CFG_TX_BULK_EN;
0108     if (dev->in_max_packet == 512)
0109         val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN;
0110     mt7601u_wr(dev, MT_USB_DMA_CFG, val);
0111 
0112     val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
0113     mt7601u_wr(dev, MT_USB_DMA_CFG, val);
0114     val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
0115     mt7601u_wr(dev, MT_USB_DMA_CFG, val);
0116 }
0117 
0118 static int mt7601u_init_bbp(struct mt7601u_dev *dev)
0119 {
0120     int ret;
0121 
0122     ret = mt7601u_wait_bbp_ready(dev);
0123     if (ret)
0124         return ret;
0125 
0126     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals,
0127                       ARRAY_SIZE(bbp_common_vals));
0128     if (ret)
0129         return ret;
0130 
0131     return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals,
0132                        ARRAY_SIZE(bbp_chip_vals));
0133 }
0134 
0135 static void
0136 mt76_init_beacon_offsets(struct mt7601u_dev *dev)
0137 {
0138     u16 base = MT_BEACON_BASE;
0139     u32 regs[4] = {};
0140     int i;
0141 
0142     for (i = 0; i < 16; i++) {
0143         u16 addr = dev->beacon_offsets[i];
0144 
0145         regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
0146     }
0147 
0148     for (i = 0; i < 4; i++)
0149         mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
0150 }
0151 
0152 static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev)
0153 {
0154     int ret;
0155 
0156     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals,
0157                       ARRAY_SIZE(mac_common_vals));
0158     if (ret)
0159         return ret;
0160     ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN,
0161                       mac_chip_vals, ARRAY_SIZE(mac_chip_vals));
0162     if (ret)
0163         return ret;
0164 
0165     mt76_init_beacon_offsets(dev);
0166 
0167     mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
0168 
0169     return 0;
0170 }
0171 
0172 static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev)
0173 {
0174     u32 *vals;
0175     int i, ret;
0176 
0177     vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
0178     if (!vals)
0179         return -ENOMEM;
0180 
0181     for (i = 0; i < N_WCIDS; i++)  {
0182         vals[i * 2] = 0xffffffff;
0183         vals[i * 2 + 1] = 0x00ffffff;
0184     }
0185 
0186     ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE,
0187                        vals, N_WCIDS * 2);
0188     kfree(vals);
0189 
0190     return ret;
0191 }
0192 
0193 static int mt7601u_init_key_mem(struct mt7601u_dev *dev)
0194 {
0195     u32 vals[4] = {};
0196 
0197     return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
0198                     vals, ARRAY_SIZE(vals));
0199 }
0200 
0201 static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev)
0202 {
0203     u32 *vals;
0204     int i, ret;
0205 
0206     vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
0207     if (!vals)
0208         return -ENOMEM;
0209 
0210     for (i = 0; i < N_WCIDS * 2; i++)
0211         vals[i] = 1;
0212 
0213     ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE,
0214                        vals, N_WCIDS * 2);
0215     kfree(vals);
0216 
0217     return ret;
0218 }
0219 
0220 static void mt7601u_reset_counters(struct mt7601u_dev *dev)
0221 {
0222     mt7601u_rr(dev, MT_RX_STA_CNT0);
0223     mt7601u_rr(dev, MT_RX_STA_CNT1);
0224     mt7601u_rr(dev, MT_RX_STA_CNT2);
0225     mt7601u_rr(dev, MT_TX_STA_CNT0);
0226     mt7601u_rr(dev, MT_TX_STA_CNT1);
0227     mt7601u_rr(dev, MT_TX_STA_CNT2);
0228 }
0229 
0230 int mt7601u_mac_start(struct mt7601u_dev *dev)
0231 {
0232     mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
0233 
0234     if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0235                MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000))
0236         return -ETIMEDOUT;
0237 
0238     dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
0239         MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC |
0240         MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP |
0241         MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND |
0242         MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS |
0243         MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL |
0244         MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV;
0245     mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
0246 
0247     mt7601u_wr(dev, MT_MAC_SYS_CTRL,
0248            MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
0249 
0250     if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0251                MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50))
0252         return -ETIMEDOUT;
0253 
0254     return 0;
0255 }
0256 
0257 static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev)
0258 {
0259     int i, ok;
0260 
0261     if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
0262         return;
0263 
0264     mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
0265            MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN |
0266            MT_BEACON_TIME_CFG_BEACON_TX);
0267 
0268     if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
0269         dev_warn(dev->dev, "Warning: TX DMA did not stop!\n");
0270 
0271     /* Page count on TxQ */
0272     i = 200;
0273     while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
0274                (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
0275                (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
0276         msleep(10);
0277 
0278     if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
0279         dev_warn(dev->dev, "Warning: MAC TX did not stop!\n");
0280 
0281     mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
0282                      MT_MAC_SYS_CTRL_ENABLE_TX);
0283 
0284     /* Page count on RxQ */
0285     ok = 0;
0286     i = 200;
0287     while (i--) {
0288         if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
0289             !mt76_rr(dev, 0x0a30) &&
0290             !mt76_rr(dev, 0x0a34)) {
0291             if (ok++ > 5)
0292                 break;
0293             continue;
0294         }
0295         msleep(1);
0296     }
0297 
0298     if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
0299         dev_warn(dev->dev, "Warning: MAC RX did not stop!\n");
0300 
0301     if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
0302         dev_warn(dev->dev, "Warning: RX DMA did not stop!\n");
0303 }
0304 
0305 void mt7601u_mac_stop(struct mt7601u_dev *dev)
0306 {
0307     mt7601u_mac_stop_hw(dev);
0308     flush_delayed_work(&dev->stat_work);
0309     cancel_delayed_work_sync(&dev->stat_work);
0310 }
0311 
0312 static void mt7601u_stop_hardware(struct mt7601u_dev *dev)
0313 {
0314     mt7601u_chip_onoff(dev, false, false);
0315 }
0316 
0317 int mt7601u_init_hardware(struct mt7601u_dev *dev)
0318 {
0319     static const u16 beacon_offsets[16] = {
0320         /* 512 byte per beacon */
0321         0xc000, 0xc200, 0xc400, 0xc600,
0322         0xc800, 0xca00, 0xcc00, 0xce00,
0323         0xd000, 0xd200, 0xd400, 0xd600,
0324         0xd800, 0xda00, 0xdc00, 0xde00
0325     };
0326     int ret;
0327 
0328     dev->beacon_offsets = beacon_offsets;
0329 
0330     mt7601u_chip_onoff(dev, true, false);
0331 
0332     ret = mt7601u_wait_asic_ready(dev);
0333     if (ret)
0334         goto err;
0335     ret = mt7601u_mcu_init(dev);
0336     if (ret)
0337         goto err;
0338 
0339     if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
0340                 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0341                 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) {
0342         ret = -EIO;
0343         goto err;
0344     }
0345 
0346     /* Wait for ASIC ready after FW load. */
0347     ret = mt7601u_wait_asic_ready(dev);
0348     if (ret)
0349         goto err;
0350 
0351     mt7601u_reset_csr_bbp(dev);
0352     mt7601u_init_usb_dma(dev);
0353 
0354     ret = mt7601u_mcu_cmd_init(dev);
0355     if (ret)
0356         goto err;
0357     ret = mt7601u_dma_init(dev);
0358     if (ret)
0359         goto err_mcu;
0360     ret = mt7601u_write_mac_initvals(dev);
0361     if (ret)
0362         goto err_rx;
0363 
0364     if (!mt76_poll_msec(dev, MT_MAC_STATUS,
0365                 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) {
0366         ret = -EIO;
0367         goto err_rx;
0368     }
0369 
0370     ret = mt7601u_init_bbp(dev);
0371     if (ret)
0372         goto err_rx;
0373     ret = mt7601u_init_wcid_mem(dev);
0374     if (ret)
0375         goto err_rx;
0376     ret = mt7601u_init_key_mem(dev);
0377     if (ret)
0378         goto err_rx;
0379     ret = mt7601u_init_wcid_attr_mem(dev);
0380     if (ret)
0381         goto err_rx;
0382 
0383     mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
0384                          MT_BEACON_TIME_CFG_SYNC_MODE |
0385                          MT_BEACON_TIME_CFG_TBTT_EN |
0386                          MT_BEACON_TIME_CFG_BEACON_TX));
0387 
0388     mt7601u_reset_counters(dev);
0389 
0390     mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
0391 
0392     mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
0393            FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |
0394            FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
0395 
0396     ret = mt7601u_eeprom_init(dev);
0397     if (ret)
0398         goto err_rx;
0399 
0400     ret = mt7601u_phy_init(dev);
0401     if (ret)
0402         goto err_rx;
0403 
0404     mt7601u_set_rx_path(dev, 0);
0405     mt7601u_set_tx_dac(dev, 0);
0406 
0407     mt7601u_mac_set_ctrlch(dev, false);
0408     mt7601u_bbp_set_ctrlch(dev, false);
0409     mt7601u_bbp_set_bw(dev, MT_BW_20);
0410 
0411     return 0;
0412 
0413 err_rx:
0414     mt7601u_dma_cleanup(dev);
0415 err_mcu:
0416     mt7601u_mcu_cmd_deinit(dev);
0417 err:
0418     mt7601u_chip_onoff(dev, false, false);
0419     return ret;
0420 }
0421 
0422 void mt7601u_cleanup(struct mt7601u_dev *dev)
0423 {
0424     if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state))
0425         return;
0426 
0427     mt7601u_stop_hardware(dev);
0428     mt7601u_dma_cleanup(dev);
0429     mt7601u_mcu_cmd_deinit(dev);
0430 }
0431 
0432 struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev)
0433 {
0434     struct ieee80211_hw *hw;
0435     struct mt7601u_dev *dev;
0436 
0437     hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops);
0438     if (!hw)
0439         return NULL;
0440 
0441     dev = hw->priv;
0442     dev->dev = pdev;
0443     dev->hw = hw;
0444     mutex_init(&dev->vendor_req_mutex);
0445     mutex_init(&dev->reg_atomic_mutex);
0446     mutex_init(&dev->hw_atomic_mutex);
0447     mutex_init(&dev->mutex);
0448     spin_lock_init(&dev->tx_lock);
0449     spin_lock_init(&dev->rx_lock);
0450     spin_lock_init(&dev->lock);
0451     spin_lock_init(&dev->mac_lock);
0452     spin_lock_init(&dev->con_mon_lock);
0453     atomic_set(&dev->avg_ampdu_len, 1);
0454     skb_queue_head_init(&dev->tx_skb_done);
0455 
0456     dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0);
0457     if (!dev->stat_wq) {
0458         ieee80211_free_hw(hw);
0459         return NULL;
0460     }
0461 
0462     return dev;
0463 }
0464 
0465 #define CHAN2G(_idx, _freq) {           \
0466     .band = NL80211_BAND_2GHZ,      \
0467     .center_freq = (_freq),         \
0468     .hw_value = (_idx),         \
0469     .max_power = 30,            \
0470 }
0471 
0472 static const struct ieee80211_channel mt76_channels_2ghz[] = {
0473     CHAN2G(1, 2412),
0474     CHAN2G(2, 2417),
0475     CHAN2G(3, 2422),
0476     CHAN2G(4, 2427),
0477     CHAN2G(5, 2432),
0478     CHAN2G(6, 2437),
0479     CHAN2G(7, 2442),
0480     CHAN2G(8, 2447),
0481     CHAN2G(9, 2452),
0482     CHAN2G(10, 2457),
0483     CHAN2G(11, 2462),
0484     CHAN2G(12, 2467),
0485     CHAN2G(13, 2472),
0486     CHAN2G(14, 2484),
0487 };
0488 
0489 #define CCK_RATE(_idx, _rate) {                 \
0490     .bitrate = _rate,                   \
0491     .flags = IEEE80211_RATE_SHORT_PREAMBLE,         \
0492     .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx,      \
0493     .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx),  \
0494 }
0495 
0496 #define OFDM_RATE(_idx, _rate) {                \
0497     .bitrate = _rate,                   \
0498     .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx,     \
0499     .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx,   \
0500 }
0501 
0502 static struct ieee80211_rate mt76_rates[] = {
0503     CCK_RATE(0, 10),
0504     CCK_RATE(1, 20),
0505     CCK_RATE(2, 55),
0506     CCK_RATE(3, 110),
0507     OFDM_RATE(0, 60),
0508     OFDM_RATE(1, 90),
0509     OFDM_RATE(2, 120),
0510     OFDM_RATE(3, 180),
0511     OFDM_RATE(4, 240),
0512     OFDM_RATE(5, 360),
0513     OFDM_RATE(6, 480),
0514     OFDM_RATE(7, 540),
0515 };
0516 
0517 static int
0518 mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband,
0519         const struct ieee80211_channel *chan, int n_chan,
0520         struct ieee80211_rate *rates, int n_rates)
0521 {
0522     struct ieee80211_sta_ht_cap *ht_cap;
0523     void *chanlist;
0524     int size;
0525 
0526     size = n_chan * sizeof(*chan);
0527     chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
0528     if (!chanlist)
0529         return -ENOMEM;
0530 
0531     sband->channels = chanlist;
0532     sband->n_channels = n_chan;
0533     sband->bitrates = rates;
0534     sband->n_bitrates = n_rates;
0535 
0536     ht_cap = &sband->ht_cap;
0537     ht_cap->ht_supported = true;
0538     ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
0539               IEEE80211_HT_CAP_GRN_FLD |
0540               IEEE80211_HT_CAP_SGI_20 |
0541               IEEE80211_HT_CAP_SGI_40 |
0542               (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
0543 
0544     ht_cap->mcs.rx_mask[0] = 0xff;
0545     ht_cap->mcs.rx_mask[4] = 0x1;
0546     ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
0547     ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
0548     ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
0549 
0550     dev->chandef.chan = &sband->channels[0];
0551 
0552     return 0;
0553 }
0554 
0555 static int
0556 mt76_init_sband_2g(struct mt7601u_dev *dev)
0557 {
0558     dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
0559                      GFP_KERNEL);
0560     if (!dev->sband_2g)
0561         return -ENOMEM;
0562 
0563     dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
0564 
0565     WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
0566         ARRAY_SIZE(mt76_channels_2ghz));
0567 
0568     return mt76_init_sband(dev, dev->sband_2g,
0569                    &mt76_channels_2ghz[dev->ee->reg.start - 1],
0570                    dev->ee->reg.num,
0571                    mt76_rates, ARRAY_SIZE(mt76_rates));
0572 }
0573 
0574 int mt7601u_register_device(struct mt7601u_dev *dev)
0575 {
0576     struct ieee80211_hw *hw = dev->hw;
0577     struct wiphy *wiphy = hw->wiphy;
0578     int ret;
0579 
0580     /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
0581      * entry no. 1 like it does in the vendor driver.
0582      */
0583     dev->wcid_mask[0] |= 1;
0584 
0585     /* init fake wcid for monitor interfaces */
0586     dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid),
0587                      GFP_KERNEL);
0588     if (!dev->mon_wcid)
0589         return -ENOMEM;
0590     dev->mon_wcid->idx = 0xff;
0591     dev->mon_wcid->hw_key_idx = -1;
0592 
0593     SET_IEEE80211_DEV(hw, dev->dev);
0594 
0595     hw->queues = 4;
0596     ieee80211_hw_set(hw, SIGNAL_DBM);
0597     ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
0598     ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
0599     ieee80211_hw_set(hw, AMPDU_AGGREGATION);
0600     ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
0601     ieee80211_hw_set(hw, MFP_CAPABLE);
0602     hw->max_rates = 1;
0603     hw->max_report_rates = 7;
0604     hw->max_rate_tries = 1;
0605 
0606     hw->sta_data_size = sizeof(struct mt76_sta);
0607     hw->vif_data_size = sizeof(struct mt76_vif);
0608 
0609     SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
0610 
0611     wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
0612     wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
0613     wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
0614 
0615     wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
0616 
0617     ret = mt76_init_sband_2g(dev);
0618     if (ret)
0619         return ret;
0620 
0621     INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work);
0622     INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat);
0623 
0624     ret = ieee80211_register_hw(hw);
0625     if (ret)
0626         return ret;
0627 
0628     mt7601u_init_debugfs(dev);
0629 
0630     return 0;
0631 }
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