mediatek/mt7601u/eeprom.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  */
0006
0007 #ifndef __MT7601U_EEPROM_H
0008 #define __MT7601U_EEPROM_H
0009
0010 struct mt7601u_dev;
0011
0012 #define MT7601U_EE_MAX_VER          0x0d
0013 #define MT7601U_EEPROM_SIZE         256
0014
0015 #define MT7601U_DEFAULT_TX_POWER        6
0016
0017 enum mt76_eeprom_field {
0018     MT_EE_CHIP_ID =             0x00,
0019     MT_EE_VERSION_FAE =         0x02,
0020     MT_EE_VERSION_EE =          0x03,
0021     MT_EE_MAC_ADDR =            0x04,
0022     MT_EE_NIC_CONF_0 =          0x34,
0023     MT_EE_NIC_CONF_1 =          0x36,
0024     MT_EE_COUNTRY_REGION =          0x39,
0025     MT_EE_FREQ_OFFSET =         0x3a,
0026     MT_EE_NIC_CONF_2 =          0x42,
0027
0028     MT_EE_LNA_GAIN =            0x44,
0029     MT_EE_RSSI_OFFSET =         0x46,
0030
0031     MT_EE_TX_POWER_DELTA_BW40 =     0x50,
0032     MT_EE_TX_POWER_OFFSET =         0x52,
0033
0034     MT_EE_TX_TSSI_SLOPE =           0x6e,
0035     MT_EE_TX_TSSI_OFFSET_GROUP =        0x6f,
0036     MT_EE_TX_TSSI_OFFSET =          0x76,
0037
0038     MT_EE_TX_TSSI_TARGET_POWER =        0xd0,
0039     MT_EE_REF_TEMP =            0xd1,
0040     MT_EE_FREQ_OFFSET_COMPENSATION =    0xdb,
0041     MT_EE_TX_POWER_BYRATE_BASE =        0xde,
0042
0043     MT_EE_USAGE_MAP_START =         0x1e0,
0044     MT_EE_USAGE_MAP_END =           0x1fc,
0045 };
0046
0047 #define MT_EE_NIC_CONF_0_RX_PATH        GENMASK(3, 0)
0048 #define MT_EE_NIC_CONF_0_TX_PATH        GENMASK(7, 4)
0049 #define MT_EE_NIC_CONF_0_BOARD_TYPE     GENMASK(13, 12)
0050
0051 #define MT_EE_NIC_CONF_1_HW_RF_CTRL     BIT(0)
0052 #define MT_EE_NIC_CONF_1_TEMP_TX_ALC        BIT(1)
0053 #define MT_EE_NIC_CONF_1_LNA_EXT_2G     BIT(2)
0054 #define MT_EE_NIC_CONF_1_LNA_EXT_5G     BIT(3)
0055 #define MT_EE_NIC_CONF_1_TX_ALC_EN      BIT(13)
0056
0057 #define MT_EE_NIC_CONF_2_RX_STREAM      GENMASK(3, 0)
0058 #define MT_EE_NIC_CONF_2_TX_STREAM      GENMASK(7, 4)
0059 #define MT_EE_NIC_CONF_2_HW_ANTDIV      BIT(8)
0060 #define MT_EE_NIC_CONF_2_XTAL_OPTION        GENMASK(10, 9)
0061 #define MT_EE_NIC_CONF_2_TEMP_DISABLE       BIT(11)
0062 #define MT_EE_NIC_CONF_2_COEX_METHOD        GENMASK(15, 13)
0063
0064 #define MT_EE_TX_POWER_BYRATE(i)        (MT_EE_TX_POWER_BYRATE_BASE + \
0065                          (i) * 4)
0066
0067 #define MT_EFUSE_USAGE_MAP_SIZE         (MT_EE_USAGE_MAP_END -  \
0068                          MT_EE_USAGE_MAP_START + 1)
0069
0070 enum mt7601u_eeprom_access_modes {
0071     MT_EE_READ = 0,
0072     MT_EE_PHYSICAL_READ = 1,
0073 };
0074
0075 struct power_per_rate  {
0076     u8 raw;  /* validated s6 value */
0077     s8 bw20; /* sign-extended int */
0078     s8 bw40; /* sign-extended int */
0079 };
0080
0081 /* Power per rate - one value per two rates */
0082 struct mt7601u_rate_power {
0083     struct power_per_rate cck[2];
0084     struct power_per_rate ofdm[4];
0085     struct power_per_rate ht[4];
0086 };
0087
0088 struct reg_channel_bounds {
0089     u8 start;
0090     u8 num;
0091 };
0092
0093 struct mt7601u_eeprom_params {
0094     bool tssi_enabled;
0095     u8 rf_freq_off;
0096     s8 rssi_offset[2];
0097     s8 ref_temp;
0098     s8 lna_gain;
0099
0100     u8 chan_pwr[14];
0101     struct mt7601u_rate_power power_rate_table;
0102     s8 real_cck_bw20[2];
0103
0104     /* TSSI stuff - only with internal TX ALC */
0105     struct tssi_data {
0106         int tx0_delta_offset;
0107         u8 slope;
0108         u8 offset[3];
0109     } tssi_data;
0110
0111     struct reg_channel_bounds reg;
0112 };
0113
0114 int mt7601u_eeprom_init(struct mt7601u_dev *dev);
0115
0116 static inline u32 s6_validate(u32 reg)
0117 {
0118     WARN_ON(reg & ~GENMASK(5, 0));
0119     return reg & GENMASK(5, 0);
0120 }
0121
0122 static inline int s6_to_int(u32 reg)
0123 {
0124     int s6;
0125
0126     s6 = s6_validate(reg);
0127     if (s6 & BIT(5))
0128         s6 -= BIT(6);
0129
0130     return s6;
0131 }
0132
0133 static inline u32 int_to_s6(int val)
0134 {
0135     if (val < -0x20)
0136         return 0x20;
0137     if (val > 0x1f)
0138         return 0x1f;
0139
0140     return val & 0x3f;
0141 }
0142
0143 #endif