mediatek/mt7601u/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  */
0006
0007 #ifndef __MT7601U_DMA_H
0008 #define __MT7601U_DMA_H
0009
0010 #include <asm/unaligned.h>
0011 #include <linux/skbuff.h>
0012
0013 #define MT_DMA_HDR_LEN          4
0014 #define MT_RX_INFO_LEN          4
0015 #define MT_FCE_INFO_LEN         4
0016 #define MT_DMA_HDRS         (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
0017
0018 /* Common Tx DMA descriptor fields */
0019 #define MT_TXD_INFO_LEN         GENMASK(15, 0)
0020 #define MT_TXD_INFO_D_PORT      GENMASK(29, 27)
0021 #define MT_TXD_INFO_TYPE        GENMASK(31, 30)
0022
0023 enum mt76_msg_port {
0024     WLAN_PORT,
0025     CPU_RX_PORT,
0026     CPU_TX_PORT,
0027     HOST_PORT,
0028     VIRTUAL_CPU_RX_PORT,
0029     VIRTUAL_CPU_TX_PORT,
0030     DISCARD,
0031 };
0032
0033 enum mt76_info_type {
0034     DMA_PACKET,
0035     DMA_COMMAND,
0036 };
0037
0038 /* Tx DMA packet specific flags */
0039 #define MT_TXD_PKT_INFO_NEXT_VLD    BIT(16)
0040 #define MT_TXD_PKT_INFO_TX_BURST    BIT(17)
0041 #define MT_TXD_PKT_INFO_80211       BIT(19)
0042 #define MT_TXD_PKT_INFO_TSO     BIT(20)
0043 #define MT_TXD_PKT_INFO_CSO     BIT(21)
0044 #define MT_TXD_PKT_INFO_WIV     BIT(24)
0045 #define MT_TXD_PKT_INFO_QSEL        GENMASK(26, 25)
0046
0047 enum mt76_qsel {
0048     MT_QSEL_MGMT,
0049     MT_QSEL_HCCA,
0050     MT_QSEL_EDCA,
0051     MT_QSEL_EDCA_2,
0052 };
0053
0054 /* Tx DMA MCU command specific flags */
0055 #define MT_TXD_CMD_INFO_SEQ     GENMASK(19, 16)
0056 #define MT_TXD_CMD_INFO_TYPE        GENMASK(26, 20)
0057
0058 static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb,
0059                        enum mt76_msg_port d_port,
0060                        enum mt76_info_type type, u32 flags)
0061 {
0062     u32 info;
0063
0064     /* Buffer layout:
0065      *  |   4B   | xfer len |      pad       |  4B  |
0066      *  | TXINFO | pkt/cmd  | zero pad to 4B | zero |
0067      *
0068      * length field of TXINFO should be set to 'xfer len'.
0069      */
0070
0071     info = flags |
0072         FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
0073         FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) |
0074         FIELD_PREP(MT_TXD_INFO_TYPE, type);
0075
0076     put_unaligned_le32(info, skb_push(skb, sizeof(info)));
0077     return skb_put_padto(skb, round_up(skb->len, 4) + 4);
0078 }
0079
0080 static inline int
0081 mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
0082 {
0083     flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel);
0084     return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
0085 }
0086
0087 /* Common Rx DMA descriptor fields */
0088 #define MT_RXD_INFO_LEN         GENMASK(13, 0)
0089 #define MT_RXD_INFO_PCIE_INTR       BIT(24)
0090 #define MT_RXD_INFO_QSEL        GENMASK(26, 25)
0091 #define MT_RXD_INFO_PORT        GENMASK(29, 27)
0092 #define MT_RXD_INFO_TYPE        GENMASK(31, 30)
0093
0094 /* Rx DMA packet specific flags */
0095 #define MT_RXD_PKT_INFO_UDP_ERR     BIT(16)
0096 #define MT_RXD_PKT_INFO_TCP_ERR     BIT(17)
0097 #define MT_RXD_PKT_INFO_IP_ERR      BIT(18)
0098 #define MT_RXD_PKT_INFO_PKT_80211   BIT(19)
0099 #define MT_RXD_PKT_INFO_L3L4_DONE   BIT(20)
0100 #define MT_RXD_PKT_INFO_MAC_LEN     GENMASK(23, 21)
0101
0102 /* Rx DMA MCU command specific flags */
0103 #define MT_RXD_CMD_INFO_SELF_GEN    BIT(15)
0104 #define MT_RXD_CMD_INFO_CMD_SEQ     GENMASK(19, 16)
0105 #define MT_RXD_CMD_INFO_EVT_TYPE    GENMASK(23, 20)
0106
0107 enum mt76_evt_type {
0108     CMD_DONE,
0109     CMD_ERROR,
0110     CMD_RETRY,
0111     EVENT_PWR_RSP,
0112     EVENT_WOW_RSP,
0113     EVENT_CARRIER_DETECT_RSP,
0114     EVENT_DFS_DETECT_RSP,
0115 };
0116
0117 #endif