mediatek/mt76/sdio.h

0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2020 MediaTek Inc.
0003  *
0004  * Author: Sean Wang <sean.wang@mediatek.com>
0005  */
0006
0007 #ifndef __MT76S_H
0008 #define __MT76S_H
0009
0010 #define MT_PSE_PAGE_SZ          128
0011
0012 #define MCR_WCIR            0x0000
0013 #define MCR_WHLPCR          0x0004
0014 #define WHLPCR_FW_OWN_REQ_CLR       BIT(9)
0015 #define WHLPCR_FW_OWN_REQ_SET       BIT(8)
0016 #define WHLPCR_IS_DRIVER_OWN        BIT(8)
0017 #define WHLPCR_INT_EN_CLR       BIT(1)
0018 #define WHLPCR_INT_EN_SET       BIT(0)
0019
0020 #define MCR_WSDIOCSR            0x0008
0021 #define MCR_WHCR            0x000C
0022 #define W_INT_CLR_CTRL          BIT(1)
0023 #define RECV_MAILBOX_RD_CLR_EN      BIT(2)
0024 #define WF_SYS_RSTB         BIT(4) /* supported in CONNAC2 */
0025 #define WF_WHOLE_PATH_RSTB      BIT(5) /* supported in CONNAC2 */
0026 #define WF_SDIO_WF_PATH_RSTB        BIT(6) /* supported in CONNAC2 */
0027 #define MAX_HIF_RX_LEN_NUM      GENMASK(13, 8)
0028 #define MAX_HIF_RX_LEN_NUM_CONNAC2  GENMASK(14, 8) /* supported in CONNAC2 */
0029 #define WF_RST_DONE         BIT(15) /* supported in CONNAC2 */
0030 #define RX_ENHANCE_MODE         BIT(16)
0031
0032 #define MCR_WHISR           0x0010
0033 #define MCR_WHIER           0x0014
0034 #define WHIER_D2H_SW_INT        GENMASK(31, 8)
0035 #define WHIER_FW_OWN_BACK_INT_EN    BIT(7)
0036 #define WHIER_ABNORMAL_INT_EN       BIT(6)
0037 #define WHIER_WDT_INT_EN        BIT(5) /* supported in CONNAC2 */
0038 #define WHIER_RX1_DONE_INT_EN       BIT(2)
0039 #define WHIER_RX0_DONE_INT_EN       BIT(1)
0040 #define WHIER_TX_DONE_INT_EN        BIT(0)
0041 #define WHIER_DEFAULT           (WHIER_RX0_DONE_INT_EN  | \
0042                      WHIER_RX1_DONE_INT_EN  | \
0043                      WHIER_TX_DONE_INT_EN   | \
0044                      WHIER_ABNORMAL_INT_EN  | \
0045                      WHIER_D2H_SW_INT)
0046
0047 #define MCR_WASR            0x0020
0048 #define MCR_WSICR           0x0024
0049 #define MCR_WTSR0           0x0028
0050 #define TQ0_CNT             GENMASK(7, 0)
0051 #define TQ1_CNT             GENMASK(15, 8)
0052 #define TQ2_CNT             GENMASK(23, 16)
0053 #define TQ3_CNT             GENMASK(31, 24)
0054
0055 #define MCR_WTSR1           0x002c
0056 #define TQ4_CNT             GENMASK(7, 0)
0057 #define TQ5_CNT             GENMASK(15, 8)
0058 #define TQ6_CNT             GENMASK(23, 16)
0059 #define TQ7_CNT             GENMASK(31, 24)
0060
0061 #define MCR_WTDR1           0x0034
0062 #define MCR_WRDR0           0x0050
0063 #define MCR_WRDR1           0x0054
0064 #define MCR_WRDR(p)         (0x0050 + 4 * (p))
0065 #define MCR_H2DSM0R         0x0070
0066 #define H2D_SW_INT_READ         BIT(16)
0067 #define H2D_SW_INT_WRITE        BIT(17)
0068 #define H2D_SW_INT_CLEAR_MAILBOX_ACK    BIT(22)
0069
0070 #define MCR_H2DSM1R         0x0074
0071 #define MCR_D2HRM0R         0x0078
0072 #define MCR_D2HRM1R         0x007c
0073 #define MCR_D2HRM2R         0x0080
0074 #define MCR_WRPLR           0x0090
0075 #define RX0_PACKET_LENGTH       GENMASK(15, 0)
0076 #define RX1_PACKET_LENGTH       GENMASK(31, 16)
0077
0078 #define MCR_WTMDR           0x00b0
0079 #define MCR_WTMCR           0x00b4
0080 #define MCR_WTMDPCR0            0x00b8
0081 #define MCR_WTMDPCR1            0x00bc
0082 #define MCR_WPLRCR          0x00d4
0083 #define MCR_WSR             0x00D8
0084 #define MCR_CLKIOCR         0x0100
0085 #define MCR_CMDIOCR         0x0104
0086 #define MCR_DAT0IOCR            0x0108
0087 #define MCR_DAT1IOCR            0x010C
0088 #define MCR_DAT2IOCR            0x0110
0089 #define MCR_DAT3IOCR            0x0114
0090 #define MCR_CLKDLYCR            0x0118
0091 #define MCR_CMDDLYCR            0x011C
0092 #define MCR_ODATDLYCR           0x0120
0093 #define MCR_IDATDLYCR1          0x0124
0094 #define MCR_IDATDLYCR2          0x0128
0095 #define MCR_ILCHCR          0x012C
0096 #define MCR_WTQCR0          0x0130
0097 #define MCR_WTQCR1          0x0134
0098 #define MCR_WTQCR2          0x0138
0099 #define MCR_WTQCR3          0x013C
0100 #define MCR_WTQCR4          0x0140
0101 #define MCR_WTQCR5          0x0144
0102 #define MCR_WTQCR6          0x0148
0103 #define MCR_WTQCR7          0x014C
0104 #define MCR_WTQCR(x)                   (0x130 + 4 * (x))
0105 #define TXQ_CNT_L           GENMASK(15, 0)
0106 #define TXQ_CNT_H           GENMASK(31, 16)
0107
0108 #define MCR_SWPCDBGR            0x0154
0109
0110 #define MCR_H2DSM2R         0x0160 /* supported in CONNAC2 */
0111 #define MCR_H2DSM3R         0x0164 /* supported in CONNAC2 */
0112 #define MCR_D2HRM3R         0x0174 /* supported in CONNAC2 */
0113 #define D2HRM3R_IS_DRIVER_OWN       BIT(0)
0114 #define MCR_WTQCR8          0x0190 /* supported in CONNAC2 */
0115 #define MCR_WTQCR9          0x0194 /* supported in CONNAC2 */
0116 #define MCR_WTQCR10         0x0198 /* supported in CONNAC2 */
0117 #define MCR_WTQCR11         0x019C /* supported in CONNAC2 */
0118 #define MCR_WTQCR12         0x01A0 /* supported in CONNAC2 */
0119 #define MCR_WTQCR13         0x01A4 /* supported in CONNAC2 */
0120 #define MCR_WTQCR14         0x01A8 /* supported in CONNAC2 */
0121 #define MCR_WTQCR15         0x01AC /* supported in CONNAC2 */
0122
0123 enum mt76_connac_sdio_ver {
0124     MT76_CONNAC_SDIO,
0125     MT76_CONNAC2_SDIO,
0126 };
0127
0128 struct mt76s_intr {
0129     u32 isr;
0130     u32 *rec_mb;
0131     struct {
0132         u32 *wtqcr;
0133     } tx;
0134     struct {
0135         u16 *len[2];
0136         u16 *num;
0137     } rx;
0138 };
0139
0140 #endif