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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc.
0003  *
0004  */
0005 
0006 #include <linux/kernel.h>
0007 #include <linux/module.h>
0008 #include <linux/pci.h>
0009 
0010 #include "mt7921.h"
0011 #include "mac.h"
0012 #include "mcu.h"
0013 #include "../trace.h"
0014 
0015 static const struct pci_device_id mt7921_pci_device_table[] = {
0016     { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961) },
0017     { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922) },
0018     { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608) },
0019     { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616) },
0020     { },
0021 };
0022 
0023 static bool mt7921_disable_aspm;
0024 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
0025 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
0026 
0027 static void
0028 mt7921_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
0029 {
0030     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0031 
0032     if (q == MT_RXQ_MAIN)
0033         mt7921_irq_enable(dev, MT_INT_RX_DONE_DATA);
0034     else if (q == MT_RXQ_MCU_WA)
0035         mt7921_irq_enable(dev, MT_INT_RX_DONE_WM2);
0036     else
0037         mt7921_irq_enable(dev, MT_INT_RX_DONE_WM);
0038 }
0039 
0040 static irqreturn_t mt7921_irq_handler(int irq, void *dev_instance)
0041 {
0042     struct mt7921_dev *dev = dev_instance;
0043 
0044     mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
0045 
0046     if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
0047         return IRQ_NONE;
0048 
0049     tasklet_schedule(&dev->irq_tasklet);
0050 
0051     return IRQ_HANDLED;
0052 }
0053 
0054 static void mt7921_irq_tasklet(unsigned long data)
0055 {
0056     struct mt7921_dev *dev = (struct mt7921_dev *)data;
0057     u32 intr, mask = 0;
0058 
0059     mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
0060 
0061     intr = mt76_rr(dev, MT_WFDMA0_HOST_INT_STA);
0062     intr &= dev->mt76.mmio.irqmask;
0063     mt76_wr(dev, MT_WFDMA0_HOST_INT_STA, intr);
0064 
0065     trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
0066 
0067     mask |= intr & MT_INT_RX_DONE_ALL;
0068     if (intr & MT_INT_TX_DONE_MCU)
0069         mask |= MT_INT_TX_DONE_MCU;
0070 
0071     if (intr & MT_INT_MCU_CMD) {
0072         u32 intr_sw;
0073 
0074         intr_sw = mt76_rr(dev, MT_MCU_CMD);
0075         /* ack MCU2HOST_SW_INT_STA */
0076         mt76_wr(dev, MT_MCU_CMD, intr_sw);
0077         if (intr_sw & MT_MCU_CMD_WAKE_RX_PCIE) {
0078             mask |= MT_INT_RX_DONE_DATA;
0079             intr |= MT_INT_RX_DONE_DATA;
0080         }
0081     }
0082 
0083     mt76_set_irq_mask(&dev->mt76, MT_WFDMA0_HOST_INT_ENA, mask, 0);
0084 
0085     if (intr & MT_INT_TX_DONE_ALL)
0086         napi_schedule(&dev->mt76.tx_napi);
0087 
0088     if (intr & MT_INT_RX_DONE_WM)
0089         napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
0090 
0091     if (intr & MT_INT_RX_DONE_WM2)
0092         napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
0093 
0094     if (intr & MT_INT_RX_DONE_DATA)
0095         napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
0096 }
0097 
0098 static int mt7921e_init_reset(struct mt7921_dev *dev)
0099 {
0100     return mt7921_wpdma_reset(dev, true);
0101 }
0102 
0103 static void mt7921e_unregister_device(struct mt7921_dev *dev)
0104 {
0105     int i;
0106     struct mt76_connac_pm *pm = &dev->pm;
0107 
0108     cancel_work_sync(&dev->init_work);
0109     mt76_unregister_device(&dev->mt76);
0110     mt76_for_each_q_rx(&dev->mt76, i)
0111         napi_disable(&dev->mt76.napi[i]);
0112     cancel_delayed_work_sync(&pm->ps_work);
0113     cancel_work_sync(&pm->wake_work);
0114 
0115     mt7921_tx_token_put(dev);
0116     mt7921_mcu_drv_pmctrl(dev);
0117     mt7921_dma_cleanup(dev);
0118     mt7921_wfsys_reset(dev);
0119     skb_queue_purge(&dev->mt76.mcu.res_q);
0120 
0121     tasklet_disable(&dev->irq_tasklet);
0122 }
0123 
0124 static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
0125 {
0126     static const struct {
0127         u32 phys;
0128         u32 mapped;
0129         u32 size;
0130     } fixed_map[] = {
0131         { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
0132         { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
0133         { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
0134         { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
0135         { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
0136         { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
0137         { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
0138         { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
0139         { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
0140         { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
0141         { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
0142         { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
0143         { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
0144         { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
0145         { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
0146         { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
0147         { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
0148         { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
0149         { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
0150         { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
0151         { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
0152         { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
0153         { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
0154         { 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
0155         { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
0156         { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
0157         { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
0158         { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
0159         { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
0160         { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
0161         { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
0162         { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
0163         { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
0164         { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
0165         { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
0166         { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
0167         { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
0168         { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
0169         { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
0170         { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
0171         { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
0172         { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
0173         { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
0174     };
0175     int i;
0176 
0177     if (addr < 0x100000)
0178         return addr;
0179 
0180     for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
0181         u32 ofs;
0182 
0183         if (addr < fixed_map[i].phys)
0184             continue;
0185 
0186         ofs = addr - fixed_map[i].phys;
0187         if (ofs > fixed_map[i].size)
0188             continue;
0189 
0190         return fixed_map[i].mapped + ofs;
0191     }
0192 
0193     if ((addr >= 0x18000000 && addr < 0x18c00000) ||
0194         (addr >= 0x70000000 && addr < 0x78000000) ||
0195         (addr >= 0x7c000000 && addr < 0x7c400000))
0196         return mt7921_reg_map_l1(dev, addr);
0197 
0198     dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
0199         addr);
0200 
0201     return 0;
0202 }
0203 
0204 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
0205 {
0206     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0207     u32 addr = __mt7921_reg_addr(dev, offset);
0208 
0209     return dev->bus_ops->rr(mdev, addr);
0210 }
0211 
0212 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
0213 {
0214     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0215     u32 addr = __mt7921_reg_addr(dev, offset);
0216 
0217     dev->bus_ops->wr(mdev, addr, val);
0218 }
0219 
0220 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
0221 {
0222     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0223     u32 addr = __mt7921_reg_addr(dev, offset);
0224 
0225     return dev->bus_ops->rmw(mdev, addr, mask, val);
0226 }
0227 
0228 static int mt7921_pci_probe(struct pci_dev *pdev,
0229                 const struct pci_device_id *id)
0230 {
0231     static const struct mt76_driver_ops drv_ops = {
0232         /* txwi_size = txd size + txp size */
0233         .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
0234         .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
0235         .survey_flags = SURVEY_INFO_TIME_TX |
0236                 SURVEY_INFO_TIME_RX |
0237                 SURVEY_INFO_TIME_BSS_RX,
0238         .token_size = MT7921_TOKEN_SIZE,
0239         .tx_prepare_skb = mt7921e_tx_prepare_skb,
0240         .tx_complete_skb = mt76_connac_tx_complete_skb,
0241         .rx_check = mt7921e_rx_check,
0242         .rx_skb = mt7921e_queue_rx_skb,
0243         .rx_poll_complete = mt7921_rx_poll_complete,
0244         .sta_ps = mt7921_sta_ps,
0245         .sta_add = mt7921_mac_sta_add,
0246         .sta_assoc = mt7921_mac_sta_assoc,
0247         .sta_remove = mt7921_mac_sta_remove,
0248         .update_survey = mt7921_update_channel,
0249     };
0250     static const struct mt7921_hif_ops mt7921_pcie_ops = {
0251         .init_reset = mt7921e_init_reset,
0252         .reset = mt7921e_mac_reset,
0253         .mcu_init = mt7921e_mcu_init,
0254         .drv_own = mt7921e_mcu_drv_pmctrl,
0255         .fw_own = mt7921e_mcu_fw_pmctrl,
0256     };
0257 
0258     struct mt76_bus_ops *bus_ops;
0259     struct mt7921_dev *dev;
0260     struct mt76_dev *mdev;
0261     int ret;
0262 
0263     ret = pcim_enable_device(pdev);
0264     if (ret)
0265         return ret;
0266 
0267     ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
0268     if (ret)
0269         return ret;
0270 
0271     pci_set_master(pdev);
0272 
0273     ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
0274     if (ret < 0)
0275         return ret;
0276 
0277     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
0278     if (ret)
0279         goto err_free_pci_vec;
0280 
0281     if (mt7921_disable_aspm)
0282         mt76_pci_disable_aspm(pdev);
0283 
0284     mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt7921_ops,
0285                  &drv_ops);
0286     if (!mdev) {
0287         ret = -ENOMEM;
0288         goto err_free_pci_vec;
0289     }
0290 
0291     dev = container_of(mdev, struct mt7921_dev, mt76);
0292     dev->hif_ops = &mt7921_pcie_ops;
0293 
0294     mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
0295     tasklet_init(&dev->irq_tasklet, mt7921_irq_tasklet, (unsigned long)dev);
0296 
0297     dev->phy.dev = dev;
0298     dev->phy.mt76 = &dev->mt76.phy;
0299     dev->mt76.phy.priv = &dev->phy;
0300     dev->bus_ops = dev->mt76.bus;
0301     bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
0302                    GFP_KERNEL);
0303     if (!bus_ops) {
0304         ret = -ENOMEM;
0305         goto err_free_dev;
0306     }
0307 
0308     bus_ops->rr = mt7921_rr;
0309     bus_ops->wr = mt7921_wr;
0310     bus_ops->rmw = mt7921_rmw;
0311     dev->mt76.bus = bus_ops;
0312 
0313     ret = __mt7921e_mcu_drv_pmctrl(dev);
0314     if (ret)
0315         goto err_free_dev;
0316 
0317     mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
0318             (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
0319     dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
0320 
0321     mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
0322 
0323     mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
0324 
0325     ret = devm_request_irq(mdev->dev, pdev->irq, mt7921_irq_handler,
0326                    IRQF_SHARED, KBUILD_MODNAME, dev);
0327     if (ret)
0328         goto err_free_dev;
0329 
0330     ret = mt7921_dma_init(dev);
0331     if (ret)
0332         goto err_free_irq;
0333 
0334     ret = mt7921_register_device(dev);
0335     if (ret)
0336         goto err_free_irq;
0337 
0338     return 0;
0339 
0340 err_free_irq:
0341     devm_free_irq(&pdev->dev, pdev->irq, dev);
0342 err_free_dev:
0343     mt76_free_device(&dev->mt76);
0344 err_free_pci_vec:
0345     pci_free_irq_vectors(pdev);
0346 
0347     return ret;
0348 }
0349 
0350 static void mt7921_pci_remove(struct pci_dev *pdev)
0351 {
0352     struct mt76_dev *mdev = pci_get_drvdata(pdev);
0353     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0354 
0355     mt7921e_unregister_device(dev);
0356     devm_free_irq(&pdev->dev, pdev->irq, dev);
0357     mt76_free_device(&dev->mt76);
0358     pci_free_irq_vectors(pdev);
0359 }
0360 
0361 static int mt7921_pci_suspend(struct device *device)
0362 {
0363     struct pci_dev *pdev = to_pci_dev(device);
0364     struct mt76_dev *mdev = pci_get_drvdata(pdev);
0365     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0366     struct mt76_connac_pm *pm = &dev->pm;
0367     int i, err;
0368 
0369     pm->suspended = true;
0370     cancel_delayed_work_sync(&pm->ps_work);
0371     cancel_work_sync(&pm->wake_work);
0372 
0373     err = mt7921_mcu_drv_pmctrl(dev);
0374     if (err < 0)
0375         goto restore_suspend;
0376 
0377     err = mt76_connac_mcu_set_hif_suspend(mdev, true);
0378     if (err)
0379         goto restore_suspend;
0380 
0381     /* always enable deep sleep during suspend to reduce
0382      * power consumption
0383      */
0384     mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
0385 
0386     napi_disable(&mdev->tx_napi);
0387     mt76_worker_disable(&mdev->tx_worker);
0388 
0389     mt76_for_each_q_rx(mdev, i) {
0390         napi_disable(&mdev->napi[i]);
0391     }
0392 
0393     /* wait until dma is idle  */
0394     mt76_poll(dev, MT_WFDMA0_GLO_CFG,
0395           MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
0396           MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
0397 
0398     /* put dma disabled */
0399     mt76_clear(dev, MT_WFDMA0_GLO_CFG,
0400            MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
0401 
0402     /* disable interrupt */
0403     mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
0404     mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
0405     synchronize_irq(pdev->irq);
0406     tasklet_kill(&dev->irq_tasklet);
0407 
0408     err = mt7921_mcu_fw_pmctrl(dev);
0409     if (err)
0410         goto restore_napi;
0411 
0412     if (err)
0413         goto restore_napi;
0414 
0415     return 0;
0416 
0417 restore_napi:
0418     mt76_for_each_q_rx(mdev, i) {
0419         napi_enable(&mdev->napi[i]);
0420     }
0421     napi_enable(&mdev->tx_napi);
0422 
0423     if (!pm->ds_enable)
0424         mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
0425 
0426     mt76_connac_mcu_set_hif_suspend(mdev, false);
0427 
0428 restore_suspend:
0429     pm->suspended = false;
0430 
0431     return err;
0432 }
0433 
0434 static int mt7921_pci_resume(struct device *device)
0435 {
0436     struct pci_dev *pdev = to_pci_dev(device);
0437     struct mt76_dev *mdev = pci_get_drvdata(pdev);
0438     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0439     struct mt76_connac_pm *pm = &dev->pm;
0440     int i, err;
0441 
0442     err = mt7921_mcu_drv_pmctrl(dev);
0443     if (err < 0)
0444         return err;
0445 
0446     mt7921_wpdma_reinit_cond(dev);
0447 
0448     /* enable interrupt */
0449     mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
0450     mt7921_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
0451               MT_INT_MCU_CMD);
0452     mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
0453 
0454     /* put dma enabled */
0455     mt76_set(dev, MT_WFDMA0_GLO_CFG,
0456          MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
0457 
0458     mt76_worker_enable(&mdev->tx_worker);
0459 
0460     local_bh_disable();
0461     mt76_for_each_q_rx(mdev, i) {
0462         napi_enable(&mdev->napi[i]);
0463         napi_schedule(&mdev->napi[i]);
0464     }
0465     napi_enable(&mdev->tx_napi);
0466     napi_schedule(&mdev->tx_napi);
0467     local_bh_enable();
0468 
0469     /* restore previous ds setting */
0470     if (!pm->ds_enable)
0471         mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
0472 
0473     err = mt76_connac_mcu_set_hif_suspend(mdev, false);
0474     if (err)
0475         return err;
0476 
0477     pm->suspended = false;
0478 
0479     return err;
0480 }
0481 
0482 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
0483 
0484 static struct pci_driver mt7921_pci_driver = {
0485     .name       = KBUILD_MODNAME,
0486     .id_table   = mt7921_pci_device_table,
0487     .probe      = mt7921_pci_probe,
0488     .remove     = mt7921_pci_remove,
0489     .driver.pm  = pm_sleep_ptr(&mt7921_pm_ops),
0490 };
0491 
0492 module_pci_driver(mt7921_pci_driver);
0493 
0494 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
0495 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
0496 MODULE_FIRMWARE(MT7921_ROM_PATCH);
0497 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
0498 MODULE_FIRMWARE(MT7922_ROM_PATCH);
0499 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
0500 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
0501 MODULE_LICENSE("Dual BSD/GPL");
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