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0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #include <linux/devcoredump.h>
0005 #include <linux/etherdevice.h>
0006 #include <linux/timekeeping.h>
0007 #include "mt7921.h"
0008 #include "../dma.h"
0009 #include "mac.h"
0010 #include "mcu.h"
0011 
0012 static struct mt76_wcid *mt7921_rx_get_wcid(struct mt7921_dev *dev,
0013                         u16 idx, bool unicast)
0014 {
0015     struct mt7921_sta *sta;
0016     struct mt76_wcid *wcid;
0017 
0018     if (idx >= ARRAY_SIZE(dev->mt76.wcid))
0019         return NULL;
0020 
0021     wcid = rcu_dereference(dev->mt76.wcid[idx]);
0022     if (unicast || !wcid)
0023         return wcid;
0024 
0025     if (!wcid->sta)
0026         return NULL;
0027 
0028     sta = container_of(wcid, struct mt7921_sta, wcid);
0029     if (!sta->vif)
0030         return NULL;
0031 
0032     return &sta->vif->sta.wcid;
0033 }
0034 
0035 void mt7921_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
0036 {
0037 }
0038 EXPORT_SYMBOL_GPL(mt7921_sta_ps);
0039 
0040 bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask)
0041 {
0042     mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
0043          FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
0044 
0045     return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
0046              0, 5000);
0047 }
0048 
0049 void mt7921_mac_sta_poll(struct mt7921_dev *dev)
0050 {
0051     static const u8 ac_to_tid[] = {
0052         [IEEE80211_AC_BE] = 0,
0053         [IEEE80211_AC_BK] = 1,
0054         [IEEE80211_AC_VI] = 4,
0055         [IEEE80211_AC_VO] = 6
0056     };
0057     struct ieee80211_sta *sta;
0058     struct mt7921_sta *msta;
0059     u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
0060     LIST_HEAD(sta_poll_list);
0061     struct rate_info *rate;
0062     int i;
0063 
0064     spin_lock_bh(&dev->sta_poll_lock);
0065     list_splice_init(&dev->sta_poll_list, &sta_poll_list);
0066     spin_unlock_bh(&dev->sta_poll_lock);
0067 
0068     while (true) {
0069         bool clear = false;
0070         u32 addr, val;
0071         u16 idx;
0072         u8 bw;
0073 
0074         spin_lock_bh(&dev->sta_poll_lock);
0075         if (list_empty(&sta_poll_list)) {
0076             spin_unlock_bh(&dev->sta_poll_lock);
0077             break;
0078         }
0079         msta = list_first_entry(&sta_poll_list,
0080                     struct mt7921_sta, poll_list);
0081         list_del_init(&msta->poll_list);
0082         spin_unlock_bh(&dev->sta_poll_lock);
0083 
0084         idx = msta->wcid.idx;
0085         addr = mt7921_mac_wtbl_lmac_addr(idx, MT_WTBL_AC0_CTT_OFFSET);
0086 
0087         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
0088             u32 tx_last = msta->airtime_ac[i];
0089             u32 rx_last = msta->airtime_ac[i + 4];
0090 
0091             msta->airtime_ac[i] = mt76_rr(dev, addr);
0092             msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
0093 
0094             tx_time[i] = msta->airtime_ac[i] - tx_last;
0095             rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
0096 
0097             if ((tx_last | rx_last) & BIT(30))
0098                 clear = true;
0099 
0100             addr += 8;
0101         }
0102 
0103         if (clear) {
0104             mt7921_mac_wtbl_update(dev, idx,
0105                            MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
0106             memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
0107         }
0108 
0109         if (!msta->wcid.sta)
0110             continue;
0111 
0112         sta = container_of((void *)msta, struct ieee80211_sta,
0113                    drv_priv);
0114         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
0115             u8 q = mt76_connac_lmac_mapping(i);
0116             u32 tx_cur = tx_time[q];
0117             u32 rx_cur = rx_time[q];
0118             u8 tid = ac_to_tid[i];
0119 
0120             if (!tx_cur && !rx_cur)
0121                 continue;
0122 
0123             ieee80211_sta_register_airtime(sta, tid, tx_cur,
0124                                rx_cur);
0125         }
0126 
0127         /* We don't support reading GI info from txs packets.
0128          * For accurate tx status reporting and AQL improvement,
0129          * we need to make sure that flags match so polling GI
0130          * from per-sta counters directly.
0131          */
0132         rate = &msta->wcid.rate;
0133         addr = mt7921_mac_wtbl_lmac_addr(idx,
0134                          MT_WTBL_TXRX_CAP_RATE_OFFSET);
0135         val = mt76_rr(dev, addr);
0136 
0137         switch (rate->bw) {
0138         case RATE_INFO_BW_160:
0139             bw = IEEE80211_STA_RX_BW_160;
0140             break;
0141         case RATE_INFO_BW_80:
0142             bw = IEEE80211_STA_RX_BW_80;
0143             break;
0144         case RATE_INFO_BW_40:
0145             bw = IEEE80211_STA_RX_BW_40;
0146             break;
0147         default:
0148             bw = IEEE80211_STA_RX_BW_20;
0149             break;
0150         }
0151 
0152         if (rate->flags & RATE_INFO_FLAGS_HE_MCS) {
0153             u8 offs = MT_WTBL_TXRX_RATE_G2_HE + 2 * bw;
0154 
0155             rate->he_gi = (val & (0x3 << offs)) >> offs;
0156         } else if (rate->flags &
0157                (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) {
0158             if (val & BIT(MT_WTBL_TXRX_RATE_G2 + bw))
0159                 rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
0160             else
0161                 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI;
0162         }
0163     }
0164 }
0165 EXPORT_SYMBOL_GPL(mt7921_mac_sta_poll);
0166 
0167 static void
0168 mt7921_get_status_freq_info(struct mt7921_dev *dev, struct mt76_phy *mphy,
0169                 struct mt76_rx_status *status, u8 chfreq)
0170 {
0171     if (!test_bit(MT76_HW_SCANNING, &mphy->state) &&
0172         !test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) &&
0173         !test_bit(MT76_STATE_ROC, &mphy->state)) {
0174         status->freq = mphy->chandef.chan->center_freq;
0175         status->band = mphy->chandef.chan->band;
0176         return;
0177     }
0178 
0179     if (chfreq > 180) {
0180         status->band = NL80211_BAND_6GHZ;
0181         chfreq = (chfreq - 181) * 4 + 1;
0182     } else if (chfreq > 14) {
0183         status->band = NL80211_BAND_5GHZ;
0184     } else {
0185         status->band = NL80211_BAND_2GHZ;
0186     }
0187     status->freq = ieee80211_channel_to_frequency(chfreq, status->band);
0188 }
0189 
0190 static void
0191 mt7921_mac_rssi_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
0192 {
0193     struct sk_buff *skb = priv;
0194     struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
0195     struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv;
0196     struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb);
0197 
0198     if (status->signal > 0)
0199         return;
0200 
0201     if (!ether_addr_equal(vif->addr, hdr->addr1))
0202         return;
0203 
0204     ewma_rssi_add(&mvif->rssi, -status->signal);
0205 }
0206 
0207 static void
0208 mt7921_mac_assoc_rssi(struct mt7921_dev *dev, struct sk_buff *skb)
0209 {
0210     struct ieee80211_hdr *hdr = mt76_skb_get_hdr(skb);
0211 
0212     if (!ieee80211_is_assoc_resp(hdr->frame_control) &&
0213         !ieee80211_is_auth(hdr->frame_control))
0214         return;
0215 
0216     ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
0217         IEEE80211_IFACE_ITER_RESUME_ALL,
0218         mt7921_mac_rssi_iter, skb);
0219 }
0220 
0221 static int
0222 mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
0223 {
0224     u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
0225     struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
0226     bool hdr_trans, unicast, insert_ccmp_hdr = false;
0227     u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info;
0228     u16 hdr_gap;
0229     __le32 *rxv = NULL, *rxd = (__le32 *)skb->data;
0230     struct mt76_phy *mphy = &dev->mt76.phy;
0231     struct mt7921_phy *phy = &dev->phy;
0232     struct ieee80211_supported_band *sband;
0233     u32 rxd0 = le32_to_cpu(rxd[0]);
0234     u32 rxd1 = le32_to_cpu(rxd[1]);
0235     u32 rxd2 = le32_to_cpu(rxd[2]);
0236     u32 rxd3 = le32_to_cpu(rxd[3]);
0237     u32 rxd4 = le32_to_cpu(rxd[4]);
0238     struct mt7921_sta *msta;
0239     u16 seq_ctrl = 0;
0240     __le16 fc = 0;
0241     u8 mode = 0;
0242     int i, idx;
0243 
0244     memset(status, 0, sizeof(*status));
0245 
0246     if (rxd1 & MT_RXD1_NORMAL_BAND_IDX)
0247         return -EINVAL;
0248 
0249     if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
0250         return -EINVAL;
0251 
0252     if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
0253         return -EINVAL;
0254 
0255     hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS;
0256     if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM))
0257         return -EINVAL;
0258 
0259     /* ICV error or CCMP/BIP/WPI MIC error */
0260     if (rxd1 & MT_RXD1_NORMAL_ICV_ERR)
0261         status->flag |= RX_FLAG_ONLY_MONITOR;
0262 
0263     chfreq = FIELD_GET(MT_RXD3_NORMAL_CH_FREQ, rxd3);
0264     unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
0265     idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
0266     status->wcid = mt7921_rx_get_wcid(dev, idx, unicast);
0267 
0268     if (status->wcid) {
0269         msta = container_of(status->wcid, struct mt7921_sta, wcid);
0270         spin_lock_bh(&dev->sta_poll_lock);
0271         if (list_empty(&msta->poll_list))
0272             list_add_tail(&msta->poll_list, &dev->sta_poll_list);
0273         spin_unlock_bh(&dev->sta_poll_lock);
0274     }
0275 
0276     mt7921_get_status_freq_info(dev, mphy, status, chfreq);
0277 
0278     switch (status->band) {
0279     case NL80211_BAND_5GHZ:
0280         sband = &mphy->sband_5g.sband;
0281         break;
0282     case NL80211_BAND_6GHZ:
0283         sband = &mphy->sband_6g.sband;
0284         break;
0285     default:
0286         sband = &mphy->sband_2g.sband;
0287         break;
0288     }
0289 
0290     if (!sband->channels)
0291         return -EINVAL;
0292 
0293     if ((rxd0 & csum_mask) == csum_mask)
0294         skb->ip_summed = CHECKSUM_UNNECESSARY;
0295 
0296     if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
0297         status->flag |= RX_FLAG_FAILED_FCS_CRC;
0298 
0299     if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
0300         status->flag |= RX_FLAG_MMIC_ERROR;
0301 
0302     if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
0303         !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
0304         status->flag |= RX_FLAG_DECRYPTED;
0305         status->flag |= RX_FLAG_IV_STRIPPED;
0306         status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
0307     }
0308 
0309     remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
0310 
0311     if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
0312         return -EINVAL;
0313 
0314     rxd += 6;
0315     if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
0316         u32 v0 = le32_to_cpu(rxd[0]);
0317         u32 v2 = le32_to_cpu(rxd[2]);
0318 
0319         fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
0320         seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
0321         qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2);
0322 
0323         rxd += 4;
0324         if ((u8 *)rxd - skb->data >= skb->len)
0325             return -EINVAL;
0326     }
0327 
0328     if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
0329         u8 *data = (u8 *)rxd;
0330 
0331         if (status->flag & RX_FLAG_DECRYPTED) {
0332             switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) {
0333             case MT_CIPHER_AES_CCMP:
0334             case MT_CIPHER_CCMP_CCX:
0335             case MT_CIPHER_CCMP_256:
0336                 insert_ccmp_hdr =
0337                     FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
0338                 fallthrough;
0339             case MT_CIPHER_TKIP:
0340             case MT_CIPHER_TKIP_NO_MIC:
0341             case MT_CIPHER_GCMP:
0342             case MT_CIPHER_GCMP_256:
0343                 status->iv[0] = data[5];
0344                 status->iv[1] = data[4];
0345                 status->iv[2] = data[3];
0346                 status->iv[3] = data[2];
0347                 status->iv[4] = data[1];
0348                 status->iv[5] = data[0];
0349                 break;
0350             default:
0351                 break;
0352             }
0353         }
0354         rxd += 4;
0355         if ((u8 *)rxd - skb->data >= skb->len)
0356             return -EINVAL;
0357     }
0358 
0359     if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
0360         status->timestamp = le32_to_cpu(rxd[0]);
0361         status->flag |= RX_FLAG_MACTIME_START;
0362 
0363         if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
0364             status->flag |= RX_FLAG_AMPDU_DETAILS;
0365 
0366             /* all subframes of an A-MPDU have the same timestamp */
0367             if (phy->rx_ampdu_ts != status->timestamp) {
0368                 if (!++phy->ampdu_ref)
0369                     phy->ampdu_ref++;
0370             }
0371             phy->rx_ampdu_ts = status->timestamp;
0372 
0373             status->ampdu_ref = phy->ampdu_ref;
0374         }
0375 
0376         rxd += 2;
0377         if ((u8 *)rxd - skb->data >= skb->len)
0378             return -EINVAL;
0379     }
0380 
0381     /* RXD Group 3 - P-RXV */
0382     if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
0383         u32 v0, v1;
0384         int ret;
0385 
0386         rxv = rxd;
0387         rxd += 2;
0388         if ((u8 *)rxd - skb->data >= skb->len)
0389             return -EINVAL;
0390 
0391         v0 = le32_to_cpu(rxv[0]);
0392         v1 = le32_to_cpu(rxv[1]);
0393 
0394         if (v0 & MT_PRXV_HT_AD_CODE)
0395             status->enc_flags |= RX_ENC_FLAG_LDPC;
0396 
0397         status->chains = mphy->antenna_mask;
0398         status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
0399         status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
0400         status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
0401         status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
0402         status->signal = -128;
0403         for (i = 0; i < hweight8(mphy->antenna_mask); i++) {
0404             if (!(status->chains & BIT(i)) ||
0405                 status->chain_signal[i] >= 0)
0406                 continue;
0407 
0408             status->signal = max(status->signal,
0409                          status->chain_signal[i]);
0410         }
0411 
0412         ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, sband,
0413                             rxv, &mode);
0414         if (ret < 0)
0415             return ret;
0416 
0417         if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
0418             rxd += 18;
0419             if ((u8 *)rxd - skb->data >= skb->len)
0420                 return -EINVAL;
0421         }
0422     }
0423 
0424     amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4);
0425     status->amsdu = !!amsdu_info;
0426     if (status->amsdu) {
0427         status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
0428         status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
0429     }
0430 
0431     hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad;
0432     if (hdr_trans && ieee80211_has_morefrags(fc)) {
0433         struct ieee80211_vif *vif;
0434         int err;
0435 
0436         if (!msta || !msta->vif)
0437             return -EINVAL;
0438 
0439         vif = container_of((void *)msta->vif, struct ieee80211_vif,
0440                    drv_priv);
0441         err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap);
0442         if (err)
0443             return err;
0444 
0445         hdr_trans = false;
0446     } else {
0447         skb_pull(skb, hdr_gap);
0448         if (!hdr_trans && status->amsdu) {
0449             memmove(skb->data + 2, skb->data,
0450                 ieee80211_get_hdrlen_from_skb(skb));
0451             skb_pull(skb, 2);
0452         }
0453     }
0454 
0455     if (!hdr_trans) {
0456         struct ieee80211_hdr *hdr;
0457 
0458         if (insert_ccmp_hdr) {
0459             u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
0460 
0461             mt76_insert_ccmp_hdr(skb, key_id);
0462         }
0463 
0464         hdr = mt76_skb_get_hdr(skb);
0465         fc = hdr->frame_control;
0466         if (ieee80211_is_data_qos(fc)) {
0467             seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
0468             qos_ctl = *ieee80211_get_qos_ctl(hdr);
0469         }
0470     } else {
0471         status->flag |= RX_FLAG_8023;
0472     }
0473 
0474     mt7921_mac_assoc_rssi(dev, skb);
0475 
0476     if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023))
0477         mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode);
0478 
0479     if (!status->wcid || !ieee80211_is_data_qos(fc))
0480         return 0;
0481 
0482     status->aggr = unicast && !ieee80211_is_qos_nullfunc(fc);
0483     status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
0484     status->qos_ctl = qos_ctl;
0485 
0486     return 0;
0487 }
0488 
0489 void mt7921_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
0490 {
0491     struct mt7921_sta *msta;
0492     u16 fc, tid;
0493     u32 val;
0494 
0495     if (!sta || !(sta->deflink.ht_cap.ht_supported || sta->deflink.he_cap.has_he))
0496         return;
0497 
0498     tid = le32_get_bits(txwi[1], MT_TXD1_TID);
0499     if (tid >= 6) /* skip VO queue */
0500         return;
0501 
0502     val = le32_to_cpu(txwi[2]);
0503     fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
0504          FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
0505     if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
0506         return;
0507 
0508     msta = (struct mt7921_sta *)sta->drv_priv;
0509     if (!test_and_set_bit(tid, &msta->ampdu_state))
0510         ieee80211_start_tx_ba_session(sta, tid, 0);
0511 }
0512 EXPORT_SYMBOL_GPL(mt7921_tx_check_aggr);
0513 
0514 void mt7921_mac_add_txs(struct mt7921_dev *dev, void *data)
0515 {
0516     struct mt7921_sta *msta = NULL;
0517     struct mt76_wcid *wcid;
0518     __le32 *txs_data = data;
0519     u16 wcidx;
0520     u8 pid;
0521 
0522     if (le32_get_bits(txs_data[0], MT_TXS0_TXS_FORMAT) > 1)
0523         return;
0524 
0525     wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
0526     pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
0527 
0528     if (pid < MT_PACKET_ID_FIRST)
0529         return;
0530 
0531     if (wcidx >= MT7921_WTBL_SIZE)
0532         return;
0533 
0534     rcu_read_lock();
0535 
0536     wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
0537     if (!wcid)
0538         goto out;
0539 
0540     msta = container_of(wcid, struct mt7921_sta, wcid);
0541 
0542     mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data,
0543                      &msta->stats);
0544     if (!wcid->sta)
0545         goto out;
0546 
0547     spin_lock_bh(&dev->sta_poll_lock);
0548     if (list_empty(&msta->poll_list))
0549         list_add_tail(&msta->poll_list, &dev->sta_poll_list);
0550     spin_unlock_bh(&dev->sta_poll_lock);
0551 
0552 out:
0553     rcu_read_unlock();
0554 }
0555 EXPORT_SYMBOL_GPL(mt7921_mac_add_txs);
0556 
0557 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
0558              struct sk_buff *skb)
0559 {
0560     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0561     __le32 *rxd = (__le32 *)skb->data;
0562     __le32 *end = (__le32 *)&skb->data[skb->len];
0563     enum rx_pkt_type type;
0564     u16 flag;
0565 
0566     type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE);
0567     flag = le32_get_bits(rxd[0], MT_RXD0_PKT_FLAG);
0568 
0569     if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
0570         type = PKT_TYPE_NORMAL_MCU;
0571 
0572     switch (type) {
0573     case PKT_TYPE_RX_EVENT:
0574         mt7921_mcu_rx_event(dev, skb);
0575         break;
0576     case PKT_TYPE_TXS:
0577         for (rxd += 2; rxd + 8 <= end; rxd += 8)
0578             mt7921_mac_add_txs(dev, rxd);
0579         dev_kfree_skb(skb);
0580         break;
0581     case PKT_TYPE_NORMAL_MCU:
0582     case PKT_TYPE_NORMAL:
0583         if (!mt7921_mac_fill_rx(dev, skb)) {
0584             mt76_rx(&dev->mt76, q, skb);
0585             return;
0586         }
0587         fallthrough;
0588     default:
0589         dev_kfree_skb(skb);
0590         break;
0591     }
0592 }
0593 EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb);
0594 
0595 void mt7921_mac_reset_counters(struct mt7921_phy *phy)
0596 {
0597     struct mt7921_dev *dev = phy->dev;
0598     int i;
0599 
0600     for (i = 0; i < 4; i++) {
0601         mt76_rr(dev, MT_TX_AGG_CNT(0, i));
0602         mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
0603     }
0604 
0605     dev->mt76.phy.survey_time = ktime_get_boottime();
0606     memset(&dev->mt76.aggr_stats[0], 0, sizeof(dev->mt76.aggr_stats) / 2);
0607 
0608     /* reset airtime counters */
0609     mt76_rr(dev, MT_MIB_SDR9(0));
0610     mt76_rr(dev, MT_MIB_SDR36(0));
0611     mt76_rr(dev, MT_MIB_SDR37(0));
0612 
0613     mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
0614     mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
0615 }
0616 
0617 void mt7921_mac_set_timing(struct mt7921_phy *phy)
0618 {
0619     s16 coverage_class = phy->coverage_class;
0620     struct mt7921_dev *dev = phy->dev;
0621     u32 val, reg_offset;
0622     u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
0623           FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
0624     u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
0625            FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
0626     bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ;
0627     int sifs = is_2ghz ? 10 : 16, offset;
0628 
0629     if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
0630         return;
0631 
0632     mt76_set(dev, MT_ARB_SCR(0),
0633          MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
0634     udelay(1);
0635 
0636     offset = 3 * coverage_class;
0637     reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
0638              FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
0639 
0640     mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset);
0641     mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset);
0642     mt76_wr(dev, MT_TMAC_ICR0(0),
0643         FIELD_PREP(MT_IFS_EIFS, 360) |
0644         FIELD_PREP(MT_IFS_RIFS, 2) |
0645         FIELD_PREP(MT_IFS_SIFS, sifs) |
0646         FIELD_PREP(MT_IFS_SLOT, phy->slottime));
0647 
0648     if (phy->slottime < 20 || !is_2ghz)
0649         val = MT7921_CFEND_RATE_DEFAULT;
0650     else
0651         val = MT7921_CFEND_RATE_11B;
0652 
0653     mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val);
0654     mt76_clear(dev, MT_ARB_SCR(0),
0655            MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
0656 }
0657 
0658 static u8
0659 mt7921_phy_get_nf(struct mt7921_phy *phy, int idx)
0660 {
0661     return 0;
0662 }
0663 
0664 static void
0665 mt7921_phy_update_channel(struct mt76_phy *mphy, int idx)
0666 {
0667     struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76);
0668     struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv;
0669     struct mt76_channel_state *state;
0670     u64 busy_time, tx_time, rx_time, obss_time;
0671     int nf;
0672 
0673     busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
0674                    MT_MIB_SDR9_BUSY_MASK);
0675     tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
0676                  MT_MIB_SDR36_TXTIME_MASK);
0677     rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
0678                  MT_MIB_SDR37_RXTIME_MASK);
0679     obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx),
0680                    MT_MIB_OBSSTIME_MASK);
0681 
0682     nf = mt7921_phy_get_nf(phy, idx);
0683     if (!phy->noise)
0684         phy->noise = nf << 4;
0685     else if (nf)
0686         phy->noise += nf - (phy->noise >> 4);
0687 
0688     state = mphy->chan_state;
0689     state->cc_busy += busy_time;
0690     state->cc_tx += tx_time;
0691     state->cc_rx += rx_time + obss_time;
0692     state->cc_bss_rx += rx_time;
0693     state->noise = -(phy->noise >> 4);
0694 }
0695 
0696 void mt7921_update_channel(struct mt76_phy *mphy)
0697 {
0698     struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76);
0699 
0700     if (mt76_connac_pm_wake(mphy, &dev->pm))
0701         return;
0702 
0703     mt7921_phy_update_channel(mphy, 0);
0704     /* reset obss airtime */
0705     mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
0706 
0707     mt76_connac_power_save_sched(mphy, &dev->pm);
0708 }
0709 EXPORT_SYMBOL_GPL(mt7921_update_channel);
0710 
0711 static void
0712 mt7921_vif_connect_iter(void *priv, u8 *mac,
0713             struct ieee80211_vif *vif)
0714 {
0715     struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv;
0716     struct mt7921_dev *dev = mvif->phy->dev;
0717     struct ieee80211_hw *hw = mt76_hw(dev);
0718 
0719     if (vif->type == NL80211_IFTYPE_STATION)
0720         ieee80211_disconnect(vif, true);
0721 
0722     mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true);
0723     mt7921_mcu_set_tx(dev, vif);
0724 
0725     if (vif->type == NL80211_IFTYPE_AP) {
0726         mt76_connac_mcu_uni_add_bss(dev->phy.mt76, vif, &mvif->sta.wcid,
0727                         true);
0728         mt7921_mcu_sta_update(dev, NULL, vif, true,
0729                       MT76_STA_INFO_STATE_NONE);
0730         mt7921_mcu_uni_add_beacon_offload(dev, hw, vif, true);
0731     }
0732 }
0733 
0734 /* system error recovery */
0735 void mt7921_mac_reset_work(struct work_struct *work)
0736 {
0737     struct mt7921_dev *dev = container_of(work, struct mt7921_dev,
0738                           reset_work);
0739     struct ieee80211_hw *hw = mt76_hw(dev);
0740     struct mt76_connac_pm *pm = &dev->pm;
0741     int i, ret;
0742 
0743     dev_dbg(dev->mt76.dev, "chip reset\n");
0744     dev->hw_full_reset = true;
0745     ieee80211_stop_queues(hw);
0746 
0747     cancel_delayed_work_sync(&dev->mphy.mac_work);
0748     cancel_delayed_work_sync(&pm->ps_work);
0749     cancel_work_sync(&pm->wake_work);
0750 
0751     for (i = 0; i < 10; i++) {
0752         mutex_lock(&dev->mt76.mutex);
0753         ret = mt7921_dev_reset(dev);
0754         mutex_unlock(&dev->mt76.mutex);
0755 
0756         if (!ret)
0757             break;
0758     }
0759 
0760     if (i == 10)
0761         dev_err(dev->mt76.dev, "chip reset failed\n");
0762 
0763     if (test_and_clear_bit(MT76_HW_SCANNING, &dev->mphy.state)) {
0764         struct cfg80211_scan_info info = {
0765             .aborted = true,
0766         };
0767 
0768         ieee80211_scan_completed(dev->mphy.hw, &info);
0769     }
0770 
0771     dev->hw_full_reset = false;
0772     pm->suspended = false;
0773     ieee80211_wake_queues(hw);
0774     ieee80211_iterate_active_interfaces(hw,
0775                         IEEE80211_IFACE_ITER_RESUME_ALL,
0776                         mt7921_vif_connect_iter, NULL);
0777     mt76_connac_power_save_sched(&dev->mt76.phy, pm);
0778 }
0779 
0780 void mt7921_reset(struct mt76_dev *mdev)
0781 {
0782     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
0783 
0784     if (!dev->hw_init_done)
0785         return;
0786 
0787     if (dev->hw_full_reset)
0788         return;
0789 
0790     queue_work(dev->mt76.wq, &dev->reset_work);
0791 }
0792 
0793 void mt7921_mac_update_mib_stats(struct mt7921_phy *phy)
0794 {
0795     struct mt7921_dev *dev = phy->dev;
0796     struct mib_stats *mib = &phy->mib;
0797     int i, aggr0 = 0, aggr1;
0798     u32 val;
0799 
0800     mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
0801                        MT_MIB_SDR3_FCS_ERR_MASK);
0802     mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0),
0803                         MT_MIB_ACK_FAIL_COUNT_MASK);
0804     mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0),
0805                        MT_MIB_BA_FAIL_COUNT_MASK);
0806     mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0),
0807                        MT_MIB_RTS_COUNT_MASK);
0808     mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0),
0809                            MT_MIB_RTS_FAIL_COUNT_MASK);
0810 
0811     mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0));
0812     mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0));
0813     mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0));
0814 
0815     val = mt76_rr(dev, MT_MIB_SDR32(0));
0816     mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val);
0817     mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR9_IBF_CNT_MASK, val);
0818 
0819     val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0));
0820     mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, val);
0821     mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, val);
0822 
0823     val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0));
0824     mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, val);
0825     mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, val);
0826     mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, val);
0827     mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, val);
0828 
0829     mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0));
0830     mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0));
0831     mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0));
0832     mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0));
0833 
0834     for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
0835         val = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
0836         mib->tx_amsdu[i] += val;
0837         mib->tx_amsdu_cnt += val;
0838     }
0839 
0840     for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
0841         u32 val2;
0842 
0843         val = mt76_rr(dev, MT_TX_AGG_CNT(0, i));
0844         val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
0845 
0846         dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
0847         dev->mt76.aggr_stats[aggr0++] += val >> 16;
0848         dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff;
0849         dev->mt76.aggr_stats[aggr1++] += val2 >> 16;
0850     }
0851 }
0852 
0853 void mt7921_mac_work(struct work_struct *work)
0854 {
0855     struct mt7921_phy *phy;
0856     struct mt76_phy *mphy;
0857 
0858     mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
0859                            mac_work.work);
0860     phy = mphy->priv;
0861 
0862     mt7921_mutex_acquire(phy->dev);
0863 
0864     mt76_update_survey(mphy);
0865     if (++mphy->mac_work_count == 2) {
0866         mphy->mac_work_count = 0;
0867 
0868         mt7921_mac_update_mib_stats(phy);
0869     }
0870 
0871     mt7921_mutex_release(phy->dev);
0872 
0873     mt76_tx_status_check(mphy->dev, false);
0874     ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work,
0875                      MT7921_WATCHDOG_TIME);
0876 }
0877 
0878 void mt7921_pm_wake_work(struct work_struct *work)
0879 {
0880     struct mt7921_dev *dev;
0881     struct mt76_phy *mphy;
0882 
0883     dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev,
0884                         pm.wake_work);
0885     mphy = dev->phy.mt76;
0886 
0887     if (!mt7921_mcu_drv_pmctrl(dev)) {
0888         struct mt76_dev *mdev = &dev->mt76;
0889         int i;
0890 
0891         if (mt76_is_sdio(mdev)) {
0892             mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
0893             mt76_worker_schedule(&mdev->sdio.txrx_worker);
0894         } else {
0895             local_bh_disable();
0896             mt76_for_each_q_rx(mdev, i)
0897                 napi_schedule(&mdev->napi[i]);
0898             local_bh_enable();
0899             mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
0900             mt76_connac_tx_cleanup(mdev);
0901         }
0902         if (test_bit(MT76_STATE_RUNNING, &mphy->state))
0903             ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
0904                              MT7921_WATCHDOG_TIME);
0905     }
0906 
0907     ieee80211_wake_queues(mphy->hw);
0908     wake_up(&dev->pm.wait);
0909 }
0910 
0911 void mt7921_pm_power_save_work(struct work_struct *work)
0912 {
0913     struct mt7921_dev *dev;
0914     unsigned long delta;
0915     struct mt76_phy *mphy;
0916 
0917     dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev,
0918                         pm.ps_work.work);
0919     mphy = dev->phy.mt76;
0920 
0921     delta = dev->pm.idle_timeout;
0922     if (test_bit(MT76_HW_SCANNING, &mphy->state) ||
0923         test_bit(MT76_HW_SCHED_SCANNING, &mphy->state) ||
0924         dev->fw_assert)
0925         goto out;
0926 
0927     if (mutex_is_locked(&dev->mt76.mutex))
0928         /* if mt76 mutex is held we should not put the device
0929          * to sleep since we are currently accessing device
0930          * register map. We need to wait for the next power_save
0931          * trigger.
0932          */
0933         goto out;
0934 
0935     if (time_is_after_jiffies(dev->pm.last_activity + delta)) {
0936         delta = dev->pm.last_activity + delta - jiffies;
0937         goto out;
0938     }
0939 
0940     if (!mt7921_mcu_fw_pmctrl(dev)) {
0941         cancel_delayed_work_sync(&mphy->mac_work);
0942         return;
0943     }
0944 out:
0945     queue_delayed_work(dev->mt76.wq, &dev->pm.ps_work, delta);
0946 }
0947 
0948 void mt7921_coredump_work(struct work_struct *work)
0949 {
0950     struct mt7921_dev *dev;
0951     char *dump, *data;
0952 
0953     dev = (struct mt7921_dev *)container_of(work, struct mt7921_dev,
0954                         coredump.work.work);
0955 
0956     if (time_is_after_jiffies(dev->coredump.last_activity +
0957                   4 * MT76_CONNAC_COREDUMP_TIMEOUT)) {
0958         queue_delayed_work(dev->mt76.wq, &dev->coredump.work,
0959                    MT76_CONNAC_COREDUMP_TIMEOUT);
0960         return;
0961     }
0962 
0963     dump = vzalloc(MT76_CONNAC_COREDUMP_SZ);
0964     data = dump;
0965 
0966     while (true) {
0967         struct sk_buff *skb;
0968 
0969         spin_lock_bh(&dev->mt76.lock);
0970         skb = __skb_dequeue(&dev->coredump.msg_list);
0971         spin_unlock_bh(&dev->mt76.lock);
0972 
0973         if (!skb)
0974             break;
0975 
0976         skb_pull(skb, sizeof(struct mt76_connac2_mcu_rxd));
0977         if (!dump || data + skb->len - dump > MT76_CONNAC_COREDUMP_SZ) {
0978             dev_kfree_skb(skb);
0979             continue;
0980         }
0981 
0982         memcpy(data, skb->data, skb->len);
0983         data += skb->len;
0984 
0985         dev_kfree_skb(skb);
0986     }
0987 
0988     if (dump)
0989         dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ,
0990                   GFP_KERNEL);
0991 
0992     mt7921_reset(&dev->mt76);
0993 }
0994 
0995 /* usb_sdio */
0996 static void
0997 mt7921_usb_sdio_write_txwi(struct mt7921_dev *dev, struct mt76_wcid *wcid,
0998                enum mt76_txq_id qid, struct ieee80211_sta *sta,
0999                struct ieee80211_key_conf *key, int pid,
1000                struct sk_buff *skb)
1001 {
1002     __le32 *txwi = (__le32 *)(skb->data - MT_SDIO_TXD_SIZE);
1003 
1004     memset(txwi, 0, MT_SDIO_TXD_SIZE);
1005     mt76_connac2_mac_write_txwi(&dev->mt76, txwi, skb, wcid, key, pid, qid, 0);
1006     skb_push(skb, MT_SDIO_TXD_SIZE);
1007 }
1008 
1009 int mt7921_usb_sdio_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1010                    enum mt76_txq_id qid, struct mt76_wcid *wcid,
1011                    struct ieee80211_sta *sta,
1012                    struct mt76_tx_info *tx_info)
1013 {
1014     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1015     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1016     struct ieee80211_key_conf *key = info->control.hw_key;
1017     struct sk_buff *skb = tx_info->skb;
1018     int err, pad, pktid, type;
1019 
1020     if (unlikely(tx_info->skb->len <= ETH_HLEN))
1021         return -EINVAL;
1022 
1023     if (!wcid)
1024         wcid = &dev->mt76.global_wcid;
1025 
1026     if (sta) {
1027         struct mt7921_sta *msta = (struct mt7921_sta *)sta->drv_priv;
1028 
1029         if (time_after(jiffies, msta->last_txs + HZ / 4)) {
1030             info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS;
1031             msta->last_txs = jiffies;
1032         }
1033     }
1034 
1035     pktid = mt76_tx_status_skb_add(&dev->mt76, wcid, skb);
1036     mt7921_usb_sdio_write_txwi(dev, wcid, qid, sta, key, pktid, skb);
1037 
1038     type = mt76_is_sdio(mdev) ? MT7921_SDIO_DATA : 0;
1039     mt7921_skb_add_usb_sdio_hdr(dev, skb, type);
1040     pad = round_up(skb->len, 4) - skb->len;
1041     if (mt76_is_usb(mdev))
1042         pad += 4;
1043 
1044     err = mt76_skb_adjust_pad(skb, pad);
1045     if (err)
1046         /* Release pktid in case of error. */
1047         idr_remove(&wcid->pktid, pktid);
1048 
1049     return err;
1050 }
1051 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_prepare_skb);
1052 
1053 void mt7921_usb_sdio_tx_complete_skb(struct mt76_dev *mdev,
1054                      struct mt76_queue_entry *e)
1055 {
1056     __le32 *txwi = (__le32 *)(e->skb->data + MT_SDIO_HDR_SIZE);
1057     unsigned int headroom = MT_SDIO_TXD_SIZE + MT_SDIO_HDR_SIZE;
1058     struct ieee80211_sta *sta;
1059     struct mt76_wcid *wcid;
1060     u16 idx;
1061 
1062     idx = le32_get_bits(txwi[1], MT_TXD1_WLAN_IDX);
1063     wcid = rcu_dereference(mdev->wcid[idx]);
1064     sta = wcid_to_sta(wcid);
1065 
1066     if (sta && likely(e->skb->protocol != cpu_to_be16(ETH_P_PAE)))
1067         mt7921_tx_check_aggr(sta, txwi);
1068 
1069     skb_pull(e->skb, headroom);
1070     mt76_tx_complete_skb(mdev, e->wcid, e->skb);
1071 }
1072 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_complete_skb);
1073 
1074 bool mt7921_usb_sdio_tx_status_data(struct mt76_dev *mdev, u8 *update)
1075 {
1076     struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
1077 
1078     mt7921_mutex_acquire(dev);
1079     mt7921_mac_sta_poll(dev);
1080     mt7921_mutex_release(dev);
1081 
1082     return false;
1083 }
1084 EXPORT_SYMBOL_GPL(mt7921_usb_sdio_tx_status_data);
1085 
1086 #if IS_ENABLED(CONFIG_IPV6)
1087 void mt7921_set_ipv6_ns_work(struct work_struct *work)
1088 {
1089     struct mt7921_dev *dev = container_of(work, struct mt7921_dev,
1090                         ipv6_ns_work);
1091     struct sk_buff *skb;
1092     int ret = 0;
1093 
1094     do {
1095         skb = skb_dequeue(&dev->ipv6_ns_list);
1096 
1097         if (!skb)
1098             break;
1099 
1100         mt7921_mutex_acquire(dev);
1101         ret = mt76_mcu_skb_send_msg(&dev->mt76, skb,
1102                         MCU_UNI_CMD(OFFLOAD), true);
1103         mt7921_mutex_release(dev);
1104 
1105     } while (!ret);
1106 
1107     if (ret)
1108         skb_queue_purge(&dev->ipv6_ns_list);
1109 }
1110 #endif
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