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0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #include "mt7915.h"
0005 #include "mac.h"
0006 #include "mcu.h"
0007 #include "testmode.h"
0008 
0009 enum {
0010     TM_CHANGED_TXPOWER,
0011     TM_CHANGED_FREQ_OFFSET,
0012 
0013     /* must be last */
0014     NUM_TM_CHANGED
0015 };
0016 
0017 static const u8 tm_change_map[] = {
0018     [TM_CHANGED_TXPOWER] = MT76_TM_ATTR_TX_POWER,
0019     [TM_CHANGED_FREQ_OFFSET] = MT76_TM_ATTR_FREQ_OFFSET,
0020 };
0021 
0022 struct reg_band {
0023     u32 band[2];
0024 };
0025 
0026 #define REG_BAND(_list, _reg) \
0027         { _list.band[0] = MT_##_reg(0); \
0028           _list.band[1] = MT_##_reg(1); }
0029 #define REG_BAND_IDX(_list, _reg, _idx) \
0030         { _list.band[0] = MT_##_reg(0, _idx);   \
0031           _list.band[1] = MT_##_reg(1, _idx); }
0032 
0033 #define TM_REG_MAX_ID   17
0034 static struct reg_band reg_backup_list[TM_REG_MAX_ID];
0035 
0036 
0037 static int
0038 mt7915_tm_set_tx_power(struct mt7915_phy *phy)
0039 {
0040     struct mt7915_dev *dev = phy->dev;
0041     struct mt76_phy *mphy = phy->mt76;
0042     struct cfg80211_chan_def *chandef = &mphy->chandef;
0043     int freq = chandef->center_freq1;
0044     int ret;
0045     struct {
0046         u8 format_id;
0047         u8 dbdc_idx;
0048         s8 tx_power;
0049         u8 ant_idx; /* Only 0 is valid */
0050         u8 center_chan;
0051         u8 rsv[3];
0052     } __packed req = {
0053         .format_id = 0xf,
0054         .dbdc_idx = phy != &dev->phy,
0055         .center_chan = ieee80211_frequency_to_channel(freq),
0056     };
0057     u8 *tx_power = NULL;
0058 
0059     if (phy->mt76->test.state != MT76_TM_STATE_OFF)
0060         tx_power = phy->mt76->test.tx_power;
0061 
0062     /* Tx power of the other antennas are the same as antenna 0 */
0063     if (tx_power && tx_power[0])
0064         req.tx_power = tx_power[0];
0065 
0066     ret = mt76_mcu_send_msg(&dev->mt76,
0067                 MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
0068                 &req, sizeof(req), false);
0069 
0070     return ret;
0071 }
0072 
0073 static int
0074 mt7915_tm_set_freq_offset(struct mt7915_phy *phy, bool en, u32 val)
0075 {
0076     struct mt7915_dev *dev = phy->dev;
0077     struct mt7915_tm_cmd req = {
0078         .testmode_en = en,
0079         .param_idx = MCU_ATE_SET_FREQ_OFFSET,
0080         .param.freq.band = phy != &dev->phy,
0081         .param.freq.freq_offset = cpu_to_le32(val),
0082     };
0083 
0084     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
0085                  sizeof(req), false);
0086 }
0087 
0088 static int
0089 mt7915_tm_mode_ctrl(struct mt7915_dev *dev, bool enable)
0090 {
0091     struct {
0092         u8 format_id;
0093         bool enable;
0094         u8 rsv[2];
0095     } __packed req = {
0096         .format_id = 0x6,
0097         .enable = enable,
0098     };
0099 
0100     return mt76_mcu_send_msg(&dev->mt76,
0101                  MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
0102                  &req, sizeof(req), false);
0103 }
0104 
0105 static int
0106 mt7915_tm_set_trx(struct mt7915_phy *phy, int type, bool en)
0107 {
0108     struct mt7915_dev *dev = phy->dev;
0109     struct mt7915_tm_cmd req = {
0110         .testmode_en = 1,
0111         .param_idx = MCU_ATE_SET_TRX,
0112         .param.trx.type = type,
0113         .param.trx.enable = en,
0114         .param.trx.band = phy != &dev->phy,
0115     };
0116 
0117     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
0118                  sizeof(req), false);
0119 }
0120 
0121 static int
0122 mt7915_tm_clean_hwq(struct mt7915_phy *phy, u8 wcid)
0123 {
0124     struct mt7915_dev *dev = phy->dev;
0125     struct mt7915_tm_cmd req = {
0126         .testmode_en = 1,
0127         .param_idx = MCU_ATE_CLEAN_TXQUEUE,
0128         .param.clean.wcid = wcid,
0129         .param.clean.band = phy != &dev->phy,
0130     };
0131 
0132     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
0133                  sizeof(req), false);
0134 }
0135 
0136 static int
0137 mt7915_tm_set_slot_time(struct mt7915_phy *phy, u8 slot_time, u8 sifs)
0138 {
0139     struct mt7915_dev *dev = phy->dev;
0140     struct mt7915_tm_cmd req = {
0141         .testmode_en = !(phy->mt76->test.state == MT76_TM_STATE_OFF),
0142         .param_idx = MCU_ATE_SET_SLOT_TIME,
0143         .param.slot.slot_time = slot_time,
0144         .param.slot.sifs = sifs,
0145         .param.slot.rifs = 2,
0146         .param.slot.eifs = cpu_to_le16(60),
0147         .param.slot.band = phy != &dev->phy,
0148     };
0149 
0150     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL), &req,
0151                  sizeof(req), false);
0152 }
0153 
0154 static int
0155 mt7915_tm_set_tam_arb(struct mt7915_phy *phy, bool enable, bool mu)
0156 {
0157     struct mt7915_dev *dev = phy->dev;
0158     u32 op_mode;
0159 
0160     if (!enable)
0161         op_mode = TAM_ARB_OP_MODE_NORMAL;
0162     else if (mu)
0163         op_mode = TAM_ARB_OP_MODE_TEST;
0164     else
0165         op_mode = TAM_ARB_OP_MODE_FORCE_SU;
0166 
0167     return mt7915_mcu_set_muru_ctrl(dev, MURU_SET_ARB_OP_MODE, op_mode);
0168 }
0169 
0170 static int
0171 mt7915_tm_set_wmm_qid(struct mt7915_phy *phy, u8 qid, u8 aifs, u8 cw_min,
0172               u16 cw_max, u16 txop)
0173 {
0174     struct mt7915_vif *mvif = (struct mt7915_vif *)phy->monitor_vif->drv_priv;
0175     struct mt7915_mcu_tx req = { .total = 1 };
0176     struct edca *e = &req.edca[0];
0177 
0178     e->queue = qid + mvif->mt76.wmm_idx * MT76_CONNAC_MAX_WMM_SETS;
0179     e->set = WMM_PARAM_SET;
0180 
0181     e->aifs = aifs;
0182     e->cw_min = cw_min;
0183     e->cw_max = cpu_to_le16(cw_max);
0184     e->txop = cpu_to_le16(txop);
0185 
0186     return mt7915_mcu_update_edca(phy->dev, &req);
0187 }
0188 
0189 static int
0190 mt7915_tm_set_ipg_params(struct mt7915_phy *phy, u32 ipg, u8 mode)
0191 {
0192 #define TM_DEFAULT_SIFS 10
0193 #define TM_MAX_SIFS 127
0194 #define TM_MAX_AIFSN    0xf
0195 #define TM_MIN_AIFSN    0x1
0196 #define BBP_PROC_TIME   1500
0197     struct mt7915_dev *dev = phy->dev;
0198     u8 sig_ext = (mode == MT76_TM_TX_MODE_CCK) ? 0 : 6;
0199     u8 slot_time = 9, sifs = TM_DEFAULT_SIFS;
0200     u8 aifsn = TM_MIN_AIFSN;
0201     u32 i2t_time, tr2t_time, txv_time;
0202     u16 cw = 0;
0203 
0204     if (ipg < sig_ext + slot_time + sifs)
0205         ipg = 0;
0206 
0207     if (!ipg)
0208         goto done;
0209 
0210     ipg -= sig_ext;
0211 
0212     if (ipg <= (TM_MAX_SIFS + slot_time)) {
0213         sifs = ipg - slot_time;
0214     } else {
0215         u32 val = (ipg + slot_time) / slot_time;
0216 
0217         while (val >>= 1)
0218             cw++;
0219 
0220         if (cw > 16)
0221             cw = 16;
0222 
0223         ipg -= ((1 << cw) - 1) * slot_time;
0224 
0225         aifsn = ipg / slot_time;
0226         if (aifsn > TM_MAX_AIFSN)
0227             aifsn = TM_MAX_AIFSN;
0228 
0229         ipg -= aifsn * slot_time;
0230 
0231         if (ipg > TM_DEFAULT_SIFS)
0232             sifs = min_t(u32, ipg, TM_MAX_SIFS);
0233     }
0234 done:
0235     txv_time = mt76_get_field(dev, MT_TMAC_ATCR(phy->band_idx),
0236                   MT_TMAC_ATCR_TXV_TOUT);
0237     txv_time *= 50; /* normal clock time */
0238 
0239     i2t_time = (slot_time * 1000 - txv_time - BBP_PROC_TIME) / 50;
0240     tr2t_time = (sifs * 1000 - txv_time - BBP_PROC_TIME) / 50;
0241 
0242     mt76_set(dev, MT_TMAC_TRCR0(phy->band_idx),
0243          FIELD_PREP(MT_TMAC_TRCR0_TR2T_CHK, tr2t_time) |
0244          FIELD_PREP(MT_TMAC_TRCR0_I2T_CHK, i2t_time));
0245 
0246     mt7915_tm_set_slot_time(phy, slot_time, sifs);
0247 
0248     return mt7915_tm_set_wmm_qid(phy,
0249                      mt76_connac_lmac_mapping(IEEE80211_AC_BE),
0250                      aifsn, cw, cw, 0);
0251 }
0252 
0253 static int
0254 mt7915_tm_set_tx_len(struct mt7915_phy *phy, u32 tx_time)
0255 {
0256     struct mt76_phy *mphy = phy->mt76;
0257     struct mt76_testmode_data *td = &mphy->test;
0258     struct ieee80211_supported_band *sband;
0259     struct rate_info rate = {};
0260     u16 flags = 0, tx_len;
0261     u32 bitrate;
0262     int ret;
0263 
0264     if (!tx_time)
0265         return 0;
0266 
0267     rate.mcs = td->tx_rate_idx;
0268     rate.nss = td->tx_rate_nss;
0269 
0270     switch (td->tx_rate_mode) {
0271     case MT76_TM_TX_MODE_CCK:
0272     case MT76_TM_TX_MODE_OFDM:
0273         if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
0274             sband = &mphy->sband_5g.sband;
0275         else if (mphy->chandef.chan->band == NL80211_BAND_6GHZ)
0276             sband = &mphy->sband_6g.sband;
0277         else
0278             sband = &mphy->sband_2g.sband;
0279 
0280         rate.legacy = sband->bitrates[rate.mcs].bitrate;
0281         break;
0282     case MT76_TM_TX_MODE_HT:
0283         rate.mcs += rate.nss * 8;
0284         flags |= RATE_INFO_FLAGS_MCS;
0285 
0286         if (td->tx_rate_sgi)
0287             flags |= RATE_INFO_FLAGS_SHORT_GI;
0288         break;
0289     case MT76_TM_TX_MODE_VHT:
0290         flags |= RATE_INFO_FLAGS_VHT_MCS;
0291 
0292         if (td->tx_rate_sgi)
0293             flags |= RATE_INFO_FLAGS_SHORT_GI;
0294         break;
0295     case MT76_TM_TX_MODE_HE_SU:
0296     case MT76_TM_TX_MODE_HE_EXT_SU:
0297     case MT76_TM_TX_MODE_HE_TB:
0298     case MT76_TM_TX_MODE_HE_MU:
0299         rate.he_gi = td->tx_rate_sgi;
0300         flags |= RATE_INFO_FLAGS_HE_MCS;
0301         break;
0302     default:
0303         break;
0304     }
0305     rate.flags = flags;
0306 
0307     switch (mphy->chandef.width) {
0308     case NL80211_CHAN_WIDTH_160:
0309     case NL80211_CHAN_WIDTH_80P80:
0310         rate.bw = RATE_INFO_BW_160;
0311         break;
0312     case NL80211_CHAN_WIDTH_80:
0313         rate.bw = RATE_INFO_BW_80;
0314         break;
0315     case NL80211_CHAN_WIDTH_40:
0316         rate.bw = RATE_INFO_BW_40;
0317         break;
0318     default:
0319         rate.bw = RATE_INFO_BW_20;
0320         break;
0321     }
0322 
0323     bitrate = cfg80211_calculate_bitrate(&rate);
0324     tx_len = bitrate * tx_time / 10 / 8;
0325 
0326     ret = mt76_testmode_alloc_skb(phy->mt76, tx_len);
0327     if (ret)
0328         return ret;
0329 
0330     return 0;
0331 }
0332 
0333 static void
0334 mt7915_tm_reg_backup_restore(struct mt7915_phy *phy)
0335 {
0336     int n_regs = ARRAY_SIZE(reg_backup_list);
0337     struct mt7915_dev *dev = phy->dev;
0338     u32 *b = phy->test.reg_backup;
0339     int i;
0340 
0341     REG_BAND_IDX(reg_backup_list[0], AGG_PCR0, 0);
0342     REG_BAND_IDX(reg_backup_list[1], AGG_PCR0, 1);
0343     REG_BAND_IDX(reg_backup_list[2], AGG_AWSCR0, 0);
0344     REG_BAND_IDX(reg_backup_list[3], AGG_AWSCR0, 1);
0345     REG_BAND_IDX(reg_backup_list[4], AGG_AWSCR0, 2);
0346     REG_BAND_IDX(reg_backup_list[5], AGG_AWSCR0, 3);
0347     REG_BAND(reg_backup_list[6], AGG_MRCR);
0348     REG_BAND(reg_backup_list[7], TMAC_TFCR0);
0349     REG_BAND(reg_backup_list[8], TMAC_TCR0);
0350     REG_BAND(reg_backup_list[9], AGG_ATCR1);
0351     REG_BAND(reg_backup_list[10], AGG_ATCR3);
0352     REG_BAND(reg_backup_list[11], TMAC_TRCR0);
0353     REG_BAND(reg_backup_list[12], TMAC_ICR0);
0354     REG_BAND_IDX(reg_backup_list[13], ARB_DRNGR0, 0);
0355     REG_BAND_IDX(reg_backup_list[14], ARB_DRNGR0, 1);
0356     REG_BAND(reg_backup_list[15], WF_RFCR);
0357     REG_BAND(reg_backup_list[16], WF_RFCR1);
0358 
0359     if (phy->mt76->test.state == MT76_TM_STATE_OFF) {
0360         for (i = 0; i < n_regs; i++)
0361             mt76_wr(dev, reg_backup_list[i].band[phy->band_idx], b[i]);
0362         return;
0363     }
0364 
0365     if (!b) {
0366         b = devm_kzalloc(dev->mt76.dev, 4 * n_regs, GFP_KERNEL);
0367         if (!b)
0368             return;
0369 
0370         phy->test.reg_backup = b;
0371         for (i = 0; i < n_regs; i++)
0372             b[i] = mt76_rr(dev, reg_backup_list[i].band[phy->band_idx]);
0373     }
0374 
0375     mt76_clear(dev, MT_AGG_PCR0(phy->band_idx, 0), MT_AGG_PCR0_MM_PROT |
0376            MT_AGG_PCR0_GF_PROT | MT_AGG_PCR0_ERP_PROT |
0377            MT_AGG_PCR0_VHT_PROT | MT_AGG_PCR0_BW20_PROT |
0378            MT_AGG_PCR0_BW40_PROT | MT_AGG_PCR0_BW80_PROT);
0379     mt76_set(dev, MT_AGG_PCR0(phy->band_idx, 0), MT_AGG_PCR0_PTA_WIN_DIS);
0380 
0381     mt76_wr(dev, MT_AGG_PCR0(phy->band_idx, 1), MT_AGG_PCR1_RTS0_NUM_THRES |
0382         MT_AGG_PCR1_RTS0_LEN_THRES);
0383 
0384     mt76_clear(dev, MT_AGG_MRCR(phy->band_idx), MT_AGG_MRCR_BAR_CNT_LIMIT |
0385            MT_AGG_MRCR_LAST_RTS_CTS_RN | MT_AGG_MRCR_RTS_FAIL_LIMIT |
0386            MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT);
0387 
0388     mt76_rmw(dev, MT_AGG_MRCR(phy->band_idx), MT_AGG_MRCR_RTS_FAIL_LIMIT |
0389          MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT,
0390          FIELD_PREP(MT_AGG_MRCR_RTS_FAIL_LIMIT, 1) |
0391          FIELD_PREP(MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT, 1));
0392 
0393     mt76_wr(dev, MT_TMAC_TFCR0(phy->band_idx), 0);
0394     mt76_clear(dev, MT_TMAC_TCR0(phy->band_idx), MT_TMAC_TCR0_TBTT_STOP_CTRL);
0395 
0396     /* config rx filter for testmode rx */
0397     mt76_wr(dev, MT_WF_RFCR(phy->band_idx), 0xcf70a);
0398     mt76_wr(dev, MT_WF_RFCR1(phy->band_idx), 0);
0399 }
0400 
0401 static void
0402 mt7915_tm_init(struct mt7915_phy *phy, bool en)
0403 {
0404     struct mt7915_dev *dev = phy->dev;
0405 
0406     if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
0407         return;
0408 
0409     mt7915_mcu_set_sku_en(phy, !en);
0410 
0411     mt7915_tm_mode_ctrl(dev, en);
0412     mt7915_tm_reg_backup_restore(phy);
0413     mt7915_tm_set_trx(phy, TM_MAC_TXRX, !en);
0414 
0415     mt7915_mcu_add_bss_info(phy, phy->monitor_vif, en);
0416     mt7915_mcu_add_sta(dev, phy->monitor_vif, NULL, en);
0417 
0418     if (!en)
0419         mt7915_tm_set_tam_arb(phy, en, 0);
0420 }
0421 
0422 static void
0423 mt7915_tm_update_channel(struct mt7915_phy *phy)
0424 {
0425     mutex_unlock(&phy->dev->mt76.mutex);
0426     mt7915_set_channel(phy);
0427     mutex_lock(&phy->dev->mt76.mutex);
0428 
0429     mt7915_mcu_set_chan_info(phy, MCU_EXT_CMD(SET_RX_PATH));
0430 }
0431 
0432 static void
0433 mt7915_tm_set_tx_frames(struct mt7915_phy *phy, bool en)
0434 {
0435     static const u8 spe_idx_map[] = {0, 0, 1, 0, 3, 2, 4, 0,
0436                      9, 8, 6, 10, 16, 12, 18, 0};
0437     struct mt76_testmode_data *td = &phy->mt76->test;
0438     struct mt7915_dev *dev = phy->dev;
0439     struct ieee80211_tx_info *info;
0440     u8 duty_cycle = td->tx_duty_cycle;
0441     u32 tx_time = td->tx_time;
0442     u32 ipg = td->tx_ipg;
0443 
0444     mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
0445     mt7915_tm_clean_hwq(phy, dev->mt76.global_wcid.idx);
0446 
0447     if (en) {
0448         mt7915_tm_update_channel(phy);
0449 
0450         if (td->tx_spe_idx) {
0451             phy->test.spe_idx = td->tx_spe_idx;
0452         } else {
0453             u8 tx_ant = td->tx_antenna_mask;
0454 
0455             if (phy != &dev->phy)
0456                 tx_ant >>= dev->chainshift;
0457             phy->test.spe_idx = spe_idx_map[tx_ant];
0458         }
0459     }
0460 
0461     mt7915_tm_set_tam_arb(phy, en,
0462                   td->tx_rate_mode == MT76_TM_TX_MODE_HE_MU);
0463 
0464     /* if all three params are set, duty_cycle will be ignored */
0465     if (duty_cycle && tx_time && !ipg) {
0466         ipg = tx_time * 100 / duty_cycle - tx_time;
0467     } else if (duty_cycle && !tx_time && ipg) {
0468         if (duty_cycle < 100)
0469             tx_time = duty_cycle * ipg / (100 - duty_cycle);
0470     }
0471 
0472     mt7915_tm_set_ipg_params(phy, ipg, td->tx_rate_mode);
0473     mt7915_tm_set_tx_len(phy, tx_time);
0474 
0475     if (ipg)
0476         td->tx_queued_limit = MT76_TM_TIMEOUT * 1000000 / ipg / 2;
0477 
0478     if (!en || !td->tx_skb)
0479         return;
0480 
0481     info = IEEE80211_SKB_CB(td->tx_skb);
0482     info->control.vif = phy->monitor_vif;
0483 
0484     mt7915_tm_set_trx(phy, TM_MAC_TX, en);
0485 }
0486 
0487 static void
0488 mt7915_tm_set_rx_frames(struct mt7915_phy *phy, bool en)
0489 {
0490     mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, false);
0491 
0492     if (en) {
0493         struct mt7915_dev *dev = phy->dev;
0494 
0495         mt7915_tm_update_channel(phy);
0496 
0497         /* read-clear */
0498         mt76_rr(dev, MT_MIB_SDR3(phy != &dev->phy));
0499         mt7915_tm_set_trx(phy, TM_MAC_RX_RXV, en);
0500     }
0501 }
0502 
0503 static int
0504 mt7915_tm_rf_switch_mode(struct mt7915_dev *dev, u32 oper)
0505 {
0506     struct mt7915_tm_rf_test req = {
0507         .op.op_mode = cpu_to_le32(oper),
0508     };
0509 
0510     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
0511                  sizeof(req), true);
0512 }
0513 
0514 static int
0515 mt7915_tm_set_tx_cont(struct mt7915_phy *phy, bool en)
0516 {
0517 #define TX_CONT_START   0x05
0518 #define TX_CONT_STOP    0x06
0519     struct mt7915_dev *dev = phy->dev;
0520     struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
0521     int freq1 = ieee80211_frequency_to_channel(chandef->center_freq1);
0522     struct mt76_testmode_data *td = &phy->mt76->test;
0523     u32 func_idx = en ? TX_CONT_START : TX_CONT_STOP;
0524     u8 rate_idx = td->tx_rate_idx, mode;
0525     u16 rateval;
0526     struct mt7915_tm_rf_test req = {
0527         .action = 1,
0528         .icap_len = 120,
0529         .op.rf.func_idx = cpu_to_le32(func_idx),
0530     };
0531     struct tm_tx_cont *tx_cont = &req.op.rf.param.tx_cont;
0532 
0533     tx_cont->control_ch = chandef->chan->hw_value;
0534     tx_cont->center_ch = freq1;
0535     tx_cont->tx_ant = td->tx_antenna_mask;
0536     tx_cont->band = phy != &dev->phy;
0537 
0538     switch (chandef->width) {
0539     case NL80211_CHAN_WIDTH_40:
0540         tx_cont->bw = CMD_CBW_40MHZ;
0541         break;
0542     case NL80211_CHAN_WIDTH_80:
0543         tx_cont->bw = CMD_CBW_80MHZ;
0544         break;
0545     case NL80211_CHAN_WIDTH_80P80:
0546         tx_cont->bw = CMD_CBW_8080MHZ;
0547         break;
0548     case NL80211_CHAN_WIDTH_160:
0549         tx_cont->bw = CMD_CBW_160MHZ;
0550         break;
0551     case NL80211_CHAN_WIDTH_5:
0552         tx_cont->bw = CMD_CBW_5MHZ;
0553         break;
0554     case NL80211_CHAN_WIDTH_10:
0555         tx_cont->bw = CMD_CBW_10MHZ;
0556         break;
0557     case NL80211_CHAN_WIDTH_20:
0558         tx_cont->bw = CMD_CBW_20MHZ;
0559         break;
0560     case NL80211_CHAN_WIDTH_20_NOHT:
0561         tx_cont->bw = CMD_CBW_20MHZ;
0562         break;
0563     default:
0564         return -EINVAL;
0565     }
0566 
0567     if (!en) {
0568         req.op.rf.param.func_data = cpu_to_le32(phy != &dev->phy);
0569         goto out;
0570     }
0571 
0572     if (td->tx_rate_mode <= MT76_TM_TX_MODE_OFDM) {
0573         struct ieee80211_supported_band *sband;
0574         u8 idx = rate_idx;
0575 
0576         if (chandef->chan->band == NL80211_BAND_5GHZ)
0577             sband = &phy->mt76->sband_5g.sband;
0578         else if (chandef->chan->band == NL80211_BAND_6GHZ)
0579             sband = &phy->mt76->sband_6g.sband;
0580         else
0581             sband = &phy->mt76->sband_2g.sband;
0582 
0583         if (td->tx_rate_mode == MT76_TM_TX_MODE_OFDM)
0584             idx += 4;
0585         rate_idx = sband->bitrates[idx].hw_value & 0xff;
0586     }
0587 
0588     switch (td->tx_rate_mode) {
0589     case MT76_TM_TX_MODE_CCK:
0590         mode = MT_PHY_TYPE_CCK;
0591         break;
0592     case MT76_TM_TX_MODE_OFDM:
0593         mode = MT_PHY_TYPE_OFDM;
0594         break;
0595     case MT76_TM_TX_MODE_HT:
0596         mode = MT_PHY_TYPE_HT;
0597         break;
0598     case MT76_TM_TX_MODE_VHT:
0599         mode = MT_PHY_TYPE_VHT;
0600         break;
0601     case MT76_TM_TX_MODE_HE_SU:
0602         mode = MT_PHY_TYPE_HE_SU;
0603         break;
0604     case MT76_TM_TX_MODE_HE_EXT_SU:
0605         mode = MT_PHY_TYPE_HE_EXT_SU;
0606         break;
0607     case MT76_TM_TX_MODE_HE_TB:
0608         mode = MT_PHY_TYPE_HE_TB;
0609         break;
0610     case MT76_TM_TX_MODE_HE_MU:
0611         mode = MT_PHY_TYPE_HE_MU;
0612         break;
0613     default:
0614         return -EINVAL;
0615     }
0616 
0617     rateval =  mode << 6 | rate_idx;
0618     tx_cont->rateval = cpu_to_le16(rateval);
0619 
0620 out:
0621     if (!en) {
0622         int ret;
0623 
0624         ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
0625                     sizeof(req), true);
0626         if (ret)
0627             return ret;
0628 
0629         return mt7915_tm_rf_switch_mode(dev, RF_OPER_NORMAL);
0630     }
0631 
0632     mt7915_tm_rf_switch_mode(dev, RF_OPER_RF_TEST);
0633     mt7915_tm_update_channel(phy);
0634 
0635     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_TEST), &req,
0636                  sizeof(req), true);
0637 }
0638 
0639 static void
0640 mt7915_tm_update_params(struct mt7915_phy *phy, u32 changed)
0641 {
0642     struct mt76_testmode_data *td = &phy->mt76->test;
0643     bool en = phy->mt76->test.state != MT76_TM_STATE_OFF;
0644 
0645     if (changed & BIT(TM_CHANGED_FREQ_OFFSET))
0646         mt7915_tm_set_freq_offset(phy, en, en ? td->freq_offset : 0);
0647     if (changed & BIT(TM_CHANGED_TXPOWER))
0648         mt7915_tm_set_tx_power(phy);
0649 }
0650 
0651 static int
0652 mt7915_tm_set_state(struct mt76_phy *mphy, enum mt76_testmode_state state)
0653 {
0654     struct mt76_testmode_data *td = &mphy->test;
0655     struct mt7915_phy *phy = mphy->priv;
0656     enum mt76_testmode_state prev_state = td->state;
0657 
0658     mphy->test.state = state;
0659 
0660     if (prev_state == MT76_TM_STATE_TX_FRAMES ||
0661         state == MT76_TM_STATE_TX_FRAMES)
0662         mt7915_tm_set_tx_frames(phy, state == MT76_TM_STATE_TX_FRAMES);
0663     else if (prev_state == MT76_TM_STATE_RX_FRAMES ||
0664          state == MT76_TM_STATE_RX_FRAMES)
0665         mt7915_tm_set_rx_frames(phy, state == MT76_TM_STATE_RX_FRAMES);
0666     else if (prev_state == MT76_TM_STATE_TX_CONT ||
0667          state == MT76_TM_STATE_TX_CONT)
0668         mt7915_tm_set_tx_cont(phy, state == MT76_TM_STATE_TX_CONT);
0669     else if (prev_state == MT76_TM_STATE_OFF ||
0670          state == MT76_TM_STATE_OFF)
0671         mt7915_tm_init(phy, !(state == MT76_TM_STATE_OFF));
0672 
0673     if ((state == MT76_TM_STATE_IDLE &&
0674          prev_state == MT76_TM_STATE_OFF) ||
0675         (state == MT76_TM_STATE_OFF &&
0676          prev_state == MT76_TM_STATE_IDLE)) {
0677         u32 changed = 0;
0678         int i;
0679 
0680         for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
0681             u16 cur = tm_change_map[i];
0682 
0683             if (td->param_set[cur / 32] & BIT(cur % 32))
0684                 changed |= BIT(i);
0685         }
0686 
0687         mt7915_tm_update_params(phy, changed);
0688     }
0689 
0690     return 0;
0691 }
0692 
0693 static int
0694 mt7915_tm_set_params(struct mt76_phy *mphy, struct nlattr **tb,
0695              enum mt76_testmode_state new_state)
0696 {
0697     struct mt76_testmode_data *td = &mphy->test;
0698     struct mt7915_phy *phy = mphy->priv;
0699     u32 changed = 0;
0700     int i;
0701 
0702     BUILD_BUG_ON(NUM_TM_CHANGED >= 32);
0703 
0704     if (new_state == MT76_TM_STATE_OFF ||
0705         td->state == MT76_TM_STATE_OFF)
0706         return 0;
0707 
0708     if (td->tx_antenna_mask & ~mphy->chainmask)
0709         return -EINVAL;
0710 
0711     for (i = 0; i < ARRAY_SIZE(tm_change_map); i++) {
0712         if (tb[tm_change_map[i]])
0713             changed |= BIT(i);
0714     }
0715 
0716     mt7915_tm_update_params(phy, changed);
0717 
0718     return 0;
0719 }
0720 
0721 static int
0722 mt7915_tm_dump_stats(struct mt76_phy *mphy, struct sk_buff *msg)
0723 {
0724     struct mt7915_phy *phy = mphy->priv;
0725     struct mt7915_dev *dev = phy->dev;
0726     enum mt76_rxq_id q;
0727     void *rx, *rssi;
0728     u16 fcs_err;
0729     int i;
0730     u32 cnt;
0731 
0732     rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX);
0733     if (!rx)
0734         return -ENOMEM;
0735 
0736     if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, phy->test.last_freq_offset))
0737         return -ENOMEM;
0738 
0739     rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI);
0740     if (!rssi)
0741         return -ENOMEM;
0742 
0743     for (i = 0; i < ARRAY_SIZE(phy->test.last_rcpi); i++)
0744         if (nla_put_u8(msg, i, phy->test.last_rcpi[i]))
0745             return -ENOMEM;
0746 
0747     nla_nest_end(msg, rssi);
0748 
0749     rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI);
0750     if (!rssi)
0751         return -ENOMEM;
0752 
0753     for (i = 0; i < ARRAY_SIZE(phy->test.last_ib_rssi); i++)
0754         if (nla_put_s8(msg, i, phy->test.last_ib_rssi[i]))
0755             return -ENOMEM;
0756 
0757     nla_nest_end(msg, rssi);
0758 
0759     rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI);
0760     if (!rssi)
0761         return -ENOMEM;
0762 
0763     for (i = 0; i < ARRAY_SIZE(phy->test.last_wb_rssi); i++)
0764         if (nla_put_s8(msg, i, phy->test.last_wb_rssi[i]))
0765             return -ENOMEM;
0766 
0767     nla_nest_end(msg, rssi);
0768 
0769     if (nla_put_u8(msg, MT76_TM_RX_ATTR_SNR, phy->test.last_snr))
0770         return -ENOMEM;
0771 
0772     nla_nest_end(msg, rx);
0773 
0774     cnt = mt76_rr(dev, MT_MIB_SDR3(phy->band_idx));
0775     fcs_err = is_mt7915(&dev->mt76) ? FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) :
0776         FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt);
0777 
0778     q = phy->band_idx ? MT_RXQ_BAND1 : MT_RXQ_MAIN;
0779     mphy->test.rx_stats.packets[q] += fcs_err;
0780     mphy->test.rx_stats.fcs_error[q] += fcs_err;
0781 
0782     return 0;
0783 }
0784 
0785 const struct mt76_testmode_ops mt7915_testmode_ops = {
0786     .set_state = mt7915_tm_set_state,
0787     .set_params = mt7915_tm_set_params,
0788     .dump_stats = mt7915_tm_dump_stats,
0789 };
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