0001
0002
0003
0004 #ifndef __MT7915_REGS_H
0005 #define __MT7915_REGS_H
0006
0007 struct __map {
0008 u32 phys;
0009 u32 maps;
0010 u32 size;
0011 };
0012
0013
0014 struct mt7915_reg_desc {
0015 const u32 *reg_rev;
0016 const u32 *offs_rev;
0017 const struct __map *map;
0018 u32 map_size;
0019 };
0020
0021 enum reg_rev {
0022 INT_SOURCE_CSR,
0023 INT_MASK_CSR,
0024 INT1_SOURCE_CSR,
0025 INT1_MASK_CSR,
0026 INT_MCU_CMD_SOURCE,
0027 INT_MCU_CMD_EVENT,
0028 WFDMA0_ADDR,
0029 WFDMA0_PCIE1_ADDR,
0030 WFDMA_EXT_CSR_ADDR,
0031 CBTOP1_PHY_END,
0032 INFRA_MCU_ADDR_END,
0033 FW_EXCEPTION_ADDR,
0034 SWDEF_BASE_ADDR,
0035 __MT_REG_MAX,
0036 };
0037
0038 enum offs_rev {
0039 TMAC_CDTR,
0040 TMAC_ODTR,
0041 TMAC_ATCR,
0042 TMAC_TRCR0,
0043 TMAC_ICR0,
0044 TMAC_ICR1,
0045 TMAC_CTCR0,
0046 TMAC_TFCR0,
0047 MDP_BNRCFR0,
0048 MDP_BNRCFR1,
0049 ARB_DRNGR0,
0050 ARB_SCR,
0051 RMAC_MIB_AIRTIME14,
0052 AGG_AWSCR0,
0053 AGG_PCR0,
0054 AGG_ACR0,
0055 AGG_MRCR,
0056 AGG_ATCR1,
0057 AGG_ATCR3,
0058 LPON_UTTR0,
0059 LPON_UTTR1,
0060 LPON_FRCR,
0061 MIB_SDR3,
0062 MIB_SDR4,
0063 MIB_SDR5,
0064 MIB_SDR7,
0065 MIB_SDR8,
0066 MIB_SDR9,
0067 MIB_SDR10,
0068 MIB_SDR11,
0069 MIB_SDR12,
0070 MIB_SDR13,
0071 MIB_SDR14,
0072 MIB_SDR15,
0073 MIB_SDR16,
0074 MIB_SDR17,
0075 MIB_SDR18,
0076 MIB_SDR19,
0077 MIB_SDR20,
0078 MIB_SDR21,
0079 MIB_SDR22,
0080 MIB_SDR23,
0081 MIB_SDR24,
0082 MIB_SDR25,
0083 MIB_SDR27,
0084 MIB_SDR28,
0085 MIB_SDR29,
0086 MIB_SDRVEC,
0087 MIB_SDR31,
0088 MIB_SDR32,
0089 MIB_SDRMUBF,
0090 MIB_DR8,
0091 MIB_DR9,
0092 MIB_DR11,
0093 MIB_MB_SDR0,
0094 MIB_MB_SDR1,
0095 TX_AGG_CNT,
0096 TX_AGG_CNT2,
0097 MIB_ARNG,
0098 WTBLON_TOP_WDUCR,
0099 WTBL_UPDATE,
0100 PLE_FL_Q_EMPTY,
0101 PLE_FL_Q_CTRL,
0102 PLE_AC_QEMPTY,
0103 PLE_FREEPG_CNT,
0104 PLE_FREEPG_HEAD_TAIL,
0105 PLE_PG_HIF_GROUP,
0106 PLE_HIF_PG_INFO,
0107 AC_OFFSET,
0108 ETBF_PAR_RPT0,
0109 __MT_OFFS_MAX,
0110 };
0111
0112 #define __REG(id) (dev->reg.reg_rev[(id)])
0113 #define __OFFS(id) (dev->reg.offs_rev[(id)])
0114
0115
0116 #define MT_MCU_WFDMA0_BASE 0x2000
0117 #define MT_MCU_WFDMA0(ofs) (MT_MCU_WFDMA0_BASE + (ofs))
0118
0119 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
0120
0121
0122 #define MT_MCU_WFDMA1_BASE 0x3000
0123 #define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
0124
0125 #define MT_MCU_INT_EVENT __REG(INT_MCU_CMD_EVENT)
0126 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
0127 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
0128 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
0129 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
0130
0131
0132 #define MT_PLE_BASE 0x820c0000
0133 #define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
0134
0135 #define MT_FL_Q_EMPTY MT_PLE(__OFFS(PLE_FL_Q_EMPTY))
0136 #define MT_FL_Q0_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL))
0137 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
0138 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
0139
0140 #define MT_PLE_FREEPG_CNT MT_PLE(__OFFS(PLE_FREEPG_CNT))
0141 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(__OFFS(PLE_FREEPG_HEAD_TAIL))
0142 #define MT_PLE_PG_HIF_GROUP MT_PLE(__OFFS(PLE_PG_HIF_GROUP))
0143 #define MT_PLE_HIF_PG_INFO MT_PLE(__OFFS(PLE_HIF_PG_INFO))
0144
0145 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(__OFFS(PLE_AC_QEMPTY) + \
0146 __OFFS(AC_OFFSET) * \
0147 (ac) + ((n) << 2))
0148 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
0149
0150 #define MT_PSE_BASE 0x820c8000
0151 #define MT_PSE(ofs) (MT_PSE_BASE + (ofs))
0152
0153
0154 #define MT_MDP_BASE 0x820cd000
0155 #define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
0156
0157 #define MT_MDP_DCR0 MT_MDP(0x000)
0158 #define MT_MDP_DCR0_DAMSDU_EN BIT(15)
0159
0160 #define MT_MDP_DCR1 MT_MDP(0x004)
0161 #define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
0162
0163 #define MT_MDP_DCR2 MT_MDP(0x0e8)
0164 #define MT_MDP_DCR2_RX_TRANS_SHORT BIT(2)
0165
0166 #define MT_MDP_BNRCFR0(_band) MT_MDP(__OFFS(MDP_BNRCFR0) + \
0167 ((_band) << 8))
0168 #define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
0169 #define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
0170 #define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
0171
0172 #define MT_MDP_BNRCFR1(_band) MT_MDP(__OFFS(MDP_BNRCFR1) + \
0173 ((_band) << 8))
0174 #define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
0175 #define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
0176 #define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
0177 #define MT_MDP_TO_HIF 0
0178 #define MT_MDP_TO_WM 1
0179
0180
0181 #define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000)
0182 #define MT_WF_TRB(_band, ofs) (MT_WF_TRB_BASE(_band) + (ofs))
0183
0184 #define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c)
0185 #define MT_TRB_RXPSR0_RX_WTBL_PTR GENMASK(25, 16)
0186 #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
0187
0188
0189 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
0190 #define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
0191
0192 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
0193 #define MT_TMAC_TCR0_TX_BLINK GENMASK(7, 6)
0194 #define MT_TMAC_TCR0_TBTT_STOP_CTRL BIT(25)
0195
0196 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CDTR))
0197 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ODTR))
0198 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
0199 #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
0200
0201 #define MT_TMAC_ATCR(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ATCR))
0202 #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)
0203
0204 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TRCR0))
0205 #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)
0206 #define MT_TMAC_TRCR0_I2T_CHK GENMASK(24, 16)
0207
0208 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR0))
0209 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
0210 #define MT_IFS_RIFS GENMASK(14, 10)
0211 #define MT_IFS_SIFS GENMASK(22, 16)
0212 #define MT_IFS_SLOT GENMASK(30, 24)
0213
0214 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, __OFFS(TMAC_ICR1))
0215 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
0216
0217 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_CTCR0))
0218 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
0219 #define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
0220 #define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
0221
0222 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, __OFFS(TMAC_TFCR0))
0223
0224
0225 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
0226 #define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
0227
0228 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
0229 #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
0230 #define MT_DMA_DCR0_RXD_G5_EN BIT(23)
0231
0232
0233 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
0234 #define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
0235
0236 #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
0237 #define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
0238 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
0239
0240 #define MT_ETBF_PAR_RPT0(_band) MT_WF_ETBF(_band, __OFFS(ETBF_PAR_RPT0))
0241 #define MT_ETBF_PAR_RPT0_FB_BW GENMASK(7, 6)
0242 #define MT_ETBF_PAR_RPT0_FB_NC GENMASK(5, 3)
0243 #define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0)
0244
0245 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
0246 #define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
0247 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
0248
0249 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8)
0250 #define MT_ETBF_RX_FB_ALL GENMASK(31, 24)
0251 #define MT_ETBF_RX_FB_HE GENMASK(23, 16)
0252 #define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
0253 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
0254
0255
0256 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
0257 #define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
0258
0259 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR0))
0260 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, __OFFS(LPON_UTTR1))
0261 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, __OFFS(LPON_FRCR))
0262
0263 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \
0264 (((n) * 4) << 1))
0265 #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \
0266 (((n) * 4) << 4))
0267 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
0268 #define MT_LPON_TCR_SW_WRITE BIT(0)
0269 #define MT_LPON_TCR_SW_ADJUST BIT(1)
0270 #define MT_LPON_TCR_SW_READ GENMASK(1, 0)
0271
0272
0273
0274
0275
0276
0277
0278
0279 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
0280 #define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
0281
0282 #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010)
0283 #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0)
0284
0285 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR3))
0286 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
0287 #define MT_MIB_SDR3_FCS_ERR_MASK_MT7916 GENMASK(31, 16)
0288
0289 #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR4))
0290 #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)
0291
0292
0293 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR5))
0294
0295 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
0296 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
0297
0298 #define MT_MIB_SDR7(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR7))
0299 #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0)
0300
0301 #define MT_MIB_SDR8(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR8))
0302 #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0)
0303
0304
0305 #define MT_MIB_SDR9_DNR(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR9))
0306 #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)
0307
0308 #define MT_MIB_SDR10(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR10))
0309 #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0)
0310 #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0)
0311
0312 #define MT_MIB_SDR11(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR11))
0313 #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0)
0314
0315
0316 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR12))
0317
0318 #define MT_MIB_SDR13(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR13))
0319 #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0)
0320
0321
0322 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR14))
0323 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0)
0324 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0)
0325
0326
0327 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR15))
0328 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0)
0329 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0)
0330
0331
0332 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR16))
0333 #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
0334
0335 #define MT_MIB_SDR17(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR17))
0336 #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
0337
0338 #define MT_MIB_SDR18(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR18))
0339 #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0)
0340
0341
0342 #define MT_MIB_SDR19(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR19))
0343 #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0)
0344
0345 #define MT_MIB_SDR20(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR20))
0346 #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0)
0347
0348 #define MT_MIB_SDR21(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR21))
0349 #define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0)
0350
0351
0352 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR22))
0353
0354
0355 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR23))
0356
0357
0358 #define MT_MIB_SDR24(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR24))
0359 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0)
0360 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0)
0361
0362
0363 #define MT_MIB_SDR25(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR25))
0364
0365
0366 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR27))
0367 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0)
0368
0369 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR28))
0370 #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0)
0371
0372 #define MT_MIB_SDR29(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR29))
0373 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0)
0374 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0)
0375
0376 #define MT_MIB_SDRVEC(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRVEC))
0377 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0)
0378 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916 GENMASK(31, 16)
0379
0380
0381 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR31))
0382
0383 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, __OFFS(MIB_SDR32))
0384 #define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0)
0385 #define MT_MIB_SDR32_TX_PKT_IBF_CNT GENMASK(31, 16)
0386
0387 #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088)
0388 #define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0)
0389
0390 #define MT_MIB_SDRMUBF(_band) MT_WF_MIB(_band, __OFFS(MIB_SDRMUBF))
0391 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
0392
0393
0394
0395 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, __OFFS(MIB_DR8))
0396 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, __OFFS(MIB_DR9))
0397 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, __OFFS(MIB_DR11))
0398
0399 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR0) + (n))
0400 #define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
0401 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
0402
0403 #define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, __OFFS(MIB_MB_SDR1) + (n))
0404 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
0405 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
0406
0407 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n))
0408 #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n))
0409
0410 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT) + \
0411 ((n) << 2))
0412 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, __OFFS(TX_AGG_CNT2) + \
0413 ((n) << 2))
0414 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, __OFFS(MIB_ARNG) + \
0415 ((n) << 2))
0416 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
0417
0418 #define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0)
0419 #define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0)
0420 #define MT_MIB_BFCR0_RX_FB_VHT GENMASK(31, 16)
0421
0422 #define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4)
0423 #define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0)
0424
0425 #define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8)
0426 #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0)
0427
0428 #define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc)
0429 #define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0)
0430
0431
0432 #define MT_WTBLON_TOP_BASE 0x820d4000
0433 #define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
0434 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(__OFFS(WTBLON_TOP_WDUCR))
0435 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
0436
0437 #define MT_WTBL_UPDATE MT_WTBLON_TOP(__OFFS(WTBL_UPDATE))
0438 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
0439 #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
0440 #define MT_WTBL_UPDATE_BUSY BIT(31)
0441
0442
0443 #define MT_WTBL_BASE 0x820d8000
0444 #define MT_WTBL_LMAC_ID GENMASK(14, 8)
0445 #define MT_WTBL_LMAC_DW GENMASK(7, 2)
0446 #define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
0447 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
0448 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
0449
0450
0451 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
0452 #define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
0453
0454 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_AWSCR0) + \
0455 (_n) * 4))
0456 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, (__OFFS(AGG_PCR0) + \
0457 (_n) * 4))
0458 #define MT_AGG_PCR0_MM_PROT BIT(0)
0459 #define MT_AGG_PCR0_GF_PROT BIT(1)
0460 #define MT_AGG_PCR0_BW20_PROT BIT(2)
0461 #define MT_AGG_PCR0_BW40_PROT BIT(4)
0462 #define MT_AGG_PCR0_BW80_PROT BIT(6)
0463 #define MT_AGG_PCR0_ERP_PROT GENMASK(12, 8)
0464 #define MT_AGG_PCR0_VHT_PROT BIT(13)
0465 #define MT_AGG_PCR0_PTA_WIN_DIS BIT(15)
0466
0467 #define MT_AGG_PCR1_RTS0_NUM_THRES GENMASK(31, 23)
0468 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
0469
0470 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, __OFFS(AGG_ACR0))
0471 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
0472 #define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
0473
0474 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, __OFFS(AGG_MRCR))
0475 #define MT_AGG_MRCR_BAR_CNT_LIMIT GENMASK(15, 12)
0476 #define MT_AGG_MRCR_LAST_RTS_CTS_RN BIT(6)
0477 #define MT_AGG_MRCR_RTS_FAIL_LIMIT GENMASK(11, 7)
0478 #define MT_AGG_MRCR_TXCMD_RTS_FAIL_LIMIT GENMASK(28, 24)
0479
0480 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR1))
0481 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, __OFFS(AGG_ATCR3))
0482
0483
0484 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
0485 #define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
0486
0487 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, __OFFS(ARB_SCR))
0488 #define MT_ARB_SCR_TX_DISABLE BIT(8)
0489 #define MT_ARB_SCR_RX_DISABLE BIT(9)
0490
0491 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, (__OFFS(ARB_DRNGR0) + \
0492 (_n) * 4))
0493
0494
0495 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
0496 #define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
0497
0498 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
0499 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
0500 #define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
0501 #define MT_WF_RFCR_DROP_VERSION BIT(3)
0502 #define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
0503 #define MT_WF_RFCR_DROP_MCAST BIT(5)
0504 #define MT_WF_RFCR_DROP_BCAST BIT(6)
0505 #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
0506 #define MT_WF_RFCR_DROP_A3_MAC BIT(8)
0507 #define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
0508 #define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
0509 #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
0510 #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
0511 #define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
0512 #define MT_WF_RFCR_DROP_CTS BIT(14)
0513 #define MT_WF_RFCR_DROP_RTS BIT(15)
0514 #define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
0515 #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
0516 #define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
0517 #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
0518 #define MT_WF_RFCR_DROP_NDPA BIT(20)
0519 #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
0520
0521 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
0522 #define MT_WF_RFCR1_DROP_ACK BIT(4)
0523 #define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
0524 #define MT_WF_RFCR1_DROP_BA BIT(6)
0525 #define MT_WF_RFCR1_DROP_CFEND BIT(7)
0526 #define MT_WF_RFCR1_DROP_CFACK BIT(8)
0527
0528 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
0529 #define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
0530
0531
0532 #define MT_WFDMA0_BASE __REG(WFDMA0_ADDR)
0533 #define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
0534
0535 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
0536 #define MT_WFDMA0_RST_LOGIC_RST BIT(4)
0537 #define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
0538
0539 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
0540 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
0541 #define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
0542 #define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
0543
0544 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
0545 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
0546 #define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
0547 #define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
0548 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
0549 #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
0550
0551 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
0552 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
0553 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
0554 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
0555
0556
0557 #define MT_WFDMA1_BASE 0xd5000
0558 #define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
0559
0560 #define MT_WFDMA1_RST MT_WFDMA1(0x100)
0561 #define MT_WFDMA1_RST_LOGIC_RST BIT(4)
0562 #define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
0563
0564 #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
0565 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
0566 #define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
0567 #define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
0568
0569 #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
0570 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
0571 #define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
0572 #define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
0573 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
0574 #define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
0575
0576 #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
0577 #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
0578
0579
0580 #define MT_WFDMA_EXT_CSR_BASE __REG(WFDMA_EXT_CSR_ADDR)
0581 #define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000
0582 #define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
0583 #define MT_WFDMA_EXT_CSR_PHYS(ofs) (MT_WFDMA_EXT_CSR_PHYS_BASE + (ofs))
0584
0585 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30)
0586 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
0587 #define MT_WFDMA_HOST_CONFIG_WED BIT(1)
0588
0589 #define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34)
0590 #define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0)
0591 #define MT_WFDMA_WED_RING_CONTROL_TX1 GENMASK(12, 8)
0592 #define MT_WFDMA_WED_RING_CONTROL_RX1 GENMASK(20, 16)
0593
0594 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44)
0595 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
0596
0597 #define MT_PCIE_RECOG_ID 0xd7090
0598 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
0599 #define MT_PCIE_RECOG_ID_SEM BIT(31)
0600
0601 #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
0602
0603 #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
0604 #define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400)
0605
0606
0607 #define MT_WFDMA0_PCIE1_BASE __REG(WFDMA0_PCIE1_ADDR)
0608 #define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
0609
0610 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
0611 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
0612 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
0613 #define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
0614
0615
0616 #define MT_WFDMA1_PCIE1_BASE 0xd9000
0617 #define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA1_PCIE1_BASE + (ofs))
0618
0619 #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
0620 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
0621 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
0622 #define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
0623
0624
0625 #define __RXQ(q) ((q) + __MT_MCUQ_MAX)
0626 #define __TXQ(q) (__RXQ(q) + MT_RXQ_BAND2)
0627
0628 #define MT_Q_ID(q) (dev->q_id[(q)])
0629 #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \
0630 MT_WFDMA1_BASE : MT_WFDMA0_BASE)
0631
0632 #define MT_MCUQ_ID(q) MT_Q_ID(q)
0633 #define MT_TXQ_ID(q) MT_Q_ID(__TXQ(q))
0634 #define MT_RXQ_ID(q) MT_Q_ID(__RXQ(q))
0635
0636 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
0637 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
0638 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
0639
0640 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
0641 MT_MCUQ_ID(q)* 0x4)
0642 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
0643 MT_RXQ_ID(q)* 0x4)
0644 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
0645 MT_TXQ_ID(q)* 0x4)
0646
0647 #define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
0648 #define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
0649
0650 #define MT_INT1_SOURCE_CSR __REG(INT1_SOURCE_CSR)
0651 #define MT_INT1_MASK_CSR __REG(INT1_MASK_CSR)
0652
0653 #define MT_INT_RX_DONE_BAND0 BIT(16)
0654 #define MT_INT_RX_DONE_BAND1 BIT(17)
0655 #define MT_INT_RX_DONE_WM BIT(0)
0656 #define MT_INT_RX_DONE_WA BIT(1)
0657 #define MT_INT_RX_DONE_WA_MAIN BIT(1)
0658 #define MT_INT_RX_DONE_WA_EXT BIT(2)
0659 #define MT_INT_MCU_CMD BIT(29)
0660 #define MT_INT_RX_DONE_BAND0_MT7916 BIT(22)
0661 #define MT_INT_RX_DONE_BAND1_MT7916 BIT(23)
0662 #define MT_INT_RX_DONE_WA_MAIN_MT7916 BIT(2)
0663 #define MT_INT_RX_DONE_WA_EXT_MT7916 BIT(3)
0664
0665 #define MT_INT_RX(q) (dev->q_int_mask[__RXQ(q)])
0666 #define MT_INT_TX_MCU(q) (dev->q_int_mask[(q)])
0667
0668 #define MT_INT_RX_DONE_MCU (MT_INT_RX(MT_RXQ_MCU) | \
0669 MT_INT_RX(MT_RXQ_MCU_WA))
0670
0671 #define MT_INT_BAND0_RX_DONE (MT_INT_RX(MT_RXQ_MAIN) | \
0672 MT_INT_RX(MT_RXQ_MAIN_WA))
0673
0674 #define MT_INT_BAND1_RX_DONE (MT_INT_RX(MT_RXQ_BAND1) | \
0675 MT_INT_RX(MT_RXQ_BAND1_WA) | \
0676 MT_INT_RX(MT_RXQ_MAIN_WA))
0677
0678 #define MT_INT_RX_DONE_ALL (MT_INT_RX_DONE_MCU | \
0679 MT_INT_BAND0_RX_DONE | \
0680 MT_INT_BAND1_RX_DONE)
0681
0682 #define MT_INT_TX_DONE_FWDL BIT(26)
0683 #define MT_INT_TX_DONE_MCU_WM BIT(27)
0684 #define MT_INT_TX_DONE_MCU_WA BIT(15)
0685 #define MT_INT_TX_DONE_BAND0 BIT(30)
0686 #define MT_INT_TX_DONE_BAND1 BIT(31)
0687 #define MT_INT_TX_DONE_MCU_WA_MT7916 BIT(25)
0688
0689 #define MT_INT_TX_DONE_MCU (MT_INT_TX_MCU(MT_MCUQ_WA) | \
0690 MT_INT_TX_MCU(MT_MCUQ_WM) | \
0691 MT_INT_TX_MCU(MT_MCUQ_FWDL))
0692
0693 #define MT_MCU_CMD __REG(INT_MCU_CMD_SOURCE)
0694 #define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
0695 #define MT_MCU_CMD_STOP_DMA BIT(2)
0696 #define MT_MCU_CMD_RESET_DONE BIT(3)
0697 #define MT_MCU_CMD_RECOVERY_DONE BIT(4)
0698 #define MT_MCU_CMD_NORMAL_STATE BIT(5)
0699 #define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
0700
0701
0702 #define MT_TOP_RGU_BASE 0x18000000
0703 #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
0704 #define MT_TOP_PWR_KEY (0x5746 << 16)
0705 #define MT_TOP_PWR_SW_RST BIT(0)
0706 #define MT_TOP_PWR_SW_PWR_ON GENMASK(3, 2)
0707 #define MT_TOP_PWR_HW_CTRL BIT(4)
0708 #define MT_TOP_PWR_PWR_ON BIT(7)
0709
0710 #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050)
0711 #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054)
0712 #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010)
0713 #define MT_TOP_PWR_EN_MASK BIT(7)
0714 #define MT_TOP_PWR_ACK_MASK BIT(6)
0715 #define MT_TOP_PWR_KEY_MASK GENMASK(31, 16)
0716
0717 #define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120)
0718 #define MT7986_TOP_WM_RESET_MASK BIT(0)
0719
0720
0721 #define MT_HIF_REMAP_L1 0xf11ac
0722 #define MT_HIF_REMAP_L1_MT7916 0xfe260
0723 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
0724 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
0725 #define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
0726 #define MT_HIF_REMAP_BASE_L1 0xe0000
0727
0728 #define MT_HIF_REMAP_L2 0xf11b0
0729 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
0730 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
0731 #define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
0732 #define MT_HIF_REMAP_L2_MT7916 0x1b8
0733 #define MT_HIF_REMAP_L2_MASK_MT7916 GENMASK(31, 16)
0734 #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0)
0735 #define MT_HIF_REMAP_L2_BASE_MT7916 GENMASK(31, 16)
0736 #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000
0737
0738 #define MT_INFRA_BASE 0x18000000
0739 #define MT_WFSYS0_PHY_START 0x18400000
0740 #define MT_WFSYS1_PHY_START 0x18800000
0741 #define MT_WFSYS1_PHY_END 0x18bfffff
0742 #define MT_CBTOP1_PHY_START 0x70000000
0743 #define MT_CBTOP1_PHY_END __REG(CBTOP1_PHY_END)
0744 #define MT_CBTOP2_PHY_START 0xf0000000
0745 #define MT_CBTOP2_PHY_END 0xffffffff
0746 #define MT_INFRA_MCU_START 0x7c000000
0747 #define MT_INFRA_MCU_END __REG(INFRA_MCU_ADDR_END)
0748 #define MT_CONN_INFRA_OFFSET(p) ((p) - MT_INFRA_BASE)
0749
0750
0751 #define MT_CONN_INFRA_BASE 0x18001000
0752 #define MT_CONN_INFRA(ofs) (MT_CONN_INFRA_BASE + (ofs))
0753
0754 #define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020)
0755
0756 #define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030)
0757 #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0)
0758 #define MT_CONN_INFRA_ADIE2_RESET_MASK BIT(2)
0759
0760 #define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380)
0761
0762 #define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300)
0763 #define MT_CONN_INFRA_OSC_RC_EN_MASK BIT(7)
0764 #define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0)
0765
0766 #define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200)
0767 #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0)
0768
0769 #define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540)
0770 #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0)
0771
0772 #define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544)
0773 #define MT_CONN_INFRA_CONN_WF_MASK (BIT(29) | BIT(31))
0774 #define MT_CONN_INFRA_CONN (BIT(25) | BIT(29) | BIT(31))
0775
0776 #define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414)
0777 #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0)
0778 #define MT_CONN_INFRA_INFRA_REQ_MASK BIT(5)
0779
0780
0781 #define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19))
0782 #define MT_AFE_CTRL(_band, ofs) (MT_AFE_CTRL_BASE(_band) + (ofs))
0783
0784 #define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00)
0785 #define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04)
0786 #define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08)
0787 #define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c)
0788
0789 #define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4)
0790 #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
0791 #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
0792 FIELD_PREP(GENMASK(14, 0), 0x7e4))
0793 #define MT_AFE_BPLL_CFG_MASK GENMASK(7, 6)
0794 #define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0)
0795 #define MT_AFE_MCU_WPLL_CFG_MASK GENMASK(3, 2)
0796 #define MT_AFE_MCU_BPLL_CFG_MASK GENMASK(17, 16)
0797 #define MT_AFE_PLL_CFG_MASK (MT_AFE_BPLL_CFG_MASK | \
0798 MT_AFE_WPLL_CFG_MASK | \
0799 MT_AFE_MCU_WPLL_CFG_MASK | \
0800 MT_AFE_MCU_BPLL_CFG_MASK)
0801 #define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
0802 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
0803 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
0804 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
0805
0806 #define MT_AFE_DIG_TOP_01_MASK GENMASK(18, 15)
0807 #define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
0808
0809 #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0)
0810 #define MT_AFE_RG_WBG_EN_BPLL_UP_MASK BIT(21)
0811 #define MT_AFE_RG_WBG_EN_WPLL_UP_MASK BIT(20)
0812 #define MT_AFE_RG_WBG_EN_PLL_UP_MASK (MT_AFE_RG_WBG_EN_BPLL_UP_MASK | \
0813 MT_AFE_RG_WBG_EN_WPLL_UP_MASK)
0814 #define MT_AFE_RG_WBG_EN_TXCAL_MASK GENMASK(21, 17)
0815
0816 #define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19))
0817 #define MT_ADIE_SLP_CTRL(_band, ofs) (MT_ADIE_SLP_CTRL_BASE(_band) + (ofs))
0818
0819 #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120)
0820
0821
0822 #define MT_ADIE_CHIP_ID 0x02c
0823 #define MT_ADIE_VERSION_MASK GENMASK(15, 0)
0824 #define MT_ADIE_CHIP_ID_MASK GENMASK(31, 16)
0825 #define MT_ADIE_IDX0 GENMASK(15, 0)
0826 #define MT_ADIE_IDX1 GENMASK(31, 16)
0827
0828 #define MT_ADIE_RG_TOP_THADC_BG 0x034
0829 #define MT_ADIE_VRPI_SEL_CR_MASK GENMASK(15, 12)
0830 #define MT_ADIE_VRPI_SEL_EFUSE_MASK GENMASK(6, 3)
0831
0832 #define MT_ADIE_RG_TOP_THADC 0x038
0833 #define MT_ADIE_PGA_GAIN_MASK GENMASK(25, 23)
0834 #define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0)
0835 #define MT_ADIE_LDO_CTRL_MASK GENMASK(27, 26)
0836 #define MT_ADIE_LDO_CTRL_EFUSE_MASK GENMASK(6, 5)
0837
0838 #define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070
0839 #define MT_ADIE_EFUSE_RDATA0 0x130
0840
0841 #define MT_ADIE_EFUSE2_CTRL 0x148
0842 #define MT_ADIE_EFUSE_CTRL_MASK BIT(1)
0843
0844 #define MT_ADIE_EFUSE_CFG 0x144
0845 #define MT_ADIE_EFUSE_MODE_MASK GENMASK(7, 6)
0846 #define MT_ADIE_EFUSE_ADDR_MASK GENMASK(25, 16)
0847 #define MT_ADIE_EFUSE_VALID_MASK BIT(29)
0848 #define MT_ADIE_EFUSE_KICK_MASK BIT(30)
0849
0850 #define MT_ADIE_THADC_ANALOG 0x3a6
0851
0852 #define MT_ADIE_THADC_SLOP 0x3a7
0853 #define MT_ADIE_ANA_EN_MASK BIT(7)
0854
0855 #define MT_ADIE_7975_XTAL_CAL 0x3a1
0856 #define MT_ADIE_TRIM_MASK GENMASK(6, 0)
0857 #define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0)
0858 #define MT_ADIE_XO_TRIM_EN_MASK BIT(7)
0859 #define MT_ADIE_XTAL_DECREASE_MASK BIT(6)
0860
0861 #define MT_ADIE_7975_XO_TRIM2 0x3a2
0862 #define MT_ADIE_7975_XO_TRIM3 0x3a3
0863 #define MT_ADIE_7975_XO_TRIM4 0x3a4
0864 #define MT_ADIE_7975_XTAL_EN 0x3a5
0865
0866 #define MT_ADIE_XO_TRIM_FLOW 0x3ac
0867 #define MT_ADIE_XTAL_AXM_80M_OSC 0x390
0868 #define MT_ADIE_XTAL_AXM_40M_OSC 0x391
0869 #define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398
0870 #define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399
0871 #define MT_ADIE_WRI_CK_SEL 0x4ac
0872 #define MT_ADIE_RG_STRAP_PIN_IN 0x4fc
0873 #define MT_ADIE_XTAL_C1 0x654
0874 #define MT_ADIE_XTAL_C2 0x658
0875 #define MT_ADIE_RG_XO_01 0x65c
0876 #define MT_ADIE_RG_XO_03 0x664
0877
0878 #define MT_ADIE_CLK_EN 0xa00
0879
0880 #define MT_ADIE_7975_XTAL 0xa18
0881 #define MT_ADIE_7975_XTAL_EN_MASK BIT(29)
0882
0883 #define MT_ADIE_7975_COCLK 0xa1c
0884 #define MT_ADIE_7975_XO_2 0xa84
0885 #define MT_ADIE_7975_XO_2_FIX_EN BIT(31)
0886
0887 #define MT_ADIE_7975_XO_CTRL2 0xa94
0888 #define MT_ADIE_7975_XO_CTRL2_C1_MASK GENMASK(26, 20)
0889 #define MT_ADIE_7975_XO_CTRL2_C2_MASK GENMASK(18, 12)
0890 #define MT_ADIE_7975_XO_CTRL2_MASK (MT_ADIE_7975_XO_CTRL2_C1_MASK | \
0891 MT_ADIE_7975_XO_CTRL2_C2_MASK)
0892
0893 #define MT_ADIE_7975_XO_CTRL6 0xaa4
0894 #define MT_ADIE_7975_XO_CTRL6_MASK BIT(16)
0895
0896
0897 #define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19))
0898 #define MT_TOP_SPI_ADIE(_band, ofs) (MT_TOP_SPI_ADIE_BASE(_band) + (ofs))
0899
0900 #define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0)
0901 #define MT_TOP_SPI_POLLING_BIT BIT(5)
0902
0903 #define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50)
0904 #define MT_TOP_SPI_READ_ADDR_FORMAT (BIT(12) | BIT(13) | BIT(15))
0905 #define MT_TOP_SPI_WRITE_ADDR_FORMAT (BIT(13) | BIT(15))
0906
0907 #define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54)
0908 #define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58)
0909
0910
0911 #define MT_INFRA_CKGEN_BASE 0x18009000
0912 #define MT_INFRA_CKGEN(ofs) (MT_INFRA_CKGEN_BASE + (ofs))
0913
0914 #define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00)
0915 #define MT_INFRA_CKGEN_BUS_CLK_SEL_MASK BIT(23)
0916 #define MT_INFRA_CKGEN_BUS_RDY_SEL_MASK BIT(29)
0917
0918 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008)
0919 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c)
0920
0921 #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040)
0922 #define MT_INFRA_CKGEN_DIV_SEL_MASK GENMASK(7, 2)
0923 #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0)
0924
0925
0926 #define MT_INFRA_BUS_BASE 0x1800e000
0927 #define MT_INFRA_BUS(ofs) (MT_INFRA_BUS_BASE + (ofs))
0928
0929 #define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300)
0930 #define MT_INFRA_BUS_TIMEOUT_LIMIT_MASK GENMASK(14, 7)
0931 #define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0)
0932
0933 #define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c)
0934 #define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360)
0935 #define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
0936
0937
0938 #define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
0939 #define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
0940 #define MT_ADIE_TYPE_MASK BIT(1)
0941
0942
0943 #define MT_FW_EXCEPTION __REG(FW_EXCEPTION_ADDR)
0944
0945 #define MT_SWDEF_BASE __REG(SWDEF_BASE_ADDR)
0946
0947 #define MT_SWDEF(ofs) (MT_SWDEF_BASE + (ofs))
0948 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
0949 #define MT_SWDEF_NORMAL_MODE 0
0950 #define MT_SWDEF_ICAP_MODE 1
0951 #define MT_SWDEF_SPECTRUM_MODE 2
0952
0953 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
0954 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
0955 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
0956 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C)
0957 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
0958 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
0959 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
0960 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C)
0961 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060)
0962 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064)
0963
0964 #define MT_DIC_CMD_REG_BASE 0x41f000
0965 #define MT_DIC_CMD_REG(ofs) (MT_DIC_CMD_REG_BASE + (ofs))
0966 #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10)
0967
0968 #define MT_CPU_UTIL_BASE 0x41f030
0969 #define MT_CPU_UTIL(ofs) (MT_CPU_UTIL_BASE + (ofs))
0970 #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00)
0971 #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04)
0972 #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08)
0973 #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c)
0974 #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c)
0975
0976
0977 #define MT_LED_TOP_BASE 0x18013000
0978 #define MT_LED_PHYS(_n) (MT_LED_TOP_BASE + (_n))
0979
0980 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
0981 #define MT_LED_CTRL_KICK BIT(7)
0982 #define MT_LED_CTRL_BLINK_MODE BIT(2)
0983 #define MT_LED_CTRL_POLARITY BIT(1)
0984
0985 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
0986 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
0987 #define MT_LED_TX_BLINK_OFF_MASK GENMASK(15, 8)
0988
0989 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
0990
0991 #define MT_LED_GPIO_MUX2 0x70005058
0992 #define MT_LED_GPIO_MUX3 0x7000505C
0993 #define MT_LED_GPIO_SEL_MASK GENMASK(11, 8)
0994
0995
0996 #define MT_TOP_BASE 0x18060000
0997 #define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
0998
0999 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
1000 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
1001 #define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
1002 #define MT_TOP_LPCR_HOST_FW_OWN_STAT BIT(2)
1003
1004 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
1005 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
1006
1007 #define MT_TOP_MISC MT_TOP(0xf0)
1008 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
1009
1010 #define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4)
1011 #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0)
1012
1013 #define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4)
1014 #define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0)
1015
1016 #define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0)
1017 #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0)
1018
1019 #define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc)
1020 #define MT_TOP_WFSYS_RESET_STATUS_MASK BIT(30)
1021
1022
1023 #define MT_SEMA_BASE 0x18070000
1024 #define MT_SEMA(ofs) (MT_SEMA_BASE + (ofs))
1025
1026 #define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4))
1027 #define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4))
1028 #define MT_SEMA_RFSPI_STATUS_MASK BIT(1)
1029
1030
1031 #define MT_MCU_BUS_BASE 0x18400000
1032 #define MT_MCU_BUS(ofs) (MT_MCU_BUS_BASE + (ofs))
1033
1034 #define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440)
1035 #define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0)
1036 #define MT_MCU_BUS_TIMEOUT_CG_EN_MASK BIT(28)
1037 #define MT_MCU_BUS_TIMEOUT_EN_MASK BIT(31)
1038
1039 #define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120)
1040
1041
1042 #define MT_TOP_CFG_BASE 0x184b0000
1043 #define MT_TOP_CFG(ofs) (MT_TOP_CFG_BASE + (ofs))
1044
1045 #define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010)
1046
1047
1048 #define MT_TOP_CFG_ON_BASE 0x184c1000
1049 #define MT_TOP_CFG_ON(ofs) (MT_TOP_CFG_ON_BASE + (ofs))
1050
1051 #define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604)
1052
1053
1054 #define MT_SLP_BASE 0x184c3000
1055 #define MT_SLP(ofs) (MT_SLP_BASE + (ofs))
1056
1057 #define MT_SLP_STATUS MT_SLP(0x00c)
1058 #define MT_SLP_WFDMA2CONN_MASK (BIT(21) | BIT(23))
1059 #define MT_SLP_CTRL_EN_MASK BIT(0)
1060 #define MT_SLP_CTRL_BSY_MASK BIT(1)
1061
1062
1063 #define MT_MCU_BUS_DBG_BASE 0x18500000
1064 #define MT_MCU_BUS_DBG(ofs) (MT_MCU_BUS_DBG_BASE + (ofs))
1065
1066 #define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0)
1067 #define MT_MCU_BUS_DBG_TIMEOUT_SET_MASK GENMASK(31, 16)
1068 #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
1069 #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2)
1070
1071 #define MT_HW_BOUND 0x70010020
1072 #define MT_HW_REV 0x70010204
1073 #define MT_WF_SUBSYS_RST 0x70002600
1074
1075
1076 #define MT_PCIE_MAC_BASE 0x74030000
1077 #define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
1078 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
1079
1080 #define MT_PCIE1_MAC_INT_ENABLE 0x74020188
1081 #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188
1082
1083 #define MT_WM_MCU_PC 0x7c060204
1084 #define MT_WA_MCU_PC 0x7c06020c
1085
1086
1087 #define MT_WF_PP_TOP_BASE 0x820cc000
1088 #define MT_WF_PP_TOP(ofs) (MT_WF_PP_TOP_BASE + (ofs))
1089
1090 #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8)
1091 #define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK BIT(6)
1092
1093 #define MT_WF_IRPI_BASE 0x83000000
1094 #define MT_WF_IRPI(ofs) (MT_WF_IRPI_BASE + (ofs))
1095
1096 #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1097 #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1098
1099
1100 #define MT_WF_PHY_BASE 0x83080000
1101 #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
1102
1103 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
1104 #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20))
1105 #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0)
1106 #define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
1107
1108 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
1109 #define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20))
1110 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
1111 #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
1112
1113 #define MT_MCU_WM_CIRQ_BASE 0x89010000
1114 #define MT_MCU_WM_CIRQ(ofs) (MT_MCU_WM_CIRQ_BASE + (ofs))
1115 #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80)
1116 #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0)
1117
1118 #endif
