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0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #ifndef __MT7915_H
0005 #define __MT7915_H
0006 
0007 #include <linux/interrupt.h>
0008 #include <linux/ktime.h>
0009 #include "../mt76_connac.h"
0010 #include "regs.h"
0011 
0012 #define MT7915_MAX_INTERFACES       19
0013 #define MT7915_WTBL_SIZE        288
0014 #define MT7916_WTBL_SIZE        544
0015 #define MT7915_WTBL_RESERVED        (mt7915_wtbl_size(dev) - 1)
0016 #define MT7915_WTBL_STA         (MT7915_WTBL_RESERVED - \
0017                      MT7915_MAX_INTERFACES)
0018 
0019 #define MT7915_WATCHDOG_TIME        (HZ / 10)
0020 #define MT7915_RESET_TIMEOUT        (30 * HZ)
0021 
0022 #define MT7915_TX_RING_SIZE     2048
0023 #define MT7915_TX_MCU_RING_SIZE     256
0024 #define MT7915_TX_FWDL_RING_SIZE    128
0025 
0026 #define MT7915_RX_RING_SIZE     1536
0027 #define MT7915_RX_MCU_RING_SIZE     512
0028 
0029 #define MT7915_FIRMWARE_WA      "mediatek/mt7915_wa.bin"
0030 #define MT7915_FIRMWARE_WM      "mediatek/mt7915_wm.bin"
0031 #define MT7915_ROM_PATCH        "mediatek/mt7915_rom_patch.bin"
0032 
0033 #define MT7916_FIRMWARE_WA      "mediatek/mt7916_wa.bin"
0034 #define MT7916_FIRMWARE_WM      "mediatek/mt7916_wm.bin"
0035 #define MT7916_ROM_PATCH        "mediatek/mt7916_rom_patch.bin"
0036 
0037 #define MT7986_FIRMWARE_WA      "mediatek/mt7986_wa.bin"
0038 #define MT7986_FIRMWARE_WM      "mediatek/mt7986_wm.bin"
0039 #define MT7986_FIRMWARE_WM_MT7975   "mediatek/mt7986_wm_mt7975.bin"
0040 #define MT7986_ROM_PATCH        "mediatek/mt7986_rom_patch.bin"
0041 #define MT7986_ROM_PATCH_MT7975     "mediatek/mt7986_rom_patch_mt7975.bin"
0042 
0043 #define MT7915_EEPROM_DEFAULT       "mediatek/mt7915_eeprom.bin"
0044 #define MT7915_EEPROM_DEFAULT_DBDC  "mediatek/mt7915_eeprom_dbdc.bin"
0045 #define MT7916_EEPROM_DEFAULT       "mediatek/mt7916_eeprom.bin"
0046 #define MT7986_EEPROM_MT7975_DEFAULT        "mediatek/mt7986_eeprom_mt7975.bin"
0047 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT   "mediatek/mt7986_eeprom_mt7975_dual.bin"
0048 #define MT7986_EEPROM_MT7976_DEFAULT        "mediatek/mt7986_eeprom_mt7976.bin"
0049 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC   "mediatek/mt7986_eeprom_mt7976_dbdc.bin"
0050 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT   "mediatek/mt7986_eeprom_mt7976_dual.bin"
0051 
0052 #define MT7915_EEPROM_SIZE      3584
0053 #define MT7916_EEPROM_SIZE      4096
0054 
0055 #define MT7915_EEPROM_BLOCK_SIZE    16
0056 #define MT7915_TOKEN_SIZE       8192
0057 
0058 #define MT7915_CFEND_RATE_DEFAULT   0x49    /* OFDM 24M */
0059 #define MT7915_CFEND_RATE_11B       0x03    /* 11B LP, 11M */
0060 
0061 #define MT7915_THERMAL_THROTTLE_MAX 100
0062 #define MT7915_CDEV_THROTTLE_MAX    99
0063 
0064 #define MT7915_SKU_RATE_NUM     161
0065 
0066 #define MT7915_MAX_TWT_AGRT     16
0067 #define MT7915_MAX_STA_TWT_AGRT     8
0068 #define MT7915_MIN_TWT_DUR 64
0069 #define MT7915_MAX_QUEUE        (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2)
0070 
0071 struct mt7915_vif;
0072 struct mt7915_sta;
0073 struct mt7915_dfs_pulse;
0074 struct mt7915_dfs_pattern;
0075 
0076 enum mt7915_txq_id {
0077     MT7915_TXQ_FWDL = 16,
0078     MT7915_TXQ_MCU_WM,
0079     MT7915_TXQ_BAND0,
0080     MT7915_TXQ_BAND1,
0081     MT7915_TXQ_MCU_WA,
0082 };
0083 
0084 enum mt7915_rxq_id {
0085     MT7915_RXQ_BAND0 = 0,
0086     MT7915_RXQ_BAND1,
0087     MT7915_RXQ_MCU_WM = 0,
0088     MT7915_RXQ_MCU_WA,
0089     MT7915_RXQ_MCU_WA_EXT,
0090 };
0091 
0092 enum mt7916_rxq_id {
0093     MT7916_RXQ_MCU_WM = 0,
0094     MT7916_RXQ_MCU_WA,
0095     MT7916_RXQ_MCU_WA_MAIN,
0096     MT7916_RXQ_MCU_WA_EXT,
0097     MT7916_RXQ_BAND0,
0098     MT7916_RXQ_BAND1,
0099 };
0100 
0101 struct mt7915_twt_flow {
0102     struct list_head list;
0103     u64 start_tsf;
0104     u64 tsf;
0105     u32 duration;
0106     u16 wcid;
0107     __le16 mantissa;
0108     u8 exp;
0109     u8 table_id;
0110     u8 id;
0111     u8 protection:1;
0112     u8 flowtype:1;
0113     u8 trigger:1;
0114     u8 sched:1;
0115 };
0116 
0117 struct mt7915_sta {
0118     struct mt76_wcid wcid; /* must be first */
0119 
0120     struct mt7915_vif *vif;
0121 
0122     struct list_head poll_list;
0123     struct list_head rc_list;
0124     u32 airtime_ac[8];
0125 
0126     unsigned long changed;
0127     unsigned long jiffies;
0128     unsigned long ampdu_state;
0129 
0130     struct mt76_sta_stats stats;
0131 
0132     struct mt76_connac_sta_key_conf bip;
0133 
0134     struct {
0135         u8 flowid_mask;
0136         struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT];
0137     } twt;
0138 };
0139 
0140 struct mt7915_vif_cap {
0141     bool ht_ldpc:1;
0142     bool vht_ldpc:1;
0143     bool he_ldpc:1;
0144     bool vht_su_ebfer:1;
0145     bool vht_su_ebfee:1;
0146     bool vht_mu_ebfer:1;
0147     bool vht_mu_ebfee:1;
0148     bool he_su_ebfer:1;
0149     bool he_su_ebfee:1;
0150     bool he_mu_ebfer:1;
0151 };
0152 
0153 struct mt7915_vif {
0154     struct mt76_vif mt76; /* must be first */
0155 
0156     struct mt7915_vif_cap cap;
0157     struct mt7915_sta sta;
0158     struct mt7915_phy *phy;
0159 
0160     struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
0161     struct cfg80211_bitrate_mask bitrate_mask;
0162 };
0163 
0164 /* per-phy stats.  */
0165 struct mib_stats {
0166     u32 ack_fail_cnt;
0167     u32 fcs_err_cnt;
0168     u32 rts_cnt;
0169     u32 rts_retries_cnt;
0170     u32 ba_miss_cnt;
0171     u32 tx_bf_cnt;
0172     u32 tx_mu_mpdu_cnt;
0173     u32 tx_mu_acked_mpdu_cnt;
0174     u32 tx_su_acked_mpdu_cnt;
0175     u32 tx_bf_ibf_ppdu_cnt;
0176     u32 tx_bf_ebf_ppdu_cnt;
0177 
0178     u32 tx_bf_rx_fb_all_cnt;
0179     u32 tx_bf_rx_fb_he_cnt;
0180     u32 tx_bf_rx_fb_vht_cnt;
0181     u32 tx_bf_rx_fb_ht_cnt;
0182 
0183     u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */
0184     u32 tx_bf_rx_fb_nc_cnt;
0185     u32 tx_bf_rx_fb_nr_cnt;
0186     u32 tx_bf_fb_cpl_cnt;
0187     u32 tx_bf_fb_trig_cnt;
0188 
0189     u32 tx_ampdu_cnt;
0190     u32 tx_stop_q_empty_cnt;
0191     u32 tx_mpdu_attempts_cnt;
0192     u32 tx_mpdu_success_cnt;
0193     u32 tx_pkt_ebf_cnt;
0194     u32 tx_pkt_ibf_cnt;
0195 
0196     u32 tx_rwp_fail_cnt;
0197     u32 tx_rwp_need_cnt;
0198 
0199     /* rx stats */
0200     u32 rx_fifo_full_cnt;
0201     u32 channel_idle_cnt;
0202     u32 primary_cca_busy_time;
0203     u32 secondary_cca_busy_time;
0204     u32 primary_energy_detect_time;
0205     u32 cck_mdrdy_time;
0206     u32 ofdm_mdrdy_time;
0207     u32 green_mdrdy_time;
0208     u32 rx_vector_mismatch_cnt;
0209     u32 rx_delimiter_fail_cnt;
0210     u32 rx_mrdy_cnt;
0211     u32 rx_len_mismatch_cnt;
0212     u32 rx_mpdu_cnt;
0213     u32 rx_ampdu_cnt;
0214     u32 rx_ampdu_bytes_cnt;
0215     u32 rx_ampdu_valid_subframe_cnt;
0216     u32 rx_ampdu_valid_subframe_bytes_cnt;
0217     u32 rx_pfdrop_cnt;
0218     u32 rx_vec_queue_overflow_drop_cnt;
0219     u32 rx_ba_cnt;
0220 
0221     u32 tx_amsdu[8];
0222     u32 tx_amsdu_cnt;
0223 };
0224 
0225 struct mt7915_hif {
0226     struct list_head list;
0227 
0228     struct device *dev;
0229     void __iomem *regs;
0230     int irq;
0231 };
0232 
0233 struct mt7915_phy {
0234     struct mt76_phy *mt76;
0235     struct mt7915_dev *dev;
0236 
0237     struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
0238 
0239     struct ieee80211_vif *monitor_vif;
0240 
0241     struct thermal_cooling_device *cdev;
0242     u8 cdev_state;
0243     u8 throttle_state;
0244     u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
0245 
0246     u32 rxfilter;
0247     u64 omac_mask;
0248     u8 band_idx;
0249 
0250     u16 noise;
0251 
0252     s16 coverage_class;
0253     u8 slottime;
0254 
0255     u8 rdd_state;
0256 
0257     u32 trb_ts;
0258 
0259     u32 rx_ampdu_ts;
0260     u32 ampdu_ref;
0261 
0262     struct mib_stats mib;
0263     struct mt76_channel_state state_ts;
0264 
0265 #ifdef CONFIG_NL80211_TESTMODE
0266     struct {
0267         u32 *reg_backup;
0268 
0269         s32 last_freq_offset;
0270         u8 last_rcpi[4];
0271         s8 last_ib_rssi[4];
0272         s8 last_wb_rssi[4];
0273         u8 last_snr;
0274 
0275         u8 spe_idx;
0276     } test;
0277 #endif
0278 };
0279 
0280 struct mt7915_dev {
0281     union { /* must be first */
0282         struct mt76_dev mt76;
0283         struct mt76_phy mphy;
0284     };
0285 
0286     struct mt7915_hif *hif2;
0287     struct mt7915_reg_desc reg;
0288     u8 q_id[MT7915_MAX_QUEUE];
0289     u32 q_int_mask[MT7915_MAX_QUEUE];
0290     u32 wfdma_mask;
0291 
0292     const struct mt76_bus_ops *bus_ops;
0293     struct tasklet_struct irq_tasklet;
0294     struct mt7915_phy phy;
0295 
0296     /* monitor rx chain configured channel */
0297     struct cfg80211_chan_def rdd2_chandef;
0298     struct mt7915_phy *rdd2_phy;
0299 
0300     u16 chainmask;
0301     u16 chainshift;
0302     u32 hif_idx;
0303 
0304     struct work_struct init_work;
0305     struct work_struct rc_work;
0306     struct work_struct reset_work;
0307     wait_queue_head_t reset_wait;
0308     u32 reset_state;
0309 
0310     struct list_head sta_rc_list;
0311     struct list_head sta_poll_list;
0312     struct list_head twt_list;
0313     spinlock_t sta_poll_lock;
0314 
0315     u32 hw_pattern;
0316 
0317     bool dbdc_support;
0318     bool flash_mode;
0319     bool muru_debug;
0320     bool ibf;
0321 
0322     struct dentry *debugfs_dir;
0323     struct rchan *relay_fwlog;
0324 
0325     void *cal;
0326 
0327     struct {
0328         u8 debug_wm;
0329         u8 debug_wa;
0330         u8 debug_bin;
0331     } fw;
0332 
0333     struct {
0334         u16 table_mask;
0335         u8 n_agrt;
0336     } twt;
0337 
0338     struct reset_control *rstc;
0339     void __iomem *dcm;
0340     void __iomem *sku;
0341 };
0342 
0343 enum {
0344     WFDMA0 = 0x0,
0345     WFDMA1,
0346     WFDMA_EXT,
0347     __MT_WFDMA_MAX,
0348 };
0349 
0350 enum {
0351     MT_RX_SEL0,
0352     MT_RX_SEL1,
0353     MT_RX_SEL2, /* monitor chain */
0354 };
0355 
0356 enum mt7915_rdd_cmd {
0357     RDD_STOP,
0358     RDD_START,
0359     RDD_DET_MODE,
0360     RDD_RADAR_EMULATE,
0361     RDD_START_TXQ = 20,
0362     RDD_CAC_START = 50,
0363     RDD_CAC_END,
0364     RDD_NORMAL_START,
0365     RDD_DISABLE_DFS_CAL,
0366     RDD_PULSE_DBG,
0367     RDD_READ_PULSE,
0368     RDD_RESUME_BF,
0369     RDD_IRQ_OFF,
0370 };
0371 
0372 static inline struct mt7915_phy *
0373 mt7915_hw_phy(struct ieee80211_hw *hw)
0374 {
0375     struct mt76_phy *phy = hw->priv;
0376 
0377     return phy->priv;
0378 }
0379 
0380 static inline struct mt7915_dev *
0381 mt7915_hw_dev(struct ieee80211_hw *hw)
0382 {
0383     struct mt76_phy *phy = hw->priv;
0384 
0385     return container_of(phy->dev, struct mt7915_dev, mt76);
0386 }
0387 
0388 static inline struct mt7915_phy *
0389 mt7915_ext_phy(struct mt7915_dev *dev)
0390 {
0391     struct mt76_phy *phy = dev->mt76.phys[MT_BAND1];
0392 
0393     if (!phy)
0394         return NULL;
0395 
0396     return phy->priv;
0397 }
0398 
0399 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku)
0400 {
0401     u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK;
0402 
0403     if (!is_mt7986(&dev->mt76))
0404         return 0;
0405 
0406     return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask;
0407 }
0408 
0409 extern const struct ieee80211_ops mt7915_ops;
0410 extern const struct mt76_testmode_ops mt7915_testmode_ops;
0411 extern struct pci_driver mt7915_pci_driver;
0412 extern struct pci_driver mt7915_hif_driver;
0413 extern struct platform_driver mt7986_wmac_driver;
0414 
0415 #ifdef CONFIG_MT7986_WMAC
0416 int mt7986_wmac_enable(struct mt7915_dev *dev);
0417 void mt7986_wmac_disable(struct mt7915_dev *dev);
0418 #else
0419 static inline int mt7986_wmac_enable(struct mt7915_dev *dev)
0420 {
0421     return 0;
0422 }
0423 
0424 static inline void mt7986_wmac_disable(struct mt7915_dev *dev)
0425 {
0426 }
0427 #endif
0428 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
0429                      void __iomem *mem_base, u32 device_id);
0430 void mt7915_wfsys_reset(struct mt7915_dev *dev);
0431 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance);
0432 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif);
0433 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
0434 
0435 int mt7915_register_device(struct mt7915_dev *dev);
0436 void mt7915_unregister_device(struct mt7915_dev *dev);
0437 int mt7915_eeprom_init(struct mt7915_dev *dev);
0438 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev,
0439                 struct mt7915_phy *phy);
0440 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev,
0441                    struct ieee80211_channel *chan,
0442                    u8 chain_idx);
0443 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band);
0444 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2);
0445 void mt7915_dma_prefetch(struct mt7915_dev *dev);
0446 void mt7915_dma_cleanup(struct mt7915_dev *dev);
0447 int mt7915_mcu_init(struct mt7915_dev *dev);
0448 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev,
0449                    struct mt7915_vif *mvif,
0450                    struct mt7915_twt_flow *flow,
0451                    int cmd);
0452 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy,
0453                 struct ieee80211_vif *vif, bool enable);
0454 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy,
0455                 struct ieee80211_vif *vif, int enable);
0456 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif,
0457                struct ieee80211_sta *sta, bool enable);
0458 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev,
0459              struct ieee80211_ampdu_params *params,
0460              bool add);
0461 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev,
0462              struct ieee80211_ampdu_params *params,
0463              bool add);
0464 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif,
0465                 struct cfg80211_he_bss_color *he_bss_color);
0466 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0467               int enable, u32 changed);
0468 int mt7915_mcu_add_obss_spr(struct mt7915_dev *dev, struct ieee80211_vif *vif,
0469                             bool enable);
0470 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif,
0471                  struct ieee80211_sta *sta, bool changed);
0472 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif,
0473             struct ieee80211_sta *sta);
0474 int mt7915_set_channel(struct mt7915_phy *phy);
0475 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd);
0476 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif);
0477 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req);
0478 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev,
0479                    struct ieee80211_vif *vif,
0480                    struct ieee80211_sta *sta,
0481                    void *data, u32 field);
0482 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev);
0483 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset);
0484 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num);
0485 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable,
0486                bool hdr_trans);
0487 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode,
0488                   u8 en);
0489 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band);
0490 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy, bool enable);
0491 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy);
0492 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len);
0493 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action);
0494 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val);
0495 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev,
0496                 const struct mt7915_dfs_pulse *pulse);
0497 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index,
0498                 const struct mt7915_dfs_pattern *pattern);
0499 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val);
0500 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev);
0501 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy);
0502 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch);
0503 int mt7915_mcu_get_temperature(struct mt7915_phy *phy);
0504 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state);
0505 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif,
0506                struct ieee80211_sta *sta, struct rate_info *rate);
0507 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy,
0508                      struct cfg80211_chan_def *chandef);
0509 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set);
0510 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
0511 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl);
0512 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level);
0513 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb);
0514 void mt7915_mcu_exit(struct mt7915_dev *dev);
0515 
0516 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev)
0517 {
0518     return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE;
0519 }
0520 
0521 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev)
0522 {
0523     return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE;
0524 }
0525 
0526 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg,
0527                   u32 clear, u32 set);
0528 
0529 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask)
0530 {
0531     if (dev->hif2)
0532         mt7915_dual_hif_set_irq_mask(dev, false, 0, mask);
0533     else
0534         mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
0535 
0536     tasklet_schedule(&dev->irq_tasklet);
0537 }
0538 
0539 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask)
0540 {
0541     if (dev->hif2)
0542         mt7915_dual_hif_set_irq_mask(dev, true, mask, 0);
0543     else
0544         mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
0545 }
0546 
0547 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw);
0548 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask);
0549 void mt7915_mac_reset_counters(struct mt7915_phy *phy);
0550 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy);
0551 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy);
0552 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
0553                struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
0554                struct ieee80211_key_conf *key,
0555                enum mt76_txq_id qid, u32 changed);
0556 void mt7915_mac_set_timing(struct mt7915_phy *phy);
0557 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
0558                struct ieee80211_sta *sta);
0559 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
0560                struct ieee80211_sta *sta);
0561 void mt7915_mac_work(struct work_struct *work);
0562 void mt7915_mac_reset_work(struct work_struct *work);
0563 void mt7915_mac_sta_rc_work(struct work_struct *work);
0564 void mt7915_mac_update_stats(struct mt7915_phy *phy);
0565 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev,
0566                   struct mt7915_sta *msta,
0567                   u8 flowid);
0568 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw,
0569                   struct ieee80211_sta *sta,
0570                   struct ieee80211_twt_setup *twt);
0571 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
0572               enum mt76_txq_id qid, struct mt76_wcid *wcid,
0573               struct ieee80211_sta *sta,
0574               struct mt76_tx_info *tx_info);
0575 void mt7915_tx_token_put(struct mt7915_dev *dev);
0576 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
0577              struct sk_buff *skb);
0578 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len);
0579 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
0580 void mt7915_stats_work(struct work_struct *work);
0581 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force);
0582 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy);
0583 void mt7915_set_stream_he_caps(struct mt7915_phy *phy);
0584 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy);
0585 void mt7915_update_channel(struct mt76_phy *mphy);
0586 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable);
0587 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy, void *ms);
0588 int mt7915_init_debugfs(struct mt7915_phy *phy);
0589 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len);
0590 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len);
0591 #ifdef CONFIG_MAC80211_DEBUGFS
0592 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0593                 struct ieee80211_sta *sta, struct dentry *dir);
0594 #endif
0595 
0596 #endif
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