Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #include <linux/kernel.h>
0005 #include <linux/module.h>
0006 #include <linux/platform_device.h>
0007 #include <linux/pci.h>
0008 
0009 #include "mt7915.h"
0010 #include "mac.h"
0011 #include "../trace.h"
0012 
0013 static const u32 mt7915_reg[] = {
0014     [INT_SOURCE_CSR]    = 0xd7010,
0015     [INT_MASK_CSR]      = 0xd7014,
0016     [INT1_SOURCE_CSR]   = 0xd7088,
0017     [INT1_MASK_CSR]     = 0xd708c,
0018     [INT_MCU_CMD_SOURCE]    = 0xd51f0,
0019     [INT_MCU_CMD_EVENT] = 0x3108,
0020     [WFDMA0_ADDR]       = 0xd4000,
0021     [WFDMA0_PCIE1_ADDR] = 0xd8000,
0022     [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
0023     [CBTOP1_PHY_END]    = 0x77ffffff,
0024     [INFRA_MCU_ADDR_END]    = 0x7c3fffff,
0025     [FW_EXCEPTION_ADDR] = 0x219848,
0026     [SWDEF_BASE_ADDR]   = 0x41f200,
0027 };
0028 
0029 static const u32 mt7916_reg[] = {
0030     [INT_SOURCE_CSR]    = 0xd4200,
0031     [INT_MASK_CSR]      = 0xd4204,
0032     [INT1_SOURCE_CSR]   = 0xd8200,
0033     [INT1_MASK_CSR]     = 0xd8204,
0034     [INT_MCU_CMD_SOURCE]    = 0xd41f0,
0035     [INT_MCU_CMD_EVENT] = 0x2108,
0036     [WFDMA0_ADDR]       = 0xd4000,
0037     [WFDMA0_PCIE1_ADDR] = 0xd8000,
0038     [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
0039     [CBTOP1_PHY_END]    = 0x7fffffff,
0040     [INFRA_MCU_ADDR_END]    = 0x7c085fff,
0041     [FW_EXCEPTION_ADDR] = 0x022050bc,
0042     [SWDEF_BASE_ADDR]   = 0x411400,
0043 };
0044 
0045 static const u32 mt7986_reg[] = {
0046     [INT_SOURCE_CSR]    = 0x24200,
0047     [INT_MASK_CSR]      = 0x24204,
0048     [INT1_SOURCE_CSR]   = 0x28200,
0049     [INT1_MASK_CSR]     = 0x28204,
0050     [INT_MCU_CMD_SOURCE]    = 0x241f0,
0051     [INT_MCU_CMD_EVENT] = 0x54000108,
0052     [WFDMA0_ADDR]       = 0x24000,
0053     [WFDMA0_PCIE1_ADDR] = 0x28000,
0054     [WFDMA_EXT_CSR_ADDR]    = 0x27000,
0055     [CBTOP1_PHY_END]    = 0x7fffffff,
0056     [INFRA_MCU_ADDR_END]    = 0x7c085fff,
0057     [FW_EXCEPTION_ADDR] = 0x02204ffc,
0058     [SWDEF_BASE_ADDR]   = 0x411400,
0059 };
0060 
0061 static const u32 mt7915_offs[] = {
0062     [TMAC_CDTR]     = 0x090,
0063     [TMAC_ODTR]     = 0x094,
0064     [TMAC_ATCR]     = 0x098,
0065     [TMAC_TRCR0]        = 0x09c,
0066     [TMAC_ICR0]     = 0x0a4,
0067     [TMAC_ICR1]     = 0x0b4,
0068     [TMAC_CTCR0]        = 0x0f4,
0069     [TMAC_TFCR0]        = 0x1e0,
0070     [MDP_BNRCFR0]       = 0x070,
0071     [MDP_BNRCFR1]       = 0x074,
0072     [ARB_DRNGR0]        = 0x194,
0073     [ARB_SCR]       = 0x080,
0074     [RMAC_MIB_AIRTIME14]    = 0x3b8,
0075     [AGG_AWSCR0]        = 0x05c,
0076     [AGG_PCR0]      = 0x06c,
0077     [AGG_ACR0]      = 0x084,
0078     [AGG_MRCR]      = 0x098,
0079     [AGG_ATCR1]     = 0x0f0,
0080     [AGG_ATCR3]     = 0x0f4,
0081     [LPON_UTTR0]        = 0x080,
0082     [LPON_UTTR1]        = 0x084,
0083     [LPON_FRCR]     = 0x314,
0084     [MIB_SDR3]      = 0x014,
0085     [MIB_SDR4]      = 0x018,
0086     [MIB_SDR5]      = 0x01c,
0087     [MIB_SDR7]      = 0x024,
0088     [MIB_SDR8]      = 0x028,
0089     [MIB_SDR9]      = 0x02c,
0090     [MIB_SDR10]     = 0x030,
0091     [MIB_SDR11]     = 0x034,
0092     [MIB_SDR12]     = 0x038,
0093     [MIB_SDR13]     = 0x03c,
0094     [MIB_SDR14]     = 0x040,
0095     [MIB_SDR15]     = 0x044,
0096     [MIB_SDR16]     = 0x048,
0097     [MIB_SDR17]     = 0x04c,
0098     [MIB_SDR18]     = 0x050,
0099     [MIB_SDR19]     = 0x054,
0100     [MIB_SDR20]     = 0x058,
0101     [MIB_SDR21]     = 0x05c,
0102     [MIB_SDR22]     = 0x060,
0103     [MIB_SDR23]     = 0x064,
0104     [MIB_SDR24]     = 0x068,
0105     [MIB_SDR25]     = 0x06c,
0106     [MIB_SDR27]     = 0x074,
0107     [MIB_SDR28]     = 0x078,
0108     [MIB_SDR29]     = 0x07c,
0109     [MIB_SDRVEC]        = 0x080,
0110     [MIB_SDR31]     = 0x084,
0111     [MIB_SDR32]     = 0x088,
0112     [MIB_SDRMUBF]       = 0x090,
0113     [MIB_DR8]       = 0x0c0,
0114     [MIB_DR9]       = 0x0c4,
0115     [MIB_DR11]      = 0x0cc,
0116     [MIB_MB_SDR0]       = 0x100,
0117     [MIB_MB_SDR1]       = 0x104,
0118     [TX_AGG_CNT]        = 0x0a8,
0119     [TX_AGG_CNT2]       = 0x164,
0120     [MIB_ARNG]      = 0x4b8,
0121     [WTBLON_TOP_WDUCR]  = 0x0,
0122     [WTBL_UPDATE]       = 0x030,
0123     [PLE_FL_Q_EMPTY]    = 0x0b0,
0124     [PLE_FL_Q_CTRL]     = 0x1b0,
0125     [PLE_AC_QEMPTY]     = 0x500,
0126     [PLE_FREEPG_CNT]    = 0x100,
0127     [PLE_FREEPG_HEAD_TAIL]  = 0x104,
0128     [PLE_PG_HIF_GROUP]  = 0x110,
0129     [PLE_HIF_PG_INFO]   = 0x114,
0130     [AC_OFFSET]     = 0x040,
0131     [ETBF_PAR_RPT0]     = 0x068,
0132 };
0133 
0134 static const u32 mt7916_offs[] = {
0135     [TMAC_CDTR]     = 0x0c8,
0136     [TMAC_ODTR]     = 0x0cc,
0137     [TMAC_ATCR]     = 0x00c,
0138     [TMAC_TRCR0]        = 0x010,
0139     [TMAC_ICR0]     = 0x014,
0140     [TMAC_ICR1]     = 0x018,
0141     [TMAC_CTCR0]        = 0x114,
0142     [TMAC_TFCR0]        = 0x0e4,
0143     [MDP_BNRCFR0]       = 0x090,
0144     [MDP_BNRCFR1]       = 0x094,
0145     [ARB_DRNGR0]        = 0x1e0,
0146     [ARB_SCR]       = 0x000,
0147     [RMAC_MIB_AIRTIME14]    = 0x0398,
0148     [AGG_AWSCR0]        = 0x030,
0149     [AGG_PCR0]      = 0x040,
0150     [AGG_ACR0]      = 0x054,
0151     [AGG_MRCR]      = 0x068,
0152     [AGG_ATCR1]     = 0x1a8,
0153     [AGG_ATCR3]     = 0x080,
0154     [LPON_UTTR0]        = 0x360,
0155     [LPON_UTTR1]        = 0x364,
0156     [LPON_FRCR]     = 0x37c,
0157     [MIB_SDR3]      = 0x698,
0158     [MIB_SDR4]      = 0x788,
0159     [MIB_SDR5]      = 0x780,
0160     [MIB_SDR7]      = 0x5a8,
0161     [MIB_SDR8]      = 0x78c,
0162     [MIB_SDR9]      = 0x024,
0163     [MIB_SDR10]     = 0x76c,
0164     [MIB_SDR11]     = 0x790,
0165     [MIB_SDR12]     = 0x558,
0166     [MIB_SDR13]     = 0x560,
0167     [MIB_SDR14]     = 0x564,
0168     [MIB_SDR15]     = 0x568,
0169     [MIB_SDR16]     = 0x7fc,
0170     [MIB_SDR17]     = 0x800,
0171     [MIB_SDR18]     = 0x030,
0172     [MIB_SDR19]     = 0x5ac,
0173     [MIB_SDR20]     = 0x5b0,
0174     [MIB_SDR21]     = 0x5b4,
0175     [MIB_SDR22]     = 0x770,
0176     [MIB_SDR23]     = 0x774,
0177     [MIB_SDR24]     = 0x778,
0178     [MIB_SDR25]     = 0x77c,
0179     [MIB_SDR27]     = 0x080,
0180     [MIB_SDR28]     = 0x084,
0181     [MIB_SDR29]     = 0x650,
0182     [MIB_SDRVEC]        = 0x5a8,
0183     [MIB_SDR31]     = 0x55c,
0184     [MIB_SDR32]     = 0x7a8,
0185     [MIB_SDRMUBF]       = 0x7ac,
0186     [MIB_DR8]       = 0x56c,
0187     [MIB_DR9]       = 0x570,
0188     [MIB_DR11]      = 0x574,
0189     [MIB_MB_SDR0]       = 0x688,
0190     [MIB_MB_SDR1]       = 0x690,
0191     [TX_AGG_CNT]        = 0x7dc,
0192     [TX_AGG_CNT2]       = 0x7ec,
0193     [MIB_ARNG]      = 0x0b0,
0194     [WTBLON_TOP_WDUCR]  = 0x200,
0195     [WTBL_UPDATE]       = 0x230,
0196     [PLE_FL_Q_EMPTY]    = 0x360,
0197     [PLE_FL_Q_CTRL]     = 0x3e0,
0198     [PLE_AC_QEMPTY]     = 0x600,
0199     [PLE_FREEPG_CNT]    = 0x380,
0200     [PLE_FREEPG_HEAD_TAIL]  = 0x384,
0201     [PLE_PG_HIF_GROUP]  = 0x00c,
0202     [PLE_HIF_PG_INFO]   = 0x388,
0203     [AC_OFFSET]     = 0x080,
0204     [ETBF_PAR_RPT0]     = 0x100,
0205 };
0206 
0207 static const struct __map mt7915_reg_map[] = {
0208     { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
0209     { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
0210     { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
0211     { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
0212     { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
0213     { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
0214     { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
0215     { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
0216     { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
0217     { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
0218     { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
0219     { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
0220     { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
0221     { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
0222     { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
0223     { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
0224     { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
0225     { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
0226     { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
0227     { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
0228     { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
0229     { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
0230     { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
0231     { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
0232     { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
0233     { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
0234     { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
0235     { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
0236     { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
0237     { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
0238     { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
0239     { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
0240     { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
0241     { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
0242     { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
0243     { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
0244     { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
0245     { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
0246     { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
0247     { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
0248     { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
0249     { 0x0, 0x0, 0x0 }, /* imply end of search */
0250 };
0251 
0252 static const struct __map mt7916_reg_map[] = {
0253     { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
0254     { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
0255     { 0x56000000, 0x04000, 0x1000 }, /* WFDMA_2 (Reserved) */
0256     { 0x57000000, 0x05000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
0257     { 0x58000000, 0x06000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
0258     { 0x59000000, 0x07000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
0259     { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
0260     { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
0261     { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
0262     { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
0263     { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
0264     { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
0265     { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
0266     { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
0267     { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
0268     { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
0269     { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
0270     { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
0271     { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
0272     { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
0273     { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
0274     { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
0275     { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
0276     { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
0277     { 0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
0278     { 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
0279     { 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure cr) */
0280     { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
0281     { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
0282     { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
0283     { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
0284     { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
0285     { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
0286     { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
0287     { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
0288     { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
0289     { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
0290     { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
0291     { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
0292     { 0x820c4000, 0xa8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
0293     { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
0294     { 0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
0295     { 0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
0296     { 0x0, 0x0, 0x0 }, /* imply end of search */
0297 };
0298 
0299 static const struct __map mt7986_reg_map[] = {
0300     { 0x54000000, 0x402000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
0301     { 0x55000000, 0x403000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
0302     { 0x56000000, 0x404000, 0x1000 }, /* WFDMA_2 (Reserved) */
0303     { 0x57000000, 0x405000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
0304     { 0x58000000, 0x406000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
0305     { 0x59000000, 0x407000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
0306     { 0x820c0000, 0x408000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
0307     { 0x820c8000, 0x40c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
0308     { 0x820cc000, 0x40e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
0309     { 0x820e0000, 0x420000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
0310     { 0x820e1000, 0x420400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
0311     { 0x820e2000, 0x420800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
0312     { 0x820e3000, 0x420c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
0313     { 0x820e4000, 0x421000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
0314     { 0x820e5000, 0x421400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
0315     { 0x820ce000, 0x421c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
0316     { 0x820e7000, 0x421e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
0317     { 0x820cf000, 0x422000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
0318     { 0x820e9000, 0x423400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
0319     { 0x820ea000, 0x424000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
0320     { 0x820eb000, 0x424200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
0321     { 0x820ec000, 0x424600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
0322     { 0x820ed000, 0x424800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
0323     { 0x820ca000, 0x426000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
0324     { 0x820d0000, 0x430000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
0325     { 0x00400000, 0x480000, 0x10000}, /* WF_MCU_SYSRAM */
0326     { 0x00410000, 0x490000, 0x10000}, /* WF_MCU_SYSRAM */
0327     { 0x820f0000, 0x4a0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
0328     { 0x820f1000, 0x4a0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
0329     { 0x820f2000, 0x4a0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
0330     { 0x820f3000, 0x4a0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
0331     { 0x820f4000, 0x4a1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
0332     { 0x820f5000, 0x4a1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
0333     { 0x820f7000, 0x4a1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
0334     { 0x820f9000, 0x4a3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
0335     { 0x820fa000, 0x4a4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
0336     { 0x820fb000, 0x4a4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
0337     { 0x820fc000, 0x4a4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
0338     { 0x820fd000, 0x4a4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
0339     { 0x820c4000, 0x4a8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
0340     { 0x820b0000, 0x4ae000, 0x1000 }, /* [APB2] WFSYS_ON */
0341     { 0x80020000, 0x4b0000, 0x10000}, /* WF_TOP_MISC_OFF */
0342     { 0x81020000, 0x4c0000, 0x10000}, /* WF_TOP_MISC_ON */
0343     { 0x89000000, 0x4d0000, 0x1000 }, /* WF_MCU_CFG_ON */
0344     { 0x89010000, 0x4d1000, 0x1000 }, /* WF_MCU_CIRQ */
0345     { 0x89020000, 0x4d2000, 0x1000 }, /* WF_MCU_GPT */
0346     { 0x89030000, 0x4d3000, 0x1000 }, /* WF_MCU_WDT */
0347     { 0x80010000, 0x4d4000, 0x1000 }, /* WF_AXIDMA */
0348     { 0x0, 0x0, 0x0 }, /* imply end of search */
0349 };
0350 
0351 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
0352 {
0353     u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
0354     u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
0355     u32 l1_remap;
0356 
0357     if (is_mt7986(&dev->mt76))
0358         return MT_CONN_INFRA_OFFSET(addr);
0359 
0360     l1_remap = is_mt7915(&dev->mt76) ?
0361            MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
0362 
0363     dev->bus_ops->rmw(&dev->mt76, l1_remap,
0364               MT_HIF_REMAP_L1_MASK,
0365               FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
0366     /* use read to push write */
0367     dev->bus_ops->rr(&dev->mt76, l1_remap);
0368 
0369     return MT_HIF_REMAP_BASE_L1 + offset;
0370 }
0371 
0372 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
0373 {
0374     u32 offset, base;
0375 
0376     if (is_mt7915(&dev->mt76)) {
0377         offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
0378         base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
0379 
0380         dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
0381                   MT_HIF_REMAP_L2_MASK,
0382                   FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
0383 
0384         /* use read to push write */
0385         dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
0386     } else {
0387         u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0;
0388 
0389         offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
0390         base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
0391 
0392         dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
0393                   MT_HIF_REMAP_L2_MASK_MT7916,
0394                   FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
0395 
0396         /* use read to push write */
0397         dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
0398 
0399         offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
0400     }
0401 
0402     return offset;
0403 }
0404 
0405 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
0406 {
0407     int i;
0408 
0409     if (addr < 0x100000)
0410         return addr;
0411 
0412     if (!dev->reg.map) {
0413         dev_err(dev->mt76.dev, "err: reg_map is null\n");
0414         return addr;
0415     }
0416 
0417     for (i = 0; i < dev->reg.map_size; i++) {
0418         u32 ofs;
0419 
0420         if (addr < dev->reg.map[i].phys)
0421             continue;
0422 
0423         ofs = addr - dev->reg.map[i].phys;
0424         if (ofs > dev->reg.map[i].size)
0425             continue;
0426 
0427         return dev->reg.map[i].maps + ofs;
0428     }
0429 
0430     if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
0431         (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
0432         (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
0433         return mt7915_reg_map_l1(dev, addr);
0434 
0435     if (dev_is_pci(dev->mt76.dev) &&
0436         ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
0437          (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END)))
0438         return mt7915_reg_map_l1(dev, addr);
0439 
0440     /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
0441     if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
0442         addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
0443         return mt7915_reg_map_l1(dev, addr);
0444     }
0445 
0446     return mt7915_reg_map_l2(dev, addr);
0447 }
0448 
0449 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
0450 {
0451     struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
0452     u32 addr = __mt7915_reg_addr(dev, offset);
0453 
0454     return dev->bus_ops->rr(mdev, addr);
0455 }
0456 
0457 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
0458 {
0459     struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
0460     u32 addr = __mt7915_reg_addr(dev, offset);
0461 
0462     dev->bus_ops->wr(mdev, addr, val);
0463 }
0464 
0465 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
0466 {
0467     struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
0468     u32 addr = __mt7915_reg_addr(dev, offset);
0469 
0470     return dev->bus_ops->rmw(mdev, addr, mask, val);
0471 }
0472 
0473 static int mt7915_mmio_init(struct mt76_dev *mdev,
0474                 void __iomem *mem_base,
0475                 u32 device_id)
0476 {
0477     struct mt76_bus_ops *bus_ops;
0478     struct mt7915_dev *dev;
0479 
0480     dev = container_of(mdev, struct mt7915_dev, mt76);
0481     mt76_mmio_init(&dev->mt76, mem_base);
0482 
0483     switch (device_id) {
0484     case 0x7915:
0485         dev->reg.reg_rev = mt7915_reg;
0486         dev->reg.offs_rev = mt7915_offs;
0487         dev->reg.map = mt7915_reg_map;
0488         dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
0489         break;
0490     case 0x7906:
0491         dev->reg.reg_rev = mt7916_reg;
0492         dev->reg.offs_rev = mt7916_offs;
0493         dev->reg.map = mt7916_reg_map;
0494         dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
0495         break;
0496     case 0x7986:
0497         dev->reg.reg_rev = mt7986_reg;
0498         dev->reg.offs_rev = mt7916_offs;
0499         dev->reg.map = mt7986_reg_map;
0500         dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
0501         break;
0502     default:
0503         return -EINVAL;
0504     }
0505 
0506     dev->bus_ops = dev->mt76.bus;
0507     bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
0508                    GFP_KERNEL);
0509     if (!bus_ops)
0510         return -ENOMEM;
0511 
0512     bus_ops->rr = mt7915_rr;
0513     bus_ops->wr = mt7915_wr;
0514     bus_ops->rmw = mt7915_rmw;
0515     dev->mt76.bus = bus_ops;
0516 
0517     mdev->rev = (device_id << 16) |
0518             (mt76_rr(dev, MT_HW_REV) & 0xff);
0519     dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
0520 
0521     return 0;
0522 }
0523 
0524 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
0525                   bool write_reg,
0526                   u32 clear, u32 set)
0527 {
0528     struct mt76_dev *mdev = &dev->mt76;
0529     unsigned long flags;
0530 
0531     spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
0532 
0533     mdev->mmio.irqmask &= ~clear;
0534     mdev->mmio.irqmask |= set;
0535 
0536     if (write_reg) {
0537         mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
0538         mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
0539     }
0540 
0541     spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
0542 }
0543 
0544 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
0545                     enum mt76_rxq_id q)
0546 {
0547     struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
0548 
0549     mt7915_irq_enable(dev, MT_INT_RX(q));
0550 }
0551 
0552 /* TODO: support 2/4/6/8 MSI-X vectors */
0553 static void mt7915_irq_tasklet(struct tasklet_struct *t)
0554 {
0555     struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
0556     struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
0557     u32 intr, intr1, mask;
0558 
0559     if (mtk_wed_device_active(wed)) {
0560         mtk_wed_device_irq_set_mask(wed, 0);
0561         intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
0562     } else {
0563         mt76_wr(dev, MT_INT_MASK_CSR, 0);
0564         if (dev->hif2)
0565             mt76_wr(dev, MT_INT1_MASK_CSR, 0);
0566 
0567         intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
0568         intr &= dev->mt76.mmio.irqmask;
0569         mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
0570     }
0571 
0572     if (dev->hif2) {
0573         intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
0574         intr1 &= dev->mt76.mmio.irqmask;
0575         mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
0576 
0577         intr |= intr1;
0578     }
0579 
0580     trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
0581 
0582     mask = intr & MT_INT_RX_DONE_ALL;
0583     if (intr & MT_INT_TX_DONE_MCU)
0584         mask |= MT_INT_TX_DONE_MCU;
0585 
0586     mt7915_irq_disable(dev, mask);
0587 
0588     if (intr & MT_INT_TX_DONE_MCU)
0589         napi_schedule(&dev->mt76.tx_napi);
0590 
0591     if (intr & MT_INT_RX(MT_RXQ_MAIN))
0592         napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
0593 
0594     if (intr & MT_INT_RX(MT_RXQ_BAND1))
0595         napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]);
0596 
0597     if (intr & MT_INT_RX(MT_RXQ_MCU))
0598         napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
0599 
0600     if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
0601         napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
0602 
0603     if (!is_mt7915(&dev->mt76) &&
0604         (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
0605         napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
0606 
0607     if (intr & MT_INT_RX(MT_RXQ_BAND1_WA))
0608         napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1_WA]);
0609 
0610     if (intr & MT_INT_MCU_CMD) {
0611         u32 val = mt76_rr(dev, MT_MCU_CMD);
0612 
0613         mt76_wr(dev, MT_MCU_CMD, val);
0614         if (val & MT_MCU_CMD_ERROR_MASK) {
0615             dev->reset_state = val;
0616             queue_work(dev->mt76.wq, &dev->reset_work);
0617             wake_up(&dev->reset_wait);
0618         }
0619     }
0620 }
0621 
0622 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
0623 {
0624     struct mt7915_dev *dev = dev_instance;
0625     struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
0626 
0627     if (mtk_wed_device_active(wed)) {
0628         mtk_wed_device_irq_set_mask(wed, 0);
0629     } else {
0630         mt76_wr(dev, MT_INT_MASK_CSR, 0);
0631         if (dev->hif2)
0632             mt76_wr(dev, MT_INT1_MASK_CSR, 0);
0633     }
0634 
0635     if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
0636         return IRQ_NONE;
0637 
0638     tasklet_schedule(&dev->irq_tasklet);
0639 
0640     return IRQ_HANDLED;
0641 }
0642 
0643 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
0644                      void __iomem *mem_base, u32 device_id)
0645 {
0646     static const struct mt76_driver_ops drv_ops = {
0647         /* txwi_size = txd size + txp size */
0648         .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp),
0649         .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
0650         .survey_flags = SURVEY_INFO_TIME_TX |
0651                 SURVEY_INFO_TIME_RX |
0652                 SURVEY_INFO_TIME_BSS_RX,
0653         .token_size = MT7915_TOKEN_SIZE,
0654         .tx_prepare_skb = mt7915_tx_prepare_skb,
0655         .tx_complete_skb = mt76_connac_tx_complete_skb,
0656         .rx_skb = mt7915_queue_rx_skb,
0657         .rx_check = mt7915_rx_check,
0658         .rx_poll_complete = mt7915_rx_poll_complete,
0659         .sta_ps = mt7915_sta_ps,
0660         .sta_add = mt7915_mac_sta_add,
0661         .sta_remove = mt7915_mac_sta_remove,
0662         .update_survey = mt7915_update_channel,
0663     };
0664     struct mt7915_dev *dev;
0665     struct mt76_dev *mdev;
0666     int ret;
0667 
0668     mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops);
0669     if (!mdev)
0670         return ERR_PTR(-ENOMEM);
0671 
0672     dev = container_of(mdev, struct mt7915_dev, mt76);
0673 
0674     ret = mt7915_mmio_init(mdev, mem_base, device_id);
0675     if (ret)
0676         goto error;
0677 
0678     tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
0679 
0680     return dev;
0681 
0682 error:
0683     mt76_free_device(&dev->mt76);
0684 
0685     return ERR_PTR(ret);
0686 }
0687 
0688 static int __init mt7915_init(void)
0689 {
0690     int ret;
0691 
0692     ret = pci_register_driver(&mt7915_hif_driver);
0693     if (ret)
0694         return ret;
0695 
0696     ret = pci_register_driver(&mt7915_pci_driver);
0697     if (ret)
0698         goto error_pci;
0699 
0700     if (IS_ENABLED(CONFIG_MT7986_WMAC)) {
0701         ret = platform_driver_register(&mt7986_wmac_driver);
0702         if (ret)
0703             goto error_wmac;
0704     }
0705 
0706     return 0;
0707 
0708 error_wmac:
0709     pci_unregister_driver(&mt7915_pci_driver);
0710 error_pci:
0711     pci_unregister_driver(&mt7915_hif_driver);
0712 
0713     return ret;
0714 }
0715 
0716 static void __exit mt7915_exit(void)
0717 {
0718     if (IS_ENABLED(CONFIG_MT7986_WMAC))
0719         platform_driver_unregister(&mt7986_wmac_driver);
0720 
0721     pci_unregister_driver(&mt7915_pci_driver);
0722     pci_unregister_driver(&mt7915_hif_driver);
0723 }
0724 
0725 module_init(mt7915_init);
0726 module_exit(mt7915_exit);
0727 MODULE_LICENSE("Dual BSD/GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!