mt76/mt7915/mcu.h

0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003
0004 #ifndef __MT7915_MCU_H
0005 #define __MT7915_MCU_H
0006
0007 #include "../mt76_connac_mcu.h"
0008
0009 enum {
0010     MCU_ATE_SET_TRX = 0x1,
0011     MCU_ATE_SET_FREQ_OFFSET = 0xa,
0012     MCU_ATE_SET_SLOT_TIME = 0x13,
0013     MCU_ATE_CLEAN_TXQUEUE = 0x1c,
0014 };
0015
0016 struct mt7915_mcu_thermal_ctrl {
0017     u8 ctrl_id;
0018     u8 band_idx;
0019     union {
0020         struct {
0021             u8 protect_type; /* 1: duty admit, 2: radio off */
0022             u8 trigger_type; /* 0: low, 1: high */
0023         } __packed type;
0024         struct {
0025             u8 duty_level;  /* level 0~3 */
0026             u8 duty_cycle;
0027         } __packed duty;
0028     };
0029 } __packed;
0030
0031 struct mt7915_mcu_thermal_notify {
0032     struct mt76_connac2_mcu_rxd rxd;
0033
0034     struct mt7915_mcu_thermal_ctrl ctrl;
0035     __le32 temperature;
0036     u8 rsv[8];
0037 } __packed;
0038
0039 struct mt7915_mcu_csa_notify {
0040     struct mt76_connac2_mcu_rxd rxd;
0041
0042     u8 omac_idx;
0043     u8 csa_count;
0044     u8 band_idx;
0045     u8 rsv;
0046 } __packed;
0047
0048 struct mt7915_mcu_bcc_notify {
0049     struct mt76_connac2_mcu_rxd rxd;
0050
0051     u8 band_idx;
0052     u8 omac_idx;
0053     u8 cca_count;
0054     u8 rsv;
0055 } __packed;
0056
0057 struct mt7915_mcu_rdd_report {
0058     struct mt76_connac2_mcu_rxd rxd;
0059
0060     u8 band_idx;
0061     u8 long_detected;
0062     u8 constant_prf_detected;
0063     u8 staggered_prf_detected;
0064     u8 radar_type_idx;
0065     u8 periodic_pulse_num;
0066     u8 long_pulse_num;
0067     u8 hw_pulse_num;
0068
0069     u8 out_lpn;
0070     u8 out_spn;
0071     u8 out_crpn;
0072     u8 out_crpw;
0073     u8 out_crbn;
0074     u8 out_stgpn;
0075     u8 out_stgpw;
0076
0077     u8 rsv;
0078
0079     __le32 out_pri_const;
0080     __le32 out_pri_stg[3];
0081
0082     struct {
0083         __le32 start;
0084         __le16 pulse_width;
0085         __le16 pulse_power;
0086         u8 mdrdy_flag;
0087         u8 rsv[3];
0088     } long_pulse[32];
0089
0090     struct {
0091         __le32 start;
0092         __le16 pulse_width;
0093         __le16 pulse_power;
0094         u8 mdrdy_flag;
0095         u8 rsv[3];
0096     } periodic_pulse[32];
0097
0098     struct {
0099         __le32 start;
0100         __le16 pulse_width;
0101         __le16 pulse_power;
0102         u8 sc_pass;
0103         u8 sw_reset;
0104         u8 mdrdy_flag;
0105         u8 tx_active;
0106     } hw_pulse[32];
0107 } __packed;
0108
0109 struct mt7915_mcu_background_chain_ctrl {
0110     u8 chan;        /* primary channel */
0111     u8 central_chan;    /* central channel */
0112     u8 bw;
0113     u8 tx_stream;
0114     u8 rx_stream;
0115
0116     u8 monitor_chan;    /* monitor channel */
0117     u8 monitor_central_chan;/* monitor central channel */
0118     u8 monitor_bw;
0119     u8 monitor_tx_stream;
0120     u8 monitor_rx_stream;
0121
0122     u8 scan_mode;       /* 0: ScanStop
0123                  * 1: ScanStart
0124                  * 2: ScanRunning
0125                  */
0126     u8 band_idx;        /* DBDC */
0127     u8 monitor_scan_type;
0128     u8 band;        /* 0: 2.4GHz, 1: 5GHz */
0129     u8 rsv[2];
0130 } __packed;
0131
0132 struct mt7915_mcu_eeprom {
0133     u8 buffer_mode;
0134     u8 format;
0135     __le16 len;
0136 } __packed;
0137
0138 struct mt7915_mcu_eeprom_info {
0139     __le32 addr;
0140     __le32 valid;
0141     u8 data[16];
0142 } __packed;
0143
0144 struct mt7915_mcu_phy_rx_info {
0145     u8 category;
0146     u8 rate;
0147     u8 mode;
0148     u8 nsts;
0149     u8 gi;
0150     u8 coding;
0151     u8 stbc;
0152     u8 bw;
0153 };
0154
0155 struct mt7915_mcu_mib {
0156     __le32 band;
0157     __le32 offs;
0158     __le64 data;
0159 } __packed;
0160
0161 enum mt7915_chan_mib_offs {
0162     /* mt7915 */
0163     MIB_BUSY_TIME = 14,
0164     MIB_TX_TIME = 81,
0165     MIB_RX_TIME,
0166     MIB_OBSS_AIRTIME = 86,
0167     /* mt7916 */
0168     MIB_BUSY_TIME_V2 = 0,
0169     MIB_TX_TIME_V2 = 6,
0170     MIB_RX_TIME_V2 = 8,
0171     MIB_OBSS_AIRTIME_V2 = 490
0172 };
0173
0174 struct edca {
0175     u8 queue;
0176     u8 set;
0177     u8 aifs;
0178     u8 cw_min;
0179     __le16 cw_max;
0180     __le16 txop;
0181 };
0182
0183 struct mt7915_mcu_tx {
0184     u8 total;
0185     u8 action;
0186     u8 valid;
0187     u8 mode;
0188
0189     struct edca edca[IEEE80211_NUM_ACS];
0190 } __packed;
0191
0192 struct mt7915_mcu_muru_stats {
0193     __le32 event_id;
0194     struct {
0195         __le32 cck_cnt;
0196         __le32 ofdm_cnt;
0197         __le32 htmix_cnt;
0198         __le32 htgf_cnt;
0199         __le32 vht_su_cnt;
0200         __le32 vht_2mu_cnt;
0201         __le32 vht_3mu_cnt;
0202         __le32 vht_4mu_cnt;
0203         __le32 he_su_cnt;
0204         __le32 he_ext_su_cnt;
0205         __le32 he_2ru_cnt;
0206         __le32 he_2mu_cnt;
0207         __le32 he_3ru_cnt;
0208         __le32 he_3mu_cnt;
0209         __le32 he_4ru_cnt;
0210         __le32 he_4mu_cnt;
0211         __le32 he_5to8ru_cnt;
0212         __le32 he_9to16ru_cnt;
0213         __le32 he_gtr16ru_cnt;
0214     } dl;
0215
0216     struct {
0217         __le32 hetrig_su_cnt;
0218         __le32 hetrig_2ru_cnt;
0219         __le32 hetrig_3ru_cnt;
0220         __le32 hetrig_4ru_cnt;
0221         __le32 hetrig_5to8ru_cnt;
0222         __le32 hetrig_9to16ru_cnt;
0223         __le32 hetrig_gtr16ru_cnt;
0224         __le32 hetrig_2mu_cnt;
0225         __le32 hetrig_3mu_cnt;
0226         __le32 hetrig_4mu_cnt;
0227     } ul;
0228 };
0229
0230 #define WMM_AIFS_SET        BIT(0)
0231 #define WMM_CW_MIN_SET      BIT(1)
0232 #define WMM_CW_MAX_SET      BIT(2)
0233 #define WMM_TXOP_SET        BIT(3)
0234 #define WMM_PARAM_SET       GENMASK(3, 0)
0235
0236 enum {
0237     MCU_FW_LOG_WM,
0238     MCU_FW_LOG_WA,
0239     MCU_FW_LOG_TO_HOST,
0240 };
0241
0242 enum {
0243     MCU_TWT_AGRT_ADD,
0244     MCU_TWT_AGRT_MODIFY,
0245     MCU_TWT_AGRT_DELETE,
0246     MCU_TWT_AGRT_TEARDOWN,
0247     MCU_TWT_AGRT_GET_TSF,
0248 };
0249
0250 enum {
0251     MCU_WA_PARAM_CMD_QUERY,
0252     MCU_WA_PARAM_CMD_SET,
0253     MCU_WA_PARAM_CMD_CAPABILITY,
0254     MCU_WA_PARAM_CMD_DEBUG,
0255 };
0256
0257 enum {
0258     MCU_WA_PARAM_PDMA_RX = 0x04,
0259     MCU_WA_PARAM_CPU_UTIL = 0x0b,
0260     MCU_WA_PARAM_RED = 0x0e,
0261 };
0262
0263 enum mcu_mmps_mode {
0264     MCU_MMPS_STATIC,
0265     MCU_MMPS_DYNAMIC,
0266     MCU_MMPS_RSV,
0267     MCU_MMPS_DISABLE,
0268 };
0269
0270 struct bss_info_bmc_rate {
0271     __le16 tag;
0272     __le16 len;
0273     __le16 bc_trans;
0274     __le16 mc_trans;
0275     u8 short_preamble;
0276     u8 rsv[7];
0277 } __packed;
0278
0279 struct bss_info_ra {
0280     __le16 tag;
0281     __le16 len;
0282     u8 op_mode;
0283     u8 adhoc_en;
0284     u8 short_preamble;
0285     u8 tx_streams;
0286     u8 rx_streams;
0287     u8 algo;
0288     u8 force_sgi;
0289     u8 force_gf;
0290     u8 ht_mode;
0291     u8 has_20_sta;      /* Check if any sta support GF. */
0292     u8 bss_width_trigger_events;
0293     u8 vht_nss_cap;
0294     u8 vht_bw_signal;   /* not use */
0295     u8 vht_force_sgi;   /* not use */
0296     u8 se_off;
0297     u8 antenna_idx;
0298     u8 train_up_rule;
0299     u8 rsv[3];
0300     unsigned short train_up_high_thres;
0301     short train_up_rule_rssi;
0302     unsigned short low_traffic_thres;
0303     __le16 max_phyrate;
0304     __le32 phy_cap;
0305     __le32 interval;
0306     __le32 fast_interval;
0307 } __packed;
0308
0309 struct bss_info_hw_amsdu {
0310     __le16 tag;
0311     __le16 len;
0312     __le32 cmp_bitmap_0;
0313     __le32 cmp_bitmap_1;
0314     __le16 trig_thres;
0315     u8 enable;
0316     u8 rsv;
0317 } __packed;
0318
0319 struct bss_info_color {
0320     __le16 tag;
0321     __le16 len;
0322     u8 disable;
0323     u8 color;
0324     u8 rsv[2];
0325 } __packed;
0326
0327 struct bss_info_he {
0328     __le16 tag;
0329     __le16 len;
0330     u8 he_pe_duration;
0331     u8 vht_op_info_present;
0332     __le16 he_rts_thres;
0333     __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
0334     u8 rsv[6];
0335 } __packed;
0336
0337 struct bss_info_bcn {
0338     __le16 tag;
0339     __le16 len;
0340     u8 ver;
0341     u8 enable;
0342     __le16 sub_ntlv;
0343 } __packed __aligned(4);
0344
0345 struct bss_info_bcn_cntdwn {
0346     __le16 tag;
0347     __le16 len;
0348     u8 cnt;
0349     u8 rsv[3];
0350 } __packed __aligned(4);
0351
0352 struct bss_info_bcn_mbss {
0353 #define MAX_BEACON_NUM  32
0354     __le16 tag;
0355     __le16 len;
0356     __le32 bitmap;
0357     __le16 offset[MAX_BEACON_NUM];
0358     u8 rsv[8];
0359 } __packed __aligned(4);
0360
0361 struct bss_info_bcn_cont {
0362     __le16 tag;
0363     __le16 len;
0364     __le16 tim_ofs;
0365     __le16 csa_ofs;
0366     __le16 bcc_ofs;
0367     __le16 pkt_len;
0368 } __packed __aligned(4);
0369
0370 struct bss_info_inband_discovery {
0371     __le16 tag;
0372     __le16 len;
0373     u8 tx_type;
0374     u8 tx_mode;
0375     u8 tx_interval;
0376     u8 enable;
0377     __le16 rsv;
0378     __le16 prob_rsp_len;
0379 } __packed __aligned(4);
0380
0381 enum {
0382     BSS_INFO_BCN_CSA,
0383     BSS_INFO_BCN_BCC,
0384     BSS_INFO_BCN_MBSSID,
0385     BSS_INFO_BCN_CONTENT,
0386     BSS_INFO_BCN_DISCOV,
0387     BSS_INFO_BCN_MAX
0388 };
0389
0390 enum {
0391     RATE_PARAM_FIXED = 3,
0392     RATE_PARAM_MMPS_UPDATE = 5,
0393     RATE_PARAM_FIXED_HE_LTF = 7,
0394     RATE_PARAM_FIXED_MCS,
0395     RATE_PARAM_FIXED_GI = 11,
0396     RATE_PARAM_AUTO = 20,
0397 };
0398
0399 #define RATE_CFG_MCS            GENMASK(3, 0)
0400 #define RATE_CFG_NSS            GENMASK(7, 4)
0401 #define RATE_CFG_GI         GENMASK(11, 8)
0402 #define RATE_CFG_BW         GENMASK(15, 12)
0403 #define RATE_CFG_STBC           GENMASK(19, 16)
0404 #define RATE_CFG_LDPC           GENMASK(23, 20)
0405 #define RATE_CFG_PHY_TYPE       GENMASK(27, 24)
0406 #define RATE_CFG_HE_LTF         GENMASK(31, 28)
0407
0408 enum {
0409     THERMAL_PROTECT_PARAMETER_CTRL,
0410     THERMAL_PROTECT_BASIC_INFO,
0411     THERMAL_PROTECT_ENABLE,
0412     THERMAL_PROTECT_DISABLE,
0413     THERMAL_PROTECT_DUTY_CONFIG,
0414     THERMAL_PROTECT_MECH_INFO,
0415     THERMAL_PROTECT_DUTY_INFO,
0416     THERMAL_PROTECT_STATE_ACT,
0417 };
0418
0419 enum {
0420     MT_BF_SOUNDING_ON = 1,
0421     MT_BF_TYPE_UPDATE = 20,
0422     MT_BF_MODULE_UPDATE = 25
0423 };
0424
0425 enum {
0426     MURU_SET_ARB_OP_MODE = 14,
0427     MURU_SET_PLATFORM_TYPE = 25,
0428 };
0429
0430 enum {
0431     MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1,
0432     MURU_PLATFORM_TYPE_PERF_LEVEL_2,
0433 };
0434
0435 /* tx cmd tx statistics */
0436 enum {
0437     MURU_SET_TXC_TX_STATS_EN = 150,
0438     MURU_GET_TXC_TX_STATS = 151,
0439 };
0440
0441 enum {
0442     SER_QUERY,
0443     /* recovery */
0444     SER_SET_RECOVER_L1,
0445     SER_SET_RECOVER_L2,
0446     SER_SET_RECOVER_L3_RX_ABORT,
0447     SER_SET_RECOVER_L3_TX_ABORT,
0448     SER_SET_RECOVER_L3_TX_DISABLE,
0449     SER_SET_RECOVER_L3_BF,
0450     /* action */
0451     SER_ENABLE = 2,
0452     SER_RECOVER
0453 };
0454
0455 #define MT7915_MAX_BEACON_SIZE      512
0456 #define MT7915_MAX_INBAND_FRAME_SIZE    256
0457 #define MT7915_MAX_BSS_OFFLOAD_SIZE (MT7915_MAX_BEACON_SIZE +     \
0458                      MT7915_MAX_INBAND_FRAME_SIZE +   \
0459                      MT7915_BEACON_UPDATE_SIZE)
0460
0461 #define MT7915_BSS_UPDATE_MAX_SIZE  (sizeof(struct sta_req_hdr) +   \
0462                      sizeof(struct bss_info_omac) + \
0463                      sizeof(struct bss_info_basic) +\
0464                      sizeof(struct bss_info_rf_ch) +\
0465                      sizeof(struct bss_info_ra) +   \
0466                      sizeof(struct bss_info_hw_amsdu) +\
0467                      sizeof(struct bss_info_he) +   \
0468                      sizeof(struct bss_info_bmc_rate) +\
0469                      sizeof(struct bss_info_ext_bss))
0470
0471 #define MT7915_BEACON_UPDATE_SIZE   (sizeof(struct sta_req_hdr) +   \
0472                      sizeof(struct bss_info_bcn_cntdwn) + \
0473                      sizeof(struct bss_info_bcn_mbss) + \
0474                      sizeof(struct bss_info_bcn_cont) + \
0475                      sizeof(struct bss_info_inband_discovery))
0476
0477 #endif