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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #include "mt7915.h"
0005 #include "../dma.h"
0006 #include "mac.h"
0007 
0008 static int
0009 mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base)
0010 {
0011     struct mt7915_dev *dev = phy->dev;
0012 
0013     if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) {
0014         ring_base = MT_WED_TX_RING_BASE;
0015         idx -= MT_TXQ_ID(0);
0016     }
0017 
0018     return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base,
0019                       MT_WED_Q_TX(idx));
0020 }
0021 
0022 static int mt7915_poll_tx(struct napi_struct *napi, int budget)
0023 {
0024     struct mt7915_dev *dev;
0025 
0026     dev = container_of(napi, struct mt7915_dev, mt76.tx_napi);
0027 
0028     mt76_connac_tx_cleanup(&dev->mt76);
0029     if (napi_complete_done(napi, 0))
0030         mt7915_irq_enable(dev, MT_INT_TX_DONE_MCU);
0031 
0032     return 0;
0033 }
0034 
0035 static void mt7915_dma_config(struct mt7915_dev *dev)
0036 {
0037 #define Q_CONFIG(q, wfdma, int, id) do {        \
0038         if (wfdma)              \
0039             dev->wfdma_mask |= (1 << (q));  \
0040         dev->q_int_mask[(q)] = int;     \
0041         dev->q_id[(q)] = id;            \
0042     } while (0)
0043 
0044 #define MCUQ_CONFIG(q, wfdma, int, id)  Q_CONFIG(q, (wfdma), (int), (id))
0045 #define RXQ_CONFIG(q, wfdma, int, id)   Q_CONFIG(__RXQ(q), (wfdma), (int), (id))
0046 #define TXQ_CONFIG(q, wfdma, int, id)   Q_CONFIG(__TXQ(q), (wfdma), (int), (id))
0047 
0048     if (is_mt7915(&dev->mt76)) {
0049         RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7915_RXQ_BAND0);
0050         RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, MT7915_RXQ_MCU_WM);
0051         RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, MT7915_RXQ_MCU_WA);
0052         RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7915_RXQ_BAND1);
0053         RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, MT7915_RXQ_MCU_WA_EXT);
0054         RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, MT7915_RXQ_MCU_WA);
0055         TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
0056         TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
0057         MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
0058         MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA);
0059         MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
0060     } else {
0061         RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0);
0062         RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM);
0063         RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA);
0064         RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1);
0065         RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT);
0066         RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN);
0067         TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0);
0068         TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1);
0069         MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM);
0070         MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA);
0071         MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL);
0072     }
0073 }
0074 
0075 static void __mt7915_dma_prefetch(struct mt7915_dev *dev, u32 ofs)
0076 {
0077 #define PREFETCH(_base, _depth) ((_base) << 16 | (_depth))
0078     u32 base = 0;
0079 
0080     /* prefetch SRAM wrapping boundary for tx/rx ring. */
0081     mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x4));
0082     mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x40, 0x4));
0083     mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x80, 0x4));
0084     mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0xc0, 0x4));
0085     mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x100, 0x4));
0086 
0087     mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs,
0088         PREFETCH(0x140, 0x4));
0089     mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs,
0090         PREFETCH(0x180, 0x4));
0091     if (!is_mt7915(&dev->mt76)) {
0092         mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs,
0093             PREFETCH(0x1c0, 0x4));
0094         base = 0x40;
0095     }
0096     mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs,
0097         PREFETCH(0x1c0 + base, 0x4));
0098     mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs,
0099         PREFETCH(0x200 + base, 0x4));
0100     mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs,
0101         PREFETCH(0x240 + base, 0x4));
0102 
0103     /* for mt7915, the ring which is next the last
0104      * used ring must be initialized.
0105      */
0106     if (is_mt7915(&dev->mt76)) {
0107         ofs += 0x4;
0108         mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs,
0109             PREFETCH(0x140, 0x0));
0110         mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1_WA) + ofs,
0111             PREFETCH(0x200 + base, 0x0));
0112         mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND1) + ofs,
0113             PREFETCH(0x280 + base, 0x0));
0114     }
0115 }
0116 
0117 void mt7915_dma_prefetch(struct mt7915_dev *dev)
0118 {
0119     __mt7915_dma_prefetch(dev, 0);
0120     if (dev->hif2)
0121         __mt7915_dma_prefetch(dev, MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0));
0122 }
0123 
0124 static void mt7915_dma_disable(struct mt7915_dev *dev, bool rst)
0125 {
0126     struct mt76_dev *mdev = &dev->mt76;
0127     u32 hif1_ofs = 0;
0128 
0129     if (dev->hif2)
0130         hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
0131 
0132     /* reset */
0133     if (rst) {
0134         mt76_clear(dev, MT_WFDMA0_RST,
0135                MT_WFDMA0_RST_DMASHDL_ALL_RST |
0136                MT_WFDMA0_RST_LOGIC_RST);
0137 
0138         mt76_set(dev, MT_WFDMA0_RST,
0139              MT_WFDMA0_RST_DMASHDL_ALL_RST |
0140              MT_WFDMA0_RST_LOGIC_RST);
0141 
0142         if (is_mt7915(mdev)) {
0143             mt76_clear(dev, MT_WFDMA1_RST,
0144                    MT_WFDMA1_RST_DMASHDL_ALL_RST |
0145                    MT_WFDMA1_RST_LOGIC_RST);
0146 
0147             mt76_set(dev, MT_WFDMA1_RST,
0148                  MT_WFDMA1_RST_DMASHDL_ALL_RST |
0149                  MT_WFDMA1_RST_LOGIC_RST);
0150         }
0151 
0152         if (dev->hif2) {
0153             mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,
0154                    MT_WFDMA0_RST_DMASHDL_ALL_RST |
0155                    MT_WFDMA0_RST_LOGIC_RST);
0156 
0157             mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,
0158                  MT_WFDMA0_RST_DMASHDL_ALL_RST |
0159                  MT_WFDMA0_RST_LOGIC_RST);
0160 
0161             if (is_mt7915(mdev)) {
0162                 mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs,
0163                        MT_WFDMA1_RST_DMASHDL_ALL_RST |
0164                        MT_WFDMA1_RST_LOGIC_RST);
0165 
0166                 mt76_set(dev, MT_WFDMA1_RST + hif1_ofs,
0167                      MT_WFDMA1_RST_DMASHDL_ALL_RST |
0168                      MT_WFDMA1_RST_LOGIC_RST);
0169             }
0170         }
0171     }
0172 
0173     /* disable */
0174     mt76_clear(dev, MT_WFDMA0_GLO_CFG,
0175            MT_WFDMA0_GLO_CFG_TX_DMA_EN |
0176            MT_WFDMA0_GLO_CFG_RX_DMA_EN |
0177            MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
0178            MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
0179            MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
0180 
0181     if (is_mt7915(mdev))
0182         mt76_clear(dev, MT_WFDMA1_GLO_CFG,
0183                MT_WFDMA1_GLO_CFG_TX_DMA_EN |
0184                MT_WFDMA1_GLO_CFG_RX_DMA_EN |
0185                MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
0186                MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
0187                MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
0188 
0189     if (dev->hif2) {
0190         mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
0191                MT_WFDMA0_GLO_CFG_TX_DMA_EN |
0192                MT_WFDMA0_GLO_CFG_RX_DMA_EN |
0193                MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
0194                MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
0195                MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
0196 
0197         if (is_mt7915(mdev))
0198             mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
0199                    MT_WFDMA1_GLO_CFG_TX_DMA_EN |
0200                    MT_WFDMA1_GLO_CFG_RX_DMA_EN |
0201                    MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
0202                    MT_WFDMA1_GLO_CFG_OMIT_RX_INFO |
0203                    MT_WFDMA1_GLO_CFG_OMIT_RX_INFO_PFET2);
0204     }
0205 }
0206 
0207 static int mt7915_dma_enable(struct mt7915_dev *dev)
0208 {
0209     struct mt76_dev *mdev = &dev->mt76;
0210     u32 hif1_ofs = 0;
0211     u32 irq_mask;
0212 
0213     if (dev->hif2)
0214         hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
0215 
0216     /* reset dma idx */
0217     mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
0218     if (is_mt7915(mdev))
0219         mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR, ~0);
0220     if (dev->hif2) {
0221         mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);
0222         if (is_mt7915(mdev))
0223             mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0);
0224     }
0225 
0226     /* configure delay interrupt off */
0227     mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
0228     if (is_mt7915(mdev)) {
0229         mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0, 0);
0230     } else {
0231         mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1, 0);
0232         mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2, 0);
0233     }
0234 
0235     if (dev->hif2) {
0236         mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);
0237         if (is_mt7915(mdev)) {
0238             mt76_wr(dev, MT_WFDMA1_PRI_DLY_INT_CFG0 +
0239                 hif1_ofs, 0);
0240         } else {
0241             mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 +
0242                 hif1_ofs, 0);
0243             mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 +
0244                 hif1_ofs, 0);
0245         }
0246     }
0247 
0248     /* configure perfetch settings */
0249     mt7915_dma_prefetch(dev);
0250 
0251     /* hif wait WFDMA idle */
0252     mt76_set(dev, MT_WFDMA0_BUSY_ENA,
0253          MT_WFDMA0_BUSY_ENA_TX_FIFO0 |
0254          MT_WFDMA0_BUSY_ENA_TX_FIFO1 |
0255          MT_WFDMA0_BUSY_ENA_RX_FIFO);
0256 
0257     if (is_mt7915(mdev))
0258         mt76_set(dev, MT_WFDMA1_BUSY_ENA,
0259              MT_WFDMA1_BUSY_ENA_TX_FIFO0 |
0260              MT_WFDMA1_BUSY_ENA_TX_FIFO1 |
0261              MT_WFDMA1_BUSY_ENA_RX_FIFO);
0262 
0263     if (dev->hif2) {
0264         mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,
0265              MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 |
0266              MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 |
0267              MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO);
0268 
0269         if (is_mt7915(mdev))
0270             mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs,
0271                  MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 |
0272                  MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 |
0273                  MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO);
0274     }
0275 
0276     mt76_poll(dev, MT_WFDMA_EXT_CSR_HIF_MISC,
0277           MT_WFDMA_EXT_CSR_HIF_MISC_BUSY, 0, 1000);
0278 
0279     /* set WFDMA Tx/Rx */
0280     mt76_set(dev, MT_WFDMA0_GLO_CFG,
0281          MT_WFDMA0_GLO_CFG_TX_DMA_EN |
0282          MT_WFDMA0_GLO_CFG_RX_DMA_EN |
0283          MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
0284          MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
0285 
0286     if (is_mt7915(mdev))
0287         mt76_set(dev, MT_WFDMA1_GLO_CFG,
0288              MT_WFDMA1_GLO_CFG_TX_DMA_EN |
0289              MT_WFDMA1_GLO_CFG_RX_DMA_EN |
0290              MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
0291              MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
0292 
0293     if (dev->hif2) {
0294         mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
0295              MT_WFDMA0_GLO_CFG_TX_DMA_EN |
0296              MT_WFDMA0_GLO_CFG_RX_DMA_EN |
0297              MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
0298              MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
0299 
0300         if (is_mt7915(mdev))
0301             mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
0302                  MT_WFDMA1_GLO_CFG_TX_DMA_EN |
0303                  MT_WFDMA1_GLO_CFG_RX_DMA_EN |
0304                  MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
0305                  MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
0306 
0307         mt76_set(dev, MT_WFDMA_HOST_CONFIG,
0308              MT_WFDMA_HOST_CONFIG_PDMA_BAND);
0309     }
0310 
0311     /* enable interrupts for TX/RX rings */
0312     irq_mask = MT_INT_RX_DONE_MCU |
0313            MT_INT_TX_DONE_MCU |
0314            MT_INT_MCU_CMD;
0315 
0316     if (!dev->phy.band_idx)
0317         irq_mask |= MT_INT_BAND0_RX_DONE;
0318 
0319     if (dev->dbdc_support || dev->phy.band_idx)
0320         irq_mask |= MT_INT_BAND1_RX_DONE;
0321 
0322     if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
0323         u32 wed_irq_mask = irq_mask;
0324 
0325         wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
0326         mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
0327         mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
0328     }
0329 
0330     mt7915_irq_enable(dev, irq_mask);
0331 
0332     return 0;
0333 }
0334 
0335 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2)
0336 {
0337     struct mt76_dev *mdev = &dev->mt76;
0338     u32 wa_rx_base, wa_rx_idx;
0339     u32 hif1_ofs = 0;
0340     int ret;
0341 
0342     mt7915_dma_config(dev);
0343 
0344     mt76_dma_attach(&dev->mt76);
0345 
0346     if (dev->hif2)
0347         hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
0348 
0349     mt7915_dma_disable(dev, true);
0350 
0351     if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
0352         mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
0353 
0354         mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL,
0355             FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) |
0356             FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) |
0357             FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, 1));
0358     } else {
0359         mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED);
0360     }
0361 
0362     /* init tx queue */
0363     ret = mt7915_init_tx_queues(&dev->phy,
0364                     MT_TXQ_ID(dev->phy.band_idx),
0365                     MT7915_TX_RING_SIZE,
0366                     MT_TXQ_RING_BASE(0));
0367     if (ret)
0368         return ret;
0369 
0370     if (phy2) {
0371         ret = mt7915_init_tx_queues(phy2,
0372                         MT_TXQ_ID(phy2->band_idx),
0373                         MT7915_TX_RING_SIZE,
0374                         MT_TXQ_RING_BASE(1));
0375         if (ret)
0376             return ret;
0377     }
0378 
0379     /* command to WM */
0380     ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM,
0381                   MT_MCUQ_ID(MT_MCUQ_WM),
0382                   MT7915_TX_MCU_RING_SIZE,
0383                   MT_MCUQ_RING_BASE(MT_MCUQ_WM));
0384     if (ret)
0385         return ret;
0386 
0387     /* command to WA */
0388     ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WA,
0389                   MT_MCUQ_ID(MT_MCUQ_WA),
0390                   MT7915_TX_MCU_RING_SIZE,
0391                   MT_MCUQ_RING_BASE(MT_MCUQ_WA));
0392     if (ret)
0393         return ret;
0394 
0395     /* firmware download */
0396     ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL,
0397                   MT_MCUQ_ID(MT_MCUQ_FWDL),
0398                   MT7915_TX_FWDL_RING_SIZE,
0399                   MT_MCUQ_RING_BASE(MT_MCUQ_FWDL));
0400     if (ret)
0401         return ret;
0402 
0403     /* event from WM */
0404     ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
0405                    MT_RXQ_ID(MT_RXQ_MCU),
0406                    MT7915_RX_MCU_RING_SIZE,
0407                    MT_RX_BUF_SIZE,
0408                    MT_RXQ_RING_BASE(MT_RXQ_MCU));
0409     if (ret)
0410         return ret;
0411 
0412     /* event from WA */
0413     if (mtk_wed_device_active(&dev->mt76.mmio.wed)) {
0414         wa_rx_base = MT_WED_RX_RING_BASE;
0415         wa_rx_idx = MT7915_RXQ_MCU_WA;
0416         dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE;
0417     } else {
0418         wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA);
0419         wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA);
0420     }
0421     ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
0422                    wa_rx_idx, MT7915_RX_MCU_RING_SIZE,
0423                    MT_RX_BUF_SIZE, wa_rx_base);
0424     if (ret)
0425         return ret;
0426 
0427     /* rx data queue for band0 */
0428     if (!dev->phy.band_idx) {
0429         ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
0430                        MT_RXQ_ID(MT_RXQ_MAIN),
0431                        MT7915_RX_RING_SIZE,
0432                        MT_RX_BUF_SIZE,
0433                        MT_RXQ_RING_BASE(MT_RXQ_MAIN));
0434         if (ret)
0435             return ret;
0436     }
0437 
0438     /* tx free notify event from WA for band0 */
0439     if (!is_mt7915(mdev)) {
0440         ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],
0441                        MT_RXQ_ID(MT_RXQ_MAIN_WA),
0442                        MT7915_RX_MCU_RING_SIZE,
0443                        MT_RX_BUF_SIZE,
0444                        MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA));
0445         if (ret)
0446             return ret;
0447     }
0448 
0449     if (dev->dbdc_support || dev->phy.band_idx) {
0450         /* rx data queue for band1 */
0451         ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],
0452                        MT_RXQ_ID(MT_RXQ_BAND1),
0453                        MT7915_RX_RING_SIZE,
0454                        MT_RX_BUF_SIZE,
0455                        MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs);
0456         if (ret)
0457             return ret;
0458 
0459         /* tx free notify event from WA for band1 */
0460         ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],
0461                        MT_RXQ_ID(MT_RXQ_BAND1_WA),
0462                        MT7915_RX_MCU_RING_SIZE,
0463                        MT_RX_BUF_SIZE,
0464                        MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs);
0465         if (ret)
0466             return ret;
0467     }
0468 
0469     ret = mt76_init_queues(dev, mt76_dma_rx_poll);
0470     if (ret < 0)
0471         return ret;
0472 
0473     netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
0474               mt7915_poll_tx);
0475     napi_enable(&dev->mt76.tx_napi);
0476 
0477     mt7915_dma_enable(dev);
0478 
0479     return 0;
0480 }
0481 
0482 void mt7915_dma_cleanup(struct mt7915_dev *dev)
0483 {
0484     mt7915_dma_disable(dev, true);
0485 
0486     mt76_dma_cleanup(&dev->mt76);
0487 }
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