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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005 
0006 #include "mt76x2u.h"
0007 #include "eeprom.h"
0008 #include "../mt76x02_phy.h"
0009 
0010 static void
0011 mt76x2u_phy_channel_calibrate(struct mt76x02_dev *dev, bool mac_stopped)
0012 {
0013     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0014     bool is_5ghz = chan->band == NL80211_BAND_5GHZ;
0015 
0016     if (dev->cal.channel_cal_done)
0017         return;
0018 
0019     if (mt76x2_channel_silent(dev))
0020         return;
0021 
0022     if (!mac_stopped)
0023         mt76x2u_mac_stop(dev);
0024 
0025     if (is_5ghz)
0026         mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 0);
0027 
0028     mt76x02_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz);
0029     mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz);
0030     mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz);
0031     mt76x02_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0);
0032     mt76x02_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0);
0033 
0034     if (!mac_stopped)
0035         mt76x2_mac_resume(dev);
0036     mt76x2_apply_gain_adj(dev);
0037     mt76x02_edcca_init(dev);
0038 
0039     dev->cal.channel_cal_done = true;
0040 }
0041 
0042 void mt76x2u_phy_calibrate(struct work_struct *work)
0043 {
0044     struct mt76x02_dev *dev;
0045 
0046     dev = container_of(work, struct mt76x02_dev, cal_work.work);
0047 
0048     mutex_lock(&dev->mt76.mutex);
0049 
0050     mt76x2u_phy_channel_calibrate(dev, false);
0051     mt76x2_phy_tssi_compensate(dev);
0052     mt76x2_phy_update_channel_gain(dev);
0053 
0054     mutex_unlock(&dev->mt76.mutex);
0055 
0056     ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
0057                      MT_CALIBRATE_INTERVAL);
0058 }
0059 
0060 int mt76x2u_phy_set_channel(struct mt76x02_dev *dev,
0061                 struct cfg80211_chan_def *chandef)
0062 {
0063     u32 ext_cca_chan[4] = {
0064         [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) |
0065               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) |
0066               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
0067               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
0068               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
0069         [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) |
0070               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) |
0071               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
0072               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
0073               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
0074         [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) |
0075               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) |
0076               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
0077               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
0078               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
0079         [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) |
0080               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) |
0081               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
0082               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
0083               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
0084     };
0085     bool scan = test_bit(MT76_SCANNING, &dev->mphy.state);
0086     struct ieee80211_channel *chan = chandef->chan;
0087     u8 channel = chan->hw_value, bw, bw_index;
0088     int ch_group_index, freq, freq1, ret;
0089 
0090     dev->cal.channel_cal_done = false;
0091     freq = chandef->chan->center_freq;
0092     freq1 = chandef->center_freq1;
0093 
0094     switch (chandef->width) {
0095     case NL80211_CHAN_WIDTH_40:
0096         bw = 1;
0097         if (freq1 > freq) {
0098             bw_index = 1;
0099             ch_group_index = 0;
0100         } else {
0101             bw_index = 3;
0102             ch_group_index = 1;
0103         }
0104         channel += 2 - ch_group_index * 4;
0105         break;
0106     case NL80211_CHAN_WIDTH_80:
0107         ch_group_index = (freq - freq1 + 30) / 20;
0108         if (WARN_ON(ch_group_index < 0 || ch_group_index > 3))
0109             ch_group_index = 0;
0110         bw = 2;
0111         bw_index = ch_group_index;
0112         channel += 6 - ch_group_index * 4;
0113         break;
0114     default:
0115         bw = 0;
0116         bw_index = 0;
0117         ch_group_index = 0;
0118         break;
0119     }
0120 
0121     mt76x2_read_rx_gain(dev);
0122     mt76x2_phy_set_txpower_regs(dev, chan->band);
0123     mt76x2_configure_tx_delay(dev, chan->band, bw);
0124     mt76x2_phy_set_txpower(dev);
0125 
0126     mt76x02_phy_set_band(dev, chan->band, ch_group_index & 1);
0127     mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
0128 
0129     mt76_rmw(dev, MT_EXT_CCA_CFG,
0130          (MT_EXT_CCA_CFG_CCA0 |
0131           MT_EXT_CCA_CFG_CCA1 |
0132           MT_EXT_CCA_CFG_CCA2 |
0133           MT_EXT_CCA_CFG_CCA3 |
0134           MT_EXT_CCA_CFG_CCA_MASK),
0135          ext_cca_chan[ch_group_index]);
0136 
0137     ret = mt76x2_mcu_set_channel(dev, channel, bw, bw_index, scan);
0138     if (ret)
0139         return ret;
0140 
0141     mt76x2_mcu_init_gain(dev, channel, dev->cal.rx.mcu_gain, true);
0142 
0143     /* Enable LDPC Rx */
0144     if (mt76xx_rev(dev) >= MT76XX_REV_E3)
0145         mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
0146 
0147     if (!dev->cal.init_cal_done) {
0148         u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
0149 
0150         if (val != 0xff)
0151             mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0);
0152     }
0153 
0154     mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel);
0155 
0156     /* Rx LPF calibration */
0157     if (!dev->cal.init_cal_done)
0158         mt76x02_mcu_calibrate(dev, MCU_CAL_RC, 0);
0159     dev->cal.init_cal_done = true;
0160 
0161     mt76_wr(dev, MT_BBP(AGC, 61), 0xff64a4e2);
0162     mt76_wr(dev, MT_BBP(AGC, 7), 0x08081010);
0163     mt76_wr(dev, MT_BBP(AGC, 11), 0x00000404);
0164     mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
0165     mt76_wr(dev, MT_TXOP_CTRL_CFG, 0X04101b3f);
0166 
0167     mt76_set(dev, MT_BBP(TXO, 4), BIT(25));
0168     mt76_set(dev, MT_BBP(RXO, 13), BIT(8));
0169 
0170     if (scan)
0171         return 0;
0172 
0173     mt76x2u_phy_channel_calibrate(dev, true);
0174     mt76x02_init_agc_gain(dev);
0175 
0176     if (mt76x2_tssi_enabled(dev)) {
0177         /* init default values for temp compensation */
0178         mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
0179                    0x38);
0180         mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
0181                    0x38);
0182 
0183         /* init tssi calibration */
0184         if (!mt76x2_channel_silent(dev)) {
0185             struct ieee80211_channel *chan;
0186             u32 flag = 0;
0187 
0188             chan = dev->mphy.chandef.chan;
0189             if (chan->band == NL80211_BAND_5GHZ)
0190                 flag |= BIT(0);
0191             if (mt76x02_ext_pa_enabled(dev, chan->band))
0192                 flag |= BIT(8);
0193             mt76x02_mcu_calibrate(dev, MCU_CAL_TSSI, flag);
0194             dev->cal.tssi_cal_done = true;
0195         }
0196     }
0197 
0198     ieee80211_queue_delayed_work(mt76_hw(dev), &dev->cal_work,
0199                      MT_CALIBRATE_INTERVAL);
0200     return 0;
0201 }
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