mt76/mt76x2/usb_mac.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005
0006 #include "mt76x2u.h"
0007 #include "eeprom.h"
0008
0009 static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev)
0010 {
0011     s8 offset = 0;
0012     u16 eep_val;
0013
0014     eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
0015
0016     offset = eep_val & 0x7f;
0017     if ((eep_val & 0xff) == 0xff)
0018         offset = 0;
0019     else if (eep_val & 0x80)
0020         offset = 0 - offset;
0021
0022     eep_val >>= 8;
0023     if (eep_val == 0x00 || eep_val == 0xff) {
0024         eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
0025         eep_val &= 0xff;
0026
0027         if (eep_val == 0x00 || eep_val == 0xff)
0028             eep_val = 0x14;
0029     }
0030
0031     eep_val &= 0x7f;
0032     mt76_rmw_field(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL5),
0033                MT_XO_CTRL5_C2_VAL, eep_val + offset);
0034     mt76_set(dev, MT_VEND_ADDR(CFG, MT_XO_CTRL6), MT_XO_CTRL6_C2_CTRL);
0035
0036     mt76_wr(dev, 0x504, 0x06000000);
0037     mt76_wr(dev, 0x50c, 0x08800000);
0038     mdelay(5);
0039     mt76_wr(dev, 0x504, 0x0);
0040
0041     /* decrease SIFS from 16us to 13us */
0042     mt76_rmw_field(dev, MT_XIFS_TIME_CFG,
0043                MT_XIFS_TIME_CFG_OFDM_SIFS, 0xd);
0044     mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, MT_BKOFF_SLOT_CFG_CC_DELAY, 1);
0045
0046     /* init fce */
0047     mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
0048
0049     eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
0050     switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
0051     case 0:
0052         mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
0053         break;
0054     case 1:
0055         mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
0056         break;
0057     default:
0058         break;
0059     }
0060 }
0061
0062 int mt76x2u_mac_reset(struct mt76x02_dev *dev)
0063 {
0064     mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5));
0065
0066     /* init pbf regs */
0067     mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
0068     mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
0069
0070     mt76_write_mac_initvals(dev);
0071
0072     mt76_wr(dev, MT_TX_LINK_CFG, 0x1020);
0073     mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13);
0074     mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00);
0075
0076     mt76_wr(dev, MT_WMM_AIFSN, 0x2273);
0077     mt76_wr(dev, MT_WMM_CWMIN, 0x2344);
0078     mt76_wr(dev, MT_WMM_CWMAX, 0x34aa);
0079
0080     mt76_clear(dev, MT_MAC_SYS_CTRL,
0081            MT_MAC_SYS_CTRL_RESET_CSR |
0082            MT_MAC_SYS_CTRL_RESET_BBP);
0083
0084     if (is_mt7612(dev))
0085         mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
0086
0087     mt76_set(dev, MT_EXT_CCA_CFG, 0xf000);
0088     mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
0089
0090     mt76x2u_mac_fixup_xtal(dev);
0091
0092     return 0;
0093 }
0094
0095 int mt76x2u_mac_stop(struct mt76x02_dev *dev)
0096 {
0097     int i, count = 0, val;
0098     bool stopped = false;
0099     u32 rts_cfg;
0100
0101     if (test_bit(MT76_REMOVED, &dev->mphy.state))
0102         return -EIO;
0103
0104     rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
0105     mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
0106
0107     mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
0108     mt76_clear(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN);
0109
0110     /* wait tx dma to stop */
0111     for (i = 0; i < 2000; i++) {
0112         val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
0113         if (!(val & MT_USB_DMA_CFG_TX_BUSY) && i > 10)
0114             break;
0115         usleep_range(50, 100);
0116     }
0117
0118     /* page count on TxQ */
0119     for (i = 0; i < 200; i++) {
0120         if (!(mt76_rr(dev, 0x0438) & 0xffffffff) &&
0121             !(mt76_rr(dev, 0x0a30) & 0x000000ff) &&
0122             !(mt76_rr(dev, 0x0a34) & 0xff00ff00))
0123             break;
0124         usleep_range(10, 20);
0125     }
0126
0127     /* disable tx-rx */
0128     mt76_clear(dev, MT_MAC_SYS_CTRL,
0129            MT_MAC_SYS_CTRL_ENABLE_RX |
0130            MT_MAC_SYS_CTRL_ENABLE_TX);
0131
0132     /* Wait for MAC to become idle */
0133     for (i = 0; i < 1000; i++) {
0134         if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) &&
0135             !mt76_rr(dev, MT_BBP(IBI, 12))) {
0136             stopped = true;
0137             break;
0138         }
0139         usleep_range(10, 20);
0140     }
0141
0142     if (!stopped) {
0143         mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
0144         mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
0145
0146         mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
0147         mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
0148     }
0149
0150     /* page count on RxQ */
0151     for (i = 0; i < 200; i++) {
0152         if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) &&
0153             !(mt76_rr(dev, 0x0a30) & 0xffffffff) &&
0154             !(mt76_rr(dev, 0x0a34) & 0xffffffff) &&
0155             ++count > 10)
0156             break;
0157         msleep(50);
0158     }
0159
0160     if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 2000))
0161         dev_warn(dev->mt76.dev, "MAC RX failed to stop\n");
0162
0163     /* wait rx dma to stop */
0164     for (i = 0; i < 2000; i++) {
0165         val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
0166         if (!(val & MT_USB_DMA_CFG_RX_BUSY) && i > 10)
0167             break;
0168         usleep_range(50, 100);
0169     }
0170
0171     mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
0172
0173     return 0;
0174 }