mt76/mt76x2/usb_init.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005
0006 #include <linux/delay.h>
0007
0008 #include "mt76x2u.h"
0009 #include "eeprom.h"
0010 #include "../mt76x02_phy.h"
0011 #include "../mt76x02_usb.h"
0012
0013 static void mt76x2u_init_dma(struct mt76x02_dev *dev)
0014 {
0015     u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG));
0016
0017     val |= MT_USB_DMA_CFG_RX_DROP_OR_PAD |
0018            MT_USB_DMA_CFG_RX_BULK_EN |
0019            MT_USB_DMA_CFG_TX_BULK_EN;
0020
0021     /* disable AGGR_BULK_RX in order to receive one
0022      * frame in each rx urb and avoid copies
0023      */
0024     val &= ~MT_USB_DMA_CFG_RX_BULK_AGG_EN;
0025     mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
0026 }
0027
0028 static void mt76x2u_power_on_rf_patch(struct mt76x02_dev *dev)
0029 {
0030     mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16));
0031     udelay(1);
0032
0033     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff);
0034     mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30);
0035
0036     mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f);
0037     udelay(1);
0038
0039     mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17));
0040     usleep_range(150, 200);
0041
0042     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16));
0043     usleep_range(50, 100);
0044
0045     mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20));
0046 }
0047
0048 static void mt76x2u_power_on_rf(struct mt76x02_dev *dev, int unit)
0049 {
0050     int shift = unit ? 8 : 0;
0051     u32 val = (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift;
0052
0053     /* Enable RF BG */
0054     mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift);
0055     usleep_range(10, 20);
0056
0057     /* Enable RFDIG LDO/AFE/ABB/ADDA */
0058     mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val);
0059     usleep_range(10, 20);
0060
0061     /* Switch RFDIG power to internal LDO */
0062     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift);
0063     usleep_range(10, 20);
0064
0065     mt76x2u_power_on_rf_patch(dev);
0066
0067     mt76_set(dev, 0x530, 0xf);
0068 }
0069
0070 static void mt76x2u_power_on(struct mt76x02_dev *dev)
0071 {
0072     u32 val;
0073
0074     /* Turn on WL MTCMOS */
0075     mt76_set(dev, MT_VEND_ADDR(CFG, 0x148),
0076          MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
0077
0078     val = MT_WLAN_MTC_CTRL_STATE_UP |
0079           MT_WLAN_MTC_CTRL_PWR_ACK |
0080           MT_WLAN_MTC_CTRL_PWR_ACK_S;
0081
0082     mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000);
0083
0084     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16);
0085     usleep_range(10, 20);
0086
0087     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
0088     usleep_range(10, 20);
0089
0090     mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24);
0091     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff);
0092
0093     /* Turn on AD/DA power down */
0094     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3));
0095
0096     /* WLAN function enable */
0097     mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0));
0098
0099     /* Release BBP software reset */
0100     mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18));
0101
0102     mt76x2u_power_on_rf(dev, 0);
0103     mt76x2u_power_on_rf(dev, 1);
0104 }
0105
0106 static int mt76x2u_init_eeprom(struct mt76x02_dev *dev)
0107 {
0108     u32 val, i;
0109
0110     dev->mt76.eeprom.data = devm_kzalloc(dev->mt76.dev,
0111                          MT7612U_EEPROM_SIZE,
0112                          GFP_KERNEL);
0113     dev->mt76.eeprom.size = MT7612U_EEPROM_SIZE;
0114     if (!dev->mt76.eeprom.data)
0115         return -ENOMEM;
0116
0117     for (i = 0; i + 4 <= MT7612U_EEPROM_SIZE; i += 4) {
0118         val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i));
0119         put_unaligned_le32(val, dev->mt76.eeprom.data + i);
0120     }
0121
0122     mt76x02_eeprom_parse_hw_cap(dev);
0123     return 0;
0124 }
0125
0126 int mt76x2u_init_hardware(struct mt76x02_dev *dev)
0127 {
0128     int i, k, err;
0129
0130     mt76x2_reset_wlan(dev, true);
0131     mt76x2u_power_on(dev);
0132
0133     if (!mt76x02_wait_for_mac(&dev->mt76))
0134         return -ETIMEDOUT;
0135
0136     err = mt76x2u_mcu_fw_init(dev);
0137     if (err < 0)
0138         return err;
0139
0140     if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
0141                 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0142                 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100))
0143         return -EIO;
0144
0145     /* wait for asic ready after fw load. */
0146     if (!mt76x02_wait_for_mac(&dev->mt76))
0147         return -ETIMEDOUT;
0148
0149     mt76x2u_init_dma(dev);
0150
0151     err = mt76x2u_mcu_init(dev);
0152     if (err < 0)
0153         return err;
0154
0155     err = mt76x2u_mac_reset(dev);
0156     if (err < 0)
0157         return err;
0158
0159     mt76x02_mac_setaddr(dev, dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
0160     dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
0161
0162     if (!mt76x02_wait_for_txrx_idle(&dev->mt76))
0163         return -ETIMEDOUT;
0164
0165     /* reset wcid table */
0166     for (i = 0; i < 256; i++)
0167         mt76x02_mac_wcid_setup(dev, i, 0, NULL);
0168
0169     /* reset shared key table and pairwise key table */
0170     for (i = 0; i < 16; i++) {
0171         for (k = 0; k < 4; k++)
0172             mt76x02_mac_shared_key_setup(dev, i, k, NULL);
0173     }
0174
0175     mt76x02u_init_beacon_config(dev);
0176
0177     mt76_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
0178     mt76_wr(dev, MT_TXOP_CTRL_CFG, 0x583f);
0179
0180     err = mt76x2_mcu_load_cr(dev, MT_RF_BBP_CR, 0, 0);
0181     if (err < 0)
0182         return err;
0183
0184     mt76x02_phy_set_rxpath(dev);
0185     mt76x02_phy_set_txdac(dev);
0186
0187     return mt76x2u_mac_stop(dev);
0188 }
0189
0190 int mt76x2u_register_device(struct mt76x02_dev *dev)
0191 {
0192     struct ieee80211_hw *hw = mt76_hw(dev);
0193     struct mt76_usb *usb = &dev->mt76.usb;
0194     int err;
0195
0196     INIT_DELAYED_WORK(&dev->cal_work, mt76x2u_phy_calibrate);
0197     err = mt76x02_init_device(dev);
0198     if (err)
0199         return err;
0200
0201     err = mt76x2u_init_eeprom(dev);
0202     if (err < 0)
0203         return err;
0204
0205     usb->mcu.data = devm_kmalloc(dev->mt76.dev, MCU_RESP_URB_SIZE,
0206                      GFP_KERNEL);
0207     if (!usb->mcu.data)
0208         return -ENOMEM;
0209
0210     err = mt76u_alloc_queues(&dev->mt76);
0211     if (err < 0)
0212         goto fail;
0213
0214     err = mt76x2u_init_hardware(dev);
0215     if (err < 0)
0216         goto fail;
0217
0218     /* check hw sg support in order to enable AMSDU */
0219     hw->max_tx_fragments = dev->mt76.usb.sg_en ? MT_TX_SG_MAX_SIZE : 1;
0220     err = mt76_register_device(&dev->mt76, true, mt76x02_rates,
0221                    ARRAY_SIZE(mt76x02_rates));
0222     if (err)
0223         goto fail;
0224
0225     set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
0226
0227     mt76x02_init_debugfs(dev);
0228     mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband);
0229     mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband);
0230
0231     return 0;
0232
0233 fail:
0234     mt76x2u_cleanup(dev);
0235     return err;
0236 }
0237
0238 void mt76x2u_stop_hw(struct mt76x02_dev *dev)
0239 {
0240     cancel_delayed_work_sync(&dev->cal_work);
0241     cancel_delayed_work_sync(&dev->mphy.mac_work);
0242     mt76x2u_mac_stop(dev);
0243 }
0244
0245 void mt76x2u_cleanup(struct mt76x02_dev *dev)
0246 {
0247     mt76x02_mcu_set_radio_state(dev, false);
0248     mt76x2u_stop_hw(dev);
0249     mt76u_queues_deinit(&dev->mt76);
0250 }