mt76/mt76x2/pci_init.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  */
0005
0006 #include <linux/delay.h>
0007 #include "mt76x2.h"
0008 #include "eeprom.h"
0009 #include "mcu.h"
0010 #include "../mt76x02_mac.h"
0011
0012 static void
0013 mt76x2_mac_pbf_init(struct mt76x02_dev *dev)
0014 {
0015     u32 val;
0016
0017     val = MT_PBF_SYS_CTRL_MCU_RESET |
0018           MT_PBF_SYS_CTRL_DMA_RESET |
0019           MT_PBF_SYS_CTRL_MAC_RESET |
0020           MT_PBF_SYS_CTRL_PBF_RESET |
0021           MT_PBF_SYS_CTRL_ASY_RESET;
0022
0023     mt76_set(dev, MT_PBF_SYS_CTRL, val);
0024     mt76_clear(dev, MT_PBF_SYS_CTRL, val);
0025
0026     mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
0027     mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
0028 }
0029
0030 static void
0031 mt76x2_fixup_xtal(struct mt76x02_dev *dev)
0032 {
0033     u16 eep_val;
0034     s8 offset = 0;
0035
0036     eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
0037
0038     offset = eep_val & 0x7f;
0039     if ((eep_val & 0xff) == 0xff)
0040         offset = 0;
0041     else if (eep_val & 0x80)
0042         offset = 0 - offset;
0043
0044     eep_val >>= 8;
0045     if (eep_val == 0x00 || eep_val == 0xff) {
0046         eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
0047         eep_val &= 0xff;
0048
0049         if (eep_val == 0x00 || eep_val == 0xff)
0050             eep_val = 0x14;
0051     }
0052
0053     eep_val &= 0x7f;
0054     mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
0055     mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
0056
0057     eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
0058     switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
0059     case 0:
0060         mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
0061         break;
0062     case 1:
0063         mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
0064         break;
0065     default:
0066         break;
0067     }
0068 }
0069
0070 int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
0071 {
0072     const u8 *macaddr = dev->mphy.macaddr;
0073     u32 val;
0074     int i, k;
0075
0076     if (!mt76x02_wait_for_mac(&dev->mt76))
0077         return -ETIMEDOUT;
0078
0079     val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
0080
0081     val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
0082          MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0083          MT_WPDMA_GLO_CFG_RX_DMA_EN |
0084          MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
0085          MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
0086     val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
0087
0088     mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
0089
0090     mt76x2_mac_pbf_init(dev);
0091     mt76_write_mac_initvals(dev);
0092     mt76x2_fixup_xtal(dev);
0093
0094     mt76_clear(dev, MT_MAC_SYS_CTRL,
0095            MT_MAC_SYS_CTRL_RESET_CSR |
0096            MT_MAC_SYS_CTRL_RESET_BBP);
0097
0098     if (is_mt7612(dev))
0099         mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
0100
0101     mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
0102     mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
0103
0104     mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
0105     mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
0106     usleep_range(5000, 10000);
0107     mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
0108
0109     mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
0110     mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
0111
0112     mt76x02_mac_setaddr(dev, macaddr);
0113     mt76x02e_init_beacon_config(dev);
0114     if (!hard)
0115         return 0;
0116
0117     for (i = 0; i < 256 / 32; i++)
0118         mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
0119
0120     for (i = 0; i < 256; i++) {
0121         mt76x02_mac_wcid_setup(dev, i, 0, NULL);
0122         mt76_wr(dev, MT_WCID_TX_RATE(i), 0);
0123         mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0);
0124     }
0125
0126     for (i = 0; i < MT_MAX_VIFS; i++)
0127         mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
0128
0129     for (i = 0; i < 16; i++)
0130         for (k = 0; k < 4; k++)
0131             mt76x02_mac_shared_key_setup(dev, i, k, NULL);
0132
0133     for (i = 0; i < 16; i++)
0134         mt76_rr(dev, MT_TX_STAT_FIFO);
0135
0136     mt76x02_set_tx_ackto(dev);
0137
0138     return 0;
0139 }
0140
0141 static void
0142 mt76x2_power_on_rf_patch(struct mt76x02_dev *dev)
0143 {
0144     mt76_set(dev, 0x10130, BIT(0) | BIT(16));
0145     udelay(1);
0146
0147     mt76_clear(dev, 0x1001c, 0xff);
0148     mt76_set(dev, 0x1001c, 0x30);
0149
0150     mt76_wr(dev, 0x10014, 0x484f);
0151     udelay(1);
0152
0153     mt76_set(dev, 0x10130, BIT(17));
0154     udelay(125);
0155
0156     mt76_clear(dev, 0x10130, BIT(16));
0157     udelay(50);
0158
0159     mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
0160 }
0161
0162 static void
0163 mt76x2_power_on_rf(struct mt76x02_dev *dev, int unit)
0164 {
0165     int shift = unit ? 8 : 0;
0166
0167     /* Enable RF BG */
0168     mt76_set(dev, 0x10130, BIT(0) << shift);
0169     udelay(10);
0170
0171     /* Enable RFDIG LDO/AFE/ABB/ADDA */
0172     mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
0173     udelay(10);
0174
0175     /* Switch RFDIG power to internal LDO */
0176     mt76_clear(dev, 0x10130, BIT(2) << shift);
0177     udelay(10);
0178
0179     mt76x2_power_on_rf_patch(dev);
0180
0181     mt76_set(dev, 0x530, 0xf);
0182 }
0183
0184 static void
0185 mt76x2_power_on(struct mt76x02_dev *dev)
0186 {
0187     u32 val;
0188
0189     /* Turn on WL MTCMOS */
0190     mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
0191
0192     val = MT_WLAN_MTC_CTRL_STATE_UP |
0193           MT_WLAN_MTC_CTRL_PWR_ACK |
0194           MT_WLAN_MTC_CTRL_PWR_ACK_S;
0195
0196     mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
0197
0198     mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
0199     udelay(10);
0200
0201     mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
0202     udelay(10);
0203
0204     mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
0205     mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
0206
0207     /* Turn on AD/DA power down */
0208     mt76_clear(dev, 0x11204, BIT(3));
0209
0210     /* WLAN function enable */
0211     mt76_set(dev, 0x10080, BIT(0));
0212
0213     /* Release BBP software reset */
0214     mt76_clear(dev, 0x10064, BIT(18));
0215
0216     mt76x2_power_on_rf(dev, 0);
0217     mt76x2_power_on_rf(dev, 1);
0218 }
0219
0220 int mt76x2_resume_device(struct mt76x02_dev *dev)
0221 {
0222     int err;
0223
0224     mt76x02_dma_disable(dev);
0225     mt76x2_reset_wlan(dev, true);
0226     mt76x2_power_on(dev);
0227
0228     err = mt76x2_mac_reset(dev, true);
0229     if (err)
0230         return err;
0231
0232     mt76x02_mac_start(dev);
0233
0234     return mt76x2_mcu_init(dev);
0235 }
0236
0237 static int mt76x2_init_hardware(struct mt76x02_dev *dev)
0238 {
0239     int ret;
0240
0241     mt76x02_dma_disable(dev);
0242     mt76x2_reset_wlan(dev, true);
0243     mt76x2_power_on(dev);
0244
0245     ret = mt76x2_eeprom_init(dev);
0246     if (ret)
0247         return ret;
0248
0249     ret = mt76x2_mac_reset(dev, true);
0250     if (ret)
0251         return ret;
0252
0253     dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
0254
0255     ret = mt76x02_dma_init(dev);
0256     if (ret)
0257         return ret;
0258
0259     set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
0260     mt76x02_mac_start(dev);
0261
0262     ret = mt76x2_mcu_init(dev);
0263     if (ret)
0264         return ret;
0265
0266     mt76x2_mac_stop(dev, false);
0267
0268     return 0;
0269 }
0270
0271 void mt76x2_stop_hardware(struct mt76x02_dev *dev)
0272 {
0273     cancel_delayed_work_sync(&dev->cal_work);
0274     cancel_delayed_work_sync(&dev->mphy.mac_work);
0275     cancel_delayed_work_sync(&dev->wdt_work);
0276     clear_bit(MT76_RESTART, &dev->mphy.state);
0277     mt76x02_mcu_set_radio_state(dev, false);
0278     mt76x2_mac_stop(dev, false);
0279 }
0280
0281 void mt76x2_cleanup(struct mt76x02_dev *dev)
0282 {
0283     tasklet_disable(&dev->dfs_pd.dfs_tasklet);
0284     tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
0285     mt76x2_stop_hardware(dev);
0286     mt76_dma_cleanup(&dev->mt76);
0287     mt76x02_mcu_cleanup(dev);
0288 }
0289
0290 int mt76x2_register_device(struct mt76x02_dev *dev)
0291 {
0292     int ret;
0293
0294     INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
0295     ret = mt76x02_init_device(dev);
0296     if (ret)
0297         return ret;
0298
0299     ret = mt76x2_init_hardware(dev);
0300     if (ret)
0301         return ret;
0302
0303     mt76x02_config_mac_addr_list(dev);
0304
0305     ret = mt76_register_device(&dev->mt76, true, mt76x02_rates,
0306                    ARRAY_SIZE(mt76x02_rates));
0307     if (ret)
0308         goto fail;
0309
0310     mt76x02_init_debugfs(dev);
0311     mt76x2_init_txpower(dev, &dev->mphy.sband_2g.sband);
0312     mt76x2_init_txpower(dev, &dev->mphy.sband_5g.sband);
0313
0314     return 0;
0315
0316 fail:
0317     mt76x2_stop_hardware(dev);
0318     return ret;
0319 }
0320