mt76/mt76x2/init.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0005  */
0006
0007 #include "mt76x2.h"
0008 #include "eeprom.h"
0009 #include "../mt76x02_phy.h"
0010
0011 int mt76x2_set_sar_specs(struct ieee80211_hw *hw,
0012              const struct cfg80211_sar_specs *sar)
0013 {
0014     int err = -EINVAL, power = hw->conf.power_level * 2;
0015     struct mt76x02_dev *dev = hw->priv;
0016     struct mt76_phy *mphy = &dev->mphy;
0017
0018     mutex_lock(&dev->mt76.mutex);
0019     if (!cfg80211_chandef_valid(&mphy->chandef))
0020         goto out;
0021
0022     err = mt76_init_sar_power(hw, sar);
0023     if (err)
0024         goto out;
0025
0026     dev->txpower_conf = mt76_get_sar_power(mphy, mphy->chandef.chan,
0027                            power);
0028     /* convert to per-chain power for 2x2 devices */
0029     dev->txpower_conf -= 6;
0030
0031     if (test_bit(MT76_STATE_RUNNING, &mphy->state))
0032         mt76x2_phy_set_txpower(dev);
0033 out:
0034     mutex_unlock(&dev->mt76.mutex);
0035
0036     return err;
0037 }
0038 EXPORT_SYMBOL_GPL(mt76x2_set_sar_specs);
0039
0040 static void
0041 mt76x2_set_wlan_state(struct mt76x02_dev *dev, bool enable)
0042 {
0043     u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
0044
0045     if (enable)
0046         val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
0047             MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
0048     else
0049         val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
0050              MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
0051
0052     mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
0053     udelay(20);
0054 }
0055
0056 void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable)
0057 {
0058     u32 val;
0059
0060     if (!enable)
0061         goto out;
0062
0063     val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
0064
0065     val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
0066
0067     if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
0068         val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
0069         mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
0070         udelay(20);
0071
0072         val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
0073     }
0074
0075     mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
0076     udelay(20);
0077
0078 out:
0079     mt76x2_set_wlan_state(dev, enable);
0080 }
0081 EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
0082
0083 void mt76_write_mac_initvals(struct mt76x02_dev *dev)
0084 {
0085 #define DEFAULT_PROT_CFG_CCK                \
0086     (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) |        \
0087      FIELD_PREP(MT_PROT_CFG_NAV, 1) |       \
0088      FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
0089      MT_PROT_CFG_RTS_THRESH)
0090
0091 #define DEFAULT_PROT_CFG_OFDM               \
0092     (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |     \
0093      FIELD_PREP(MT_PROT_CFG_NAV, 1) |           \
0094      FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
0095      MT_PROT_CFG_RTS_THRESH)
0096
0097 #define DEFAULT_PROT_CFG_20             \
0098     (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) |     \
0099      FIELD_PREP(MT_PROT_CFG_CTRL, 1) |      \
0100      FIELD_PREP(MT_PROT_CFG_NAV, 1) |           \
0101      FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
0102
0103 #define DEFAULT_PROT_CFG_40             \
0104     (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) |     \
0105      FIELD_PREP(MT_PROT_CFG_CTRL, 1) |      \
0106      FIELD_PREP(MT_PROT_CFG_NAV, 1) |           \
0107      FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
0108
0109     static const struct mt76_reg_pair vals[] = {
0110         /* Copied from MediaTek reference source */
0111         { MT_PBF_SYS_CTRL,      0x00080c00 },
0112         { MT_PBF_CFG,           0x1efebcff },
0113         { MT_FCE_PSE_CTRL,      0x00000001 },
0114         { MT_MAC_SYS_CTRL,      0x00000000 },
0115         { MT_MAX_LEN_CFG,       0x003e3f00 },
0116         { MT_AMPDU_MAX_LEN_20M1S,   0xaaa99887 },
0117         { MT_AMPDU_MAX_LEN_20M2S,   0x000000aa },
0118         { MT_XIFS_TIME_CFG,     0x33a40d0a },
0119         { MT_BKOFF_SLOT_CFG,        0x00000209 },
0120         { MT_TBTT_SYNC_CFG,     0x00422010 },
0121         { MT_PWR_PIN_CFG,       0x00000000 },
0122         { 0x1238,           0x001700c8 },
0123         { MT_TX_SW_CFG0,        0x00101001 },
0124         { MT_TX_SW_CFG1,        0x00010000 },
0125         { MT_TX_SW_CFG2,        0x00000000 },
0126         { MT_TXOP_CTRL_CFG,     0x0400583f },
0127         { MT_TX_RTS_CFG,        0x00ffff20 },
0128         { MT_TX_TIMEOUT_CFG,        0x000a2290 },
0129         { MT_TX_RETRY_CFG,      0x47f01f0f },
0130         { MT_EXP_ACK_TIME,      0x002c00dc },
0131         { MT_TX_PROT_CFG6,      0xe3f42004 },
0132         { MT_TX_PROT_CFG7,      0xe3f42084 },
0133         { MT_TX_PROT_CFG8,      0xe3f42104 },
0134         { MT_PIFS_TX_CFG,       0x00060fff },
0135         { MT_RX_FILTR_CFG,      0x00015f97 },
0136         { MT_LEGACY_BASIC_RATE,     0x0000017f },
0137         { MT_HT_BASIC_RATE,     0x00004003 },
0138         { MT_PN_PAD_MODE,       0x00000003 },
0139         { MT_TXOP_HLDR_ET,      0x00000002 },
0140         { 0xa44,            0x00000000 },
0141         { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
0142         { MT_TSO_CTRL,          0x00000000 },
0143         { MT_AUX_CLK_CFG,       0x00000000 },
0144         { MT_DACCLK_EN_DLY_CFG,     0x00000000 },
0145         { MT_TX_ALC_CFG_4,      0x00000000 },
0146         { MT_TX_ALC_VGA3,       0x00000000 },
0147         { MT_TX_PWR_CFG_0,      0x3a3a3a3a },
0148         { MT_TX_PWR_CFG_1,      0x3a3a3a3a },
0149         { MT_TX_PWR_CFG_2,      0x3a3a3a3a },
0150         { MT_TX_PWR_CFG_3,      0x3a3a3a3a },
0151         { MT_TX_PWR_CFG_4,      0x3a3a3a3a },
0152         { MT_TX_PWR_CFG_7,      0x3a3a3a3a },
0153         { MT_TX_PWR_CFG_8,      0x0000003a },
0154         { MT_TX_PWR_CFG_9,      0x0000003a },
0155         { MT_EFUSE_CTRL,        0x0000d000 },
0156         { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
0157         { MT_FCE_WLAN_FLOW_CONTROL1,    0x60401c18 },
0158         { MT_WPDMA_DELAY_INT_CFG,   0x94ff0000 },
0159         { MT_TX_SW_CFG3,        0x00000004 },
0160         { MT_HT_FBK_TO_LEGACY,      0x00001818 },
0161         { MT_VHT_HT_FBK_CFG1,       0xedcba980 },
0162         { MT_PROT_AUTO_TX_CFG,      0x00830083 },
0163         { MT_HT_CTRL_CFG,       0x000001ff },
0164         { MT_TX_LINK_CFG,       0x00001020 },
0165     };
0166     struct mt76_reg_pair prot_vals[] = {
0167         { MT_CCK_PROT_CFG,      DEFAULT_PROT_CFG_CCK },
0168         { MT_OFDM_PROT_CFG,     DEFAULT_PROT_CFG_OFDM },
0169         { MT_MM20_PROT_CFG,     DEFAULT_PROT_CFG_20 },
0170         { MT_MM40_PROT_CFG,     DEFAULT_PROT_CFG_40 },
0171         { MT_GF20_PROT_CFG,     DEFAULT_PROT_CFG_20 },
0172         { MT_GF40_PROT_CFG,     DEFAULT_PROT_CFG_40 },
0173     };
0174
0175     mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));
0176     mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));
0177 }
0178 EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
0179
0180 void mt76x2_init_txpower(struct mt76x02_dev *dev,
0181              struct ieee80211_supported_band *sband)
0182 {
0183     struct ieee80211_channel *chan;
0184     struct mt76x2_tx_power_info txp;
0185     struct mt76_rate_power t = {};
0186     int i;
0187
0188     for (i = 0; i < sband->n_channels; i++) {
0189         chan = &sband->channels[i];
0190
0191         mt76x2_get_power_info(dev, &txp, chan);
0192         mt76x2_get_rate_power(dev, &t, chan);
0193
0194         chan->orig_mpwr = mt76x02_get_max_rate_power(&t) +
0195                   txp.target_power;
0196         chan->orig_mpwr = DIV_ROUND_UP(chan->orig_mpwr, 2);
0197
0198         /* convert to combined output power on 2x2 devices */
0199         chan->orig_mpwr += 3;
0200         chan->max_power = min_t(int, chan->max_reg_power,
0201                     chan->orig_mpwr);
0202     }
0203 }
0204 EXPORT_SYMBOL_GPL(mt76x2_init_txpower);