mediatek/mt76/mt76x02_usb_core.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005
0006 #include "mt76x02_usb.h"
0007
0008 static void mt76x02u_remove_dma_hdr(struct sk_buff *skb)
0009 {
0010     int hdr_len;
0011
0012     skb_pull(skb, sizeof(struct mt76x02_txwi) + MT_DMA_HDR_LEN);
0013     hdr_len = ieee80211_get_hdrlen_from_skb(skb);
0014     if (hdr_len % 4)
0015         mt76x02_remove_hdr_pad(skb, 2);
0016 }
0017
0018 void mt76x02u_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
0019 {
0020     mt76x02u_remove_dma_hdr(e->skb);
0021     mt76_tx_complete_skb(mdev, e->wcid, e->skb);
0022 }
0023 EXPORT_SYMBOL_GPL(mt76x02u_tx_complete_skb);
0024
0025 int mt76x02u_mac_start(struct mt76x02_dev *dev)
0026 {
0027     mt76x02_mac_reset_counters(dev);
0028
0029     mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
0030     if (!mt76x02_wait_for_wpdma(&dev->mt76, 200000))
0031         return -ETIMEDOUT;
0032
0033     mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
0034
0035     mt76_wr(dev, MT_MAC_SYS_CTRL,
0036         MT_MAC_SYS_CTRL_ENABLE_TX |
0037         MT_MAC_SYS_CTRL_ENABLE_RX);
0038
0039     if (!mt76x02_wait_for_wpdma(&dev->mt76, 50))
0040         return -ETIMEDOUT;
0041
0042     return 0;
0043 }
0044 EXPORT_SYMBOL_GPL(mt76x02u_mac_start);
0045
0046 int mt76x02u_skb_dma_info(struct sk_buff *skb, int port, u32 flags)
0047 {
0048     u32 info, pad;
0049
0050     /* Buffer layout:
0051      *  |   4B   | xfer len |      pad       |  4B  |
0052      *  | TXINFO | pkt/cmd  | zero pad to 4B | zero |
0053      *
0054      * length field of TXINFO should be set to 'xfer len'.
0055      */
0056     info = FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
0057            FIELD_PREP(MT_TXD_INFO_DPORT, port) | flags;
0058     put_unaligned_le32(info, skb_push(skb, sizeof(info)));
0059
0060     pad = round_up(skb->len, 4) + 4 - skb->len;
0061     return mt76_skb_adjust_pad(skb, pad);
0062 }
0063
0064 int mt76x02u_tx_prepare_skb(struct mt76_dev *mdev, void *data,
0065                 enum mt76_txq_id qid, struct mt76_wcid *wcid,
0066                 struct ieee80211_sta *sta,
0067                 struct mt76_tx_info *tx_info)
0068 {
0069     struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
0070     int pid, len = tx_info->skb->len, ep = q2ep(dev->mphy.q_tx[qid]->hw_idx);
0071     struct mt76x02_txwi *txwi;
0072     bool ampdu = IEEE80211_SKB_CB(tx_info->skb)->flags & IEEE80211_TX_CTL_AMPDU;
0073     enum mt76_qsel qsel;
0074     u32 flags;
0075     int err;
0076
0077     mt76_insert_hdr_pad(tx_info->skb);
0078
0079     txwi = (struct mt76x02_txwi *)(tx_info->skb->data - sizeof(*txwi));
0080     mt76x02_mac_write_txwi(dev, txwi, tx_info->skb, wcid, sta, len);
0081     skb_push(tx_info->skb, sizeof(*txwi));
0082
0083     pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
0084
0085     /* encode packet rate for no-skb packet id to fix up status reporting */
0086     if (pid == MT_PACKET_ID_NO_SKB)
0087         pid = MT_PACKET_ID_HAS_RATE |
0088               (le16_to_cpu(txwi->rate) & MT_PKTID_RATE) |
0089               FIELD_PREP(MT_PKTID_AC,
0090                  skb_get_queue_mapping(tx_info->skb));
0091
0092     txwi->pktid = pid;
0093
0094     if ((mt76_is_skb_pktid(pid) && ampdu) || ep == MT_EP_OUT_HCCA)
0095         qsel = MT_QSEL_MGMT;
0096     else
0097         qsel = MT_QSEL_EDCA;
0098
0099     flags = FIELD_PREP(MT_TXD_INFO_QSEL, qsel) |
0100         MT_TXD_INFO_80211;
0101     if (!wcid || wcid->hw_key_idx == 0xff || wcid->sw_iv)
0102         flags |= MT_TXD_INFO_WIV;
0103
0104     if (sta) {
0105         struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
0106
0107         ewma_pktlen_add(&msta->pktlen, tx_info->skb->len);
0108     }
0109
0110     err = mt76x02u_skb_dma_info(tx_info->skb, WLAN_PORT, flags);
0111     if (err && wcid)
0112         /* Release pktid in case of error. */
0113         idr_remove(&wcid->pktid, pid);
0114
0115     return err;
0116 }
0117 EXPORT_SYMBOL_GPL(mt76x02u_tx_prepare_skb);
0118
0119 /* Trigger pre-TBTT event 8 ms before TBTT */
0120 #define PRE_TBTT_USEC 8000
0121
0122 /* Beacon SRAM memory is limited to 8kB. We need to send PS buffered frames
0123  * (which can be 1500 bytes big) via beacon memory. That make limit of number
0124  * of slots to 5. TODO: dynamically calculate offsets in beacon SRAM.
0125  */
0126 #define N_BCN_SLOTS 5
0127
0128 static void mt76x02u_start_pre_tbtt_timer(struct mt76x02_dev *dev)
0129 {
0130     u64 time;
0131     u32 tbtt;
0132
0133     /* Get remaining TBTT in usec */
0134     tbtt = mt76_get_field(dev, MT_TBTT_TIMER, MT_TBTT_TIMER_VAL);
0135     tbtt *= 32;
0136
0137     if (tbtt <= PRE_TBTT_USEC) {
0138         queue_work(system_highpri_wq, &dev->pre_tbtt_work);
0139         return;
0140     }
0141
0142     time = (tbtt - PRE_TBTT_USEC) * 1000ull;
0143     hrtimer_start(&dev->pre_tbtt_timer, time, HRTIMER_MODE_REL);
0144 }
0145
0146 static void mt76x02u_restart_pre_tbtt_timer(struct mt76x02_dev *dev)
0147 {
0148     u32 tbtt, dw0, dw1;
0149     u64 tsf, time;
0150
0151     /* Get remaining TBTT in usec */
0152     tbtt = mt76_get_field(dev, MT_TBTT_TIMER, MT_TBTT_TIMER_VAL);
0153     tbtt *= 32;
0154
0155     dw0 = mt76_rr(dev, MT_TSF_TIMER_DW0);
0156     dw1 = mt76_rr(dev, MT_TSF_TIMER_DW1);
0157     tsf = (u64)dw0 << 32 | dw1;
0158     dev_dbg(dev->mt76.dev, "TSF: %llu us TBTT %u us\n", tsf, tbtt);
0159
0160     /* Convert beacon interval in TU (1024 usec) to nsec */
0161     time = ((1000000000ull * dev->mt76.beacon_int) >> 10);
0162
0163     /* Adjust time to trigger hrtimer 8ms before TBTT */
0164     if (tbtt < PRE_TBTT_USEC)
0165         time -= (PRE_TBTT_USEC - tbtt) * 1000ull;
0166     else
0167         time += (tbtt - PRE_TBTT_USEC) * 1000ull;
0168
0169     hrtimer_start(&dev->pre_tbtt_timer, time, HRTIMER_MODE_REL);
0170 }
0171
0172 static void mt76x02u_stop_pre_tbtt_timer(struct mt76x02_dev *dev)
0173 {
0174     do {
0175         hrtimer_cancel(&dev->pre_tbtt_timer);
0176         cancel_work_sync(&dev->pre_tbtt_work);
0177         /* Timer can be rearmed by work. */
0178     } while (hrtimer_active(&dev->pre_tbtt_timer));
0179 }
0180
0181 static void mt76x02u_pre_tbtt_work(struct work_struct *work)
0182 {
0183     struct mt76x02_dev *dev =
0184         container_of(work, struct mt76x02_dev, pre_tbtt_work);
0185     struct beacon_bc_data data = {};
0186     struct sk_buff *skb;
0187     int nbeacons;
0188
0189     if (!dev->mt76.beacon_mask)
0190         return;
0191
0192     if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
0193         return;
0194
0195     mt76x02_resync_beacon_timer(dev);
0196
0197     /* Prevent corrupt transmissions during update */
0198     mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
0199     dev->beacon_data_count = 0;
0200
0201     ieee80211_iterate_active_interfaces(mt76_hw(dev),
0202         IEEE80211_IFACE_ITER_RESUME_ALL,
0203         mt76x02_update_beacon_iter, dev);
0204
0205     mt76_csa_check(&dev->mt76);
0206
0207     if (dev->mt76.csa_complete) {
0208         mt76_csa_finish(&dev->mt76);
0209         goto out;
0210     }
0211
0212     nbeacons = hweight8(dev->mt76.beacon_mask);
0213     mt76x02_enqueue_buffered_bc(dev, &data, N_BCN_SLOTS - nbeacons);
0214
0215     while ((skb = __skb_dequeue(&data.q)) != NULL)
0216         mt76x02_mac_set_beacon(dev, skb);
0217
0218 out:
0219     mt76_wr(dev, MT_BCN_BYPASS_MASK,
0220         0xff00 | ~(0xff00 >> dev->beacon_data_count));
0221
0222     mt76x02u_restart_pre_tbtt_timer(dev);
0223 }
0224
0225 static enum hrtimer_restart mt76x02u_pre_tbtt_interrupt(struct hrtimer *timer)
0226 {
0227     struct mt76x02_dev *dev =
0228         container_of(timer, struct mt76x02_dev, pre_tbtt_timer);
0229
0230     queue_work(system_highpri_wq, &dev->pre_tbtt_work);
0231
0232     return HRTIMER_NORESTART;
0233 }
0234
0235 static void mt76x02u_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
0236 {
0237     if (en && dev->mt76.beacon_mask &&
0238         !hrtimer_active(&dev->pre_tbtt_timer))
0239         mt76x02u_start_pre_tbtt_timer(dev);
0240     if (!en)
0241         mt76x02u_stop_pre_tbtt_timer(dev);
0242 }
0243
0244 static void mt76x02u_beacon_enable(struct mt76x02_dev *dev, bool en)
0245 {
0246     if (WARN_ON_ONCE(!dev->mt76.beacon_int))
0247         return;
0248
0249     if (en)
0250         mt76x02u_start_pre_tbtt_timer(dev);
0251 }
0252
0253 void mt76x02u_init_beacon_config(struct mt76x02_dev *dev)
0254 {
0255     static const struct mt76x02_beacon_ops beacon_ops = {
0256         .nslots = N_BCN_SLOTS,
0257         .slot_size = (8192 / N_BCN_SLOTS) & ~63,
0258         .pre_tbtt_enable = mt76x02u_pre_tbtt_enable,
0259         .beacon_enable = mt76x02u_beacon_enable,
0260     };
0261     dev->beacon_ops = &beacon_ops;
0262
0263     hrtimer_init(&dev->pre_tbtt_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
0264     dev->pre_tbtt_timer.function = mt76x02u_pre_tbtt_interrupt;
0265     INIT_WORK(&dev->pre_tbtt_work, mt76x02u_pre_tbtt_work);
0266
0267     mt76x02_init_beacon_config(dev);
0268 }
0269 EXPORT_SYMBOL_GPL(mt76x02u_init_beacon_config);
0270
0271 void mt76x02u_exit_beacon_config(struct mt76x02_dev *dev)
0272 {
0273     if (!test_bit(MT76_REMOVED, &dev->mphy.state))
0274         mt76_clear(dev, MT_BEACON_TIME_CFG,
0275                MT_BEACON_TIME_CFG_TIMER_EN |
0276                MT_BEACON_TIME_CFG_SYNC_MODE |
0277                MT_BEACON_TIME_CFG_TBTT_EN |
0278                MT_BEACON_TIME_CFG_BEACON_TX);
0279
0280     mt76x02u_stop_pre_tbtt_timer(dev);
0281 }
0282 EXPORT_SYMBOL_GPL(mt76x02u_exit_beacon_config);