mediatek/mt76/mt76x02_phy.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0005  */
0006
0007 #include <linux/kernel.h>
0008
0009 #include "mt76x02.h"
0010 #include "mt76x02_phy.h"
0011
0012 void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)
0013 {
0014     u32 val;
0015
0016     val = mt76_rr(dev, MT_BBP(AGC, 0));
0017     val &= ~BIT(4);
0018
0019     switch (dev->mphy.chainmask & 0xf) {
0020     case 2:
0021         val |= BIT(3);
0022         break;
0023     default:
0024         val &= ~BIT(3);
0025         break;
0026     }
0027
0028     mt76_wr(dev, MT_BBP(AGC, 0), val);
0029     mb();
0030     val = mt76_rr(dev, MT_BBP(AGC, 0));
0031 }
0032 EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath);
0033
0034 void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)
0035 {
0036     int txpath;
0037
0038     txpath = (dev->mphy.chainmask >> 8) & 0xf;
0039     switch (txpath) {
0040     case 2:
0041         mt76_set(dev, MT_BBP(TXBE, 5), 0x3);
0042         break;
0043     default:
0044         mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);
0045         break;
0046     }
0047 }
0048 EXPORT_SYMBOL_GPL(mt76x02_phy_set_txdac);
0049
0050 static u32
0051 mt76x02_tx_power_mask(u8 v1, u8 v2, u8 v3, u8 v4)
0052 {
0053     u32 val = 0;
0054
0055     val |= (v1 & (BIT(6) - 1)) << 0;
0056     val |= (v2 & (BIT(6) - 1)) << 8;
0057     val |= (v3 & (BIT(6) - 1)) << 16;
0058     val |= (v4 & (BIT(6) - 1)) << 24;
0059     return val;
0060 }
0061
0062 int mt76x02_get_max_rate_power(struct mt76_rate_power *r)
0063 {
0064     s8 ret = 0;
0065     int i;
0066
0067     for (i = 0; i < sizeof(r->all); i++)
0068         ret = max(ret, r->all[i]);
0069
0070     return ret;
0071 }
0072 EXPORT_SYMBOL_GPL(mt76x02_get_max_rate_power);
0073
0074 void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit)
0075 {
0076     int i;
0077
0078     for (i = 0; i < sizeof(r->all); i++)
0079         if (r->all[i] > limit)
0080             r->all[i] = limit;
0081 }
0082 EXPORT_SYMBOL_GPL(mt76x02_limit_rate_power);
0083
0084 void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset)
0085 {
0086     int i;
0087
0088     for (i = 0; i < sizeof(r->all); i++)
0089         r->all[i] += offset;
0090 }
0091 EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset);
0092
0093 void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)
0094 {
0095     struct mt76_rate_power *t = &dev->mt76.rate_power;
0096
0097     mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
0098     mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
0099
0100     mt76_wr(dev, MT_TX_PWR_CFG_0,
0101         mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0],
0102                       t->ofdm[2]));
0103     mt76_wr(dev, MT_TX_PWR_CFG_1,
0104         mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0],
0105                       t->ht[2]));
0106     mt76_wr(dev, MT_TX_PWR_CFG_2,
0107         mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8],
0108                       t->ht[10]));
0109     mt76_wr(dev, MT_TX_PWR_CFG_3,
0110         mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0],
0111                       t->stbc[2]));
0112     mt76_wr(dev, MT_TX_PWR_CFG_4,
0113         mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0));
0114     mt76_wr(dev, MT_TX_PWR_CFG_7,
0115         mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7],
0116                       t->vht[9]));
0117     mt76_wr(dev, MT_TX_PWR_CFG_8,
0118         mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9]));
0119     mt76_wr(dev, MT_TX_PWR_CFG_9,
0120         mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9]));
0121 }
0122 EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower);
0123
0124 void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
0125 {
0126     int core_val, agc_val;
0127
0128     switch (width) {
0129     case NL80211_CHAN_WIDTH_80:
0130         core_val = 3;
0131         agc_val = 7;
0132         break;
0133     case NL80211_CHAN_WIDTH_40:
0134         core_val = 2;
0135         agc_val = 3;
0136         break;
0137     default:
0138         core_val = 0;
0139         agc_val = 1;
0140         break;
0141     }
0142
0143     mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
0144     mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
0145     mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
0146     mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
0147 }
0148 EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw);
0149
0150 void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
0151               bool primary_upper)
0152 {
0153     switch (band) {
0154     case NL80211_BAND_2GHZ:
0155         mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
0156         mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
0157         break;
0158     case NL80211_BAND_5GHZ:
0159         mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
0160         mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
0161         break;
0162     }
0163
0164     mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
0165                primary_upper);
0166 }
0167 EXPORT_SYMBOL_GPL(mt76x02_phy_set_band);
0168
0169 bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)
0170 {
0171     u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
0172     bool ret = false;
0173     u32 false_cca;
0174
0175     false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS,
0176                   mt76_rr(dev, MT_RX_STAT_1));
0177     dev->cal.false_cca = false_cca;
0178     if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {
0179         dev->cal.agc_gain_adjust += 2;
0180         ret = true;
0181     } else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
0182            (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {
0183         dev->cal.agc_gain_adjust -= 2;
0184         ret = true;
0185     }
0186
0187     dev->cal.agc_lowest_gain = dev->cal.agc_gain_adjust >= limit;
0188
0189     return ret;
0190 }
0191 EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain);
0192
0193 void mt76x02_init_agc_gain(struct mt76x02_dev *dev)
0194 {
0195     dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
0196                            MT_BBP_AGC_GAIN);
0197     dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
0198                            MT_BBP_AGC_GAIN);
0199     memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
0200            sizeof(dev->cal.agc_gain_cur));
0201     dev->cal.low_gain = -1;
0202     dev->cal.gain_init_done = true;
0203 }
0204 EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain);