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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/irq.h>
0009 
0010 #include "mt76x02.h"
0011 #include "mt76x02_mcu.h"
0012 #include "trace.h"
0013 
0014 static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t)
0015 {
0016     struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
0017     struct mt76_dev *mdev = &dev->mt76;
0018     struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
0019     struct beacon_bc_data data = {};
0020     struct sk_buff *skb;
0021     int i;
0022 
0023     if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
0024         return;
0025 
0026     mt76x02_resync_beacon_timer(dev);
0027 
0028     /* Prevent corrupt transmissions during update */
0029     mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
0030     dev->beacon_data_count = 0;
0031 
0032     ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
0033         IEEE80211_IFACE_ITER_RESUME_ALL,
0034         mt76x02_update_beacon_iter, dev);
0035 
0036     mt76_wr(dev, MT_BCN_BYPASS_MASK,
0037         0xff00 | ~(0xff00 >> dev->beacon_data_count));
0038 
0039     mt76_csa_check(mdev);
0040 
0041     if (mdev->csa_complete)
0042         return;
0043 
0044     mt76x02_enqueue_buffered_bc(dev, &data, 8);
0045 
0046     if (!skb_queue_len(&data.q))
0047         return;
0048 
0049     for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
0050         if (!data.tail[i])
0051             continue;
0052 
0053         mt76_skb_set_moredata(data.tail[i], false);
0054     }
0055 
0056     spin_lock(&q->lock);
0057     while ((skb = __skb_dequeue(&data.q)) != NULL) {
0058         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0059         struct ieee80211_vif *vif = info->control.vif;
0060         struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
0061 
0062         mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
0063                   NULL);
0064     }
0065     spin_unlock(&q->lock);
0066 }
0067 
0068 static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
0069 {
0070     if (en)
0071         tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
0072     else
0073         tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
0074 }
0075 
0076 static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
0077 {
0078     mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
0079     if (en)
0080         mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
0081     else
0082         mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
0083 }
0084 
0085 void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
0086 {
0087     static const struct mt76x02_beacon_ops beacon_ops = {
0088         .nslots = 8,
0089         .slot_size = 1024,
0090         .pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
0091         .beacon_enable = mt76x02e_beacon_enable,
0092     };
0093 
0094     dev->beacon_ops = &beacon_ops;
0095 
0096     /* Fire a pre-TBTT interrupt 8 ms before TBTT */
0097     mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
0098                8 << 4);
0099     mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
0100                MT_DFS_GP_INTERVAL);
0101     mt76_wr(dev, MT_INT_TIMER_EN, 0);
0102 
0103     mt76x02_init_beacon_config(dev);
0104 }
0105 EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
0106 
0107 static int
0108 mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
0109               int idx, int n_desc, int bufsize)
0110 {
0111     int err;
0112 
0113     err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
0114                    MT_RX_RING_BASE);
0115     if (err < 0)
0116         return err;
0117 
0118     mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
0119 
0120     return 0;
0121 }
0122 
0123 static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
0124 {
0125     struct mt76x02_tx_status stat;
0126     u8 update = 1;
0127 
0128     while (kfifo_get(&dev->txstatus_fifo, &stat))
0129         mt76x02_send_tx_status(dev, &stat, &update);
0130 }
0131 
0132 static void mt76x02_tx_worker(struct mt76_worker *w)
0133 {
0134     struct mt76x02_dev *dev;
0135 
0136     dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
0137 
0138     mt76x02_mac_poll_tx_status(dev, false);
0139     mt76x02_process_tx_status_fifo(dev);
0140 
0141     mt76_txq_schedule_all(&dev->mphy);
0142 }
0143 
0144 static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
0145 {
0146     struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
0147                            mt76.tx_napi);
0148     int i;
0149 
0150     mt76x02_mac_poll_tx_status(dev, false);
0151 
0152     mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
0153     for (i = MT_TXQ_PSD; i >= 0; i--)
0154         mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
0155 
0156     if (napi_complete_done(napi, 0))
0157         mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
0158 
0159     mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
0160     for (i = MT_TXQ_PSD; i >= 0; i--)
0161         mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
0162 
0163     mt76_worker_schedule(&dev->mt76.tx_worker);
0164 
0165     return 0;
0166 }
0167 
0168 int mt76x02_dma_init(struct mt76x02_dev *dev)
0169 {
0170     struct mt76_txwi_cache __maybe_unused *t;
0171     int i, ret, fifo_size;
0172     struct mt76_queue *q;
0173     void *status_fifo;
0174 
0175     BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
0176 
0177     fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
0178     status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
0179     if (!status_fifo)
0180         return -ENOMEM;
0181 
0182     dev->mt76.tx_worker.fn = mt76x02_tx_worker;
0183     tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
0184 
0185     spin_lock_init(&dev->txstatus_fifo_lock);
0186     kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
0187 
0188     mt76_dma_attach(&dev->mt76);
0189 
0190     mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
0191 
0192     for (i = 0; i < IEEE80211_NUM_ACS; i++) {
0193         ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
0194                      MT76x02_TX_RING_SIZE,
0195                      MT_TX_RING_BASE, 0);
0196         if (ret)
0197             return ret;
0198     }
0199 
0200     ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
0201                  MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE, 0);
0202     if (ret)
0203         return ret;
0204 
0205     ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
0206                   MT_MCU_RING_SIZE, MT_TX_RING_BASE);
0207     if (ret)
0208         return ret;
0209 
0210     mt76x02_irq_enable(dev,
0211                MT_INT_TX_DONE(IEEE80211_AC_VO) |
0212                MT_INT_TX_DONE(IEEE80211_AC_VI) |
0213                MT_INT_TX_DONE(IEEE80211_AC_BE) |
0214                MT_INT_TX_DONE(IEEE80211_AC_BK) |
0215                MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
0216                MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU));
0217 
0218     ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
0219                     MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
0220     if (ret)
0221         return ret;
0222 
0223     q = &dev->mt76.q_rx[MT_RXQ_MAIN];
0224     q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
0225     ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
0226                     MT_RX_BUF_SIZE);
0227     if (ret)
0228         return ret;
0229 
0230     ret = mt76_init_queues(dev, mt76_dma_rx_poll);
0231     if (ret)
0232         return ret;
0233 
0234     netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
0235               mt76x02_poll_tx);
0236     napi_enable(&dev->mt76.tx_napi);
0237 
0238     return 0;
0239 }
0240 EXPORT_SYMBOL_GPL(mt76x02_dma_init);
0241 
0242 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
0243 {
0244     struct mt76x02_dev *dev;
0245 
0246     dev = container_of(mdev, struct mt76x02_dev, mt76);
0247     mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
0248 }
0249 EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
0250 
0251 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
0252 {
0253     struct mt76x02_dev *dev = dev_instance;
0254     u32 intr, mask;
0255 
0256     intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
0257     intr &= dev->mt76.mmio.irqmask;
0258     mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
0259 
0260     if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
0261         return IRQ_NONE;
0262 
0263     trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
0264 
0265     mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
0266     if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
0267         mask |= MT_INT_TX_DONE_ALL;
0268 
0269     mt76x02_irq_disable(dev, mask);
0270 
0271     if (intr & MT_INT_RX_DONE(0))
0272         napi_schedule(&dev->mt76.napi[0]);
0273 
0274     if (intr & MT_INT_RX_DONE(1))
0275         napi_schedule(&dev->mt76.napi[1]);
0276 
0277     if (intr & MT_INT_PRE_TBTT)
0278         tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
0279 
0280     /* send buffered multicast frames now */
0281     if (intr & MT_INT_TBTT) {
0282         if (dev->mt76.csa_complete)
0283             mt76_csa_finish(&dev->mt76);
0284         else
0285             mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
0286     }
0287 
0288     if (intr & MT_INT_TX_STAT)
0289         mt76x02_mac_poll_tx_status(dev, true);
0290 
0291     if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
0292         napi_schedule(&dev->mt76.tx_napi);
0293 
0294     if (intr & MT_INT_GPTIMER)
0295         tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
0296 
0297     return IRQ_HANDLED;
0298 }
0299 EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
0300 
0301 static void mt76x02_dma_enable(struct mt76x02_dev *dev)
0302 {
0303     u32 val;
0304 
0305     mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
0306     mt76x02_wait_for_wpdma(&dev->mt76, 1000);
0307     usleep_range(50, 100);
0308 
0309     val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
0310           MT_WPDMA_GLO_CFG_TX_DMA_EN |
0311           MT_WPDMA_GLO_CFG_RX_DMA_EN;
0312     mt76_set(dev, MT_WPDMA_GLO_CFG, val);
0313     mt76_clear(dev, MT_WPDMA_GLO_CFG,
0314            MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
0315 }
0316 
0317 void mt76x02_dma_disable(struct mt76x02_dev *dev)
0318 {
0319     u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
0320 
0321     val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
0322            MT_WPDMA_GLO_CFG_BIG_ENDIAN |
0323            MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
0324     val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
0325     mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
0326 }
0327 EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
0328 
0329 void mt76x02_mac_start(struct mt76x02_dev *dev)
0330 {
0331     mt76x02_mac_reset_counters(dev);
0332     mt76x02_dma_enable(dev);
0333     mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
0334     mt76_wr(dev, MT_MAC_SYS_CTRL,
0335         MT_MAC_SYS_CTRL_ENABLE_TX |
0336         MT_MAC_SYS_CTRL_ENABLE_RX);
0337     mt76x02_irq_enable(dev,
0338                MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
0339                MT_INT_TX_STAT);
0340 }
0341 EXPORT_SYMBOL_GPL(mt76x02_mac_start);
0342 
0343 static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
0344 {
0345     u32 dma_idx, prev_dma_idx;
0346     struct mt76_queue *q;
0347     int i;
0348 
0349     for (i = 0; i < 4; i++) {
0350         q = dev->mphy.q_tx[i];
0351 
0352         prev_dma_idx = dev->mt76.tx_dma_idx[i];
0353         dma_idx = readl(&q->regs->dma_idx);
0354         dev->mt76.tx_dma_idx[i] = dma_idx;
0355 
0356         if (!q->queued || prev_dma_idx != dma_idx) {
0357             dev->tx_hang_check[i] = 0;
0358             continue;
0359         }
0360 
0361         if (++dev->tx_hang_check[i] >= MT_TX_HANG_TH)
0362             return true;
0363     }
0364 
0365     return false;
0366 }
0367 
0368 static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
0369                  struct ieee80211_sta *sta,
0370                  struct ieee80211_key_conf *key, void *data)
0371 {
0372     struct mt76x02_dev *dev = hw->priv;
0373     struct mt76_wcid *wcid;
0374 
0375     if (!sta)
0376         return;
0377 
0378     wcid = (struct mt76_wcid *)sta->drv_priv;
0379 
0380     if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
0381         return;
0382 
0383     mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
0384 }
0385 
0386 static void mt76x02_reset_state(struct mt76x02_dev *dev)
0387 {
0388     int i;
0389 
0390     lockdep_assert_held(&dev->mt76.mutex);
0391 
0392     clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
0393 
0394     rcu_read_lock();
0395     ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
0396     rcu_read_unlock();
0397 
0398     for (i = 0; i < MT76x02_N_WCIDS; i++) {
0399         struct ieee80211_sta *sta;
0400         struct ieee80211_vif *vif;
0401         struct mt76x02_sta *msta;
0402         struct mt76_wcid *wcid;
0403         void *priv;
0404 
0405         wcid = rcu_dereference_protected(dev->mt76.wcid[i],
0406                     lockdep_is_held(&dev->mt76.mutex));
0407         if (!wcid)
0408             continue;
0409 
0410         rcu_assign_pointer(dev->mt76.wcid[i], NULL);
0411 
0412         priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
0413         sta = container_of(priv, struct ieee80211_sta, drv_priv);
0414 
0415         priv = msta->vif;
0416         vif = container_of(priv, struct ieee80211_vif, drv_priv);
0417 
0418         __mt76_sta_remove(&dev->mt76, vif, sta);
0419         memset(msta, 0, sizeof(*msta));
0420     }
0421 
0422     dev->mt76.vif_mask = 0;
0423     dev->mt76.beacon_mask = 0;
0424 }
0425 
0426 static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
0427 {
0428     u32 mask = dev->mt76.mmio.irqmask;
0429     bool restart = dev->mt76.mcu_ops->mcu_restart;
0430     int i;
0431 
0432     ieee80211_stop_queues(dev->mt76.hw);
0433     set_bit(MT76_RESET, &dev->mphy.state);
0434 
0435     tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
0436     mt76_worker_disable(&dev->mt76.tx_worker);
0437     napi_disable(&dev->mt76.tx_napi);
0438 
0439     mt76_for_each_q_rx(&dev->mt76, i) {
0440         napi_disable(&dev->mt76.napi[i]);
0441     }
0442 
0443     mutex_lock(&dev->mt76.mutex);
0444 
0445     dev->mcu_timeout = 0;
0446     if (restart)
0447         mt76x02_reset_state(dev);
0448 
0449     if (dev->mt76.beacon_mask)
0450         mt76_clear(dev, MT_BEACON_TIME_CFG,
0451                MT_BEACON_TIME_CFG_BEACON_TX |
0452                MT_BEACON_TIME_CFG_TBTT_EN);
0453 
0454     mt76x02_irq_disable(dev, mask);
0455 
0456     /* perform device reset */
0457     mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
0458     mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
0459     mt76_clear(dev, MT_WPDMA_GLO_CFG,
0460            MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
0461     usleep_range(5000, 10000);
0462     mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
0463 
0464     /* let fw reset DMA */
0465     mt76_set(dev, 0x734, 0x3);
0466 
0467     if (restart)
0468         mt76_mcu_restart(dev);
0469 
0470     mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
0471     for (i = 0; i < __MT_TXQ_MAX; i++)
0472         mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
0473 
0474     mt76_for_each_q_rx(&dev->mt76, i) {
0475         mt76_queue_rx_reset(dev, i);
0476     }
0477 
0478     mt76_tx_status_check(&dev->mt76, true);
0479 
0480     mt76x02_mac_start(dev);
0481 
0482     if (dev->ed_monitor)
0483         mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
0484 
0485     if (dev->mt76.beacon_mask && !restart)
0486         mt76_set(dev, MT_BEACON_TIME_CFG,
0487              MT_BEACON_TIME_CFG_BEACON_TX |
0488              MT_BEACON_TIME_CFG_TBTT_EN);
0489 
0490     mt76x02_irq_enable(dev, mask);
0491 
0492     mutex_unlock(&dev->mt76.mutex);
0493 
0494     clear_bit(MT76_RESET, &dev->mphy.state);
0495 
0496     mt76_worker_enable(&dev->mt76.tx_worker);
0497     tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
0498 
0499     local_bh_disable();
0500     napi_enable(&dev->mt76.tx_napi);
0501     napi_schedule(&dev->mt76.tx_napi);
0502 
0503     mt76_for_each_q_rx(&dev->mt76, i) {
0504         napi_enable(&dev->mt76.napi[i]);
0505         napi_schedule(&dev->mt76.napi[i]);
0506     }
0507     local_bh_enable();
0508 
0509     if (restart) {
0510         set_bit(MT76_RESTART, &dev->mphy.state);
0511         mt76x02_mcu_function_select(dev, Q_SELECT, 1);
0512         ieee80211_restart_hw(dev->mt76.hw);
0513     } else {
0514         ieee80211_wake_queues(dev->mt76.hw);
0515         mt76_txq_schedule_all(&dev->mphy);
0516     }
0517 }
0518 
0519 void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
0520                    enum ieee80211_reconfig_type reconfig_type)
0521 {
0522     struct mt76x02_dev *dev = hw->priv;
0523 
0524     if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
0525         return;
0526 
0527     clear_bit(MT76_RESTART, &dev->mphy.state);
0528 }
0529 EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete);
0530 
0531 static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
0532 {
0533     if (test_bit(MT76_RESTART, &dev->mphy.state))
0534         return;
0535 
0536     if (!mt76x02_tx_hang(dev) && !dev->mcu_timeout)
0537         return;
0538 
0539     mt76x02_watchdog_reset(dev);
0540 
0541     dev->tx_hang_reset++;
0542     memset(dev->tx_hang_check, 0, sizeof(dev->tx_hang_check));
0543     memset(dev->mt76.tx_dma_idx, 0xff,
0544            sizeof(dev->mt76.tx_dma_idx));
0545 }
0546 
0547 void mt76x02_wdt_work(struct work_struct *work)
0548 {
0549     struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
0550                            wdt_work.work);
0551 
0552     mt76x02_check_tx_hang(dev);
0553 
0554     ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
0555                      MT_WATCHDOG_TIME);
0556 }
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