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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
0005  */
0006 
0007 #ifndef __MT76X02_MAC_H
0008 #define __MT76X02_MAC_H
0009 
0010 struct mt76x02_dev;
0011 
0012 struct mt76x02_tx_status {
0013     u8 valid:1;
0014     u8 success:1;
0015     u8 aggr:1;
0016     u8 ack_req:1;
0017     u8 wcid;
0018     u8 pktid;
0019     u8 retry;
0020     u16 rate;
0021 } __packed __aligned(2);
0022 
0023 #define MT_VIF_WCID(_n)     (254 - ((_n) & 7))
0024 #define MT_MAX_VIFS     8
0025 
0026 #define MT_PKTID_RATE       GENMASK(4, 0)
0027 #define MT_PKTID_AC     GENMASK(6, 5)
0028 
0029 struct mt76x02_vif {
0030     struct mt76_wcid group_wcid; /* must be first */
0031     u8 idx;
0032 };
0033 
0034 DECLARE_EWMA(pktlen, 8, 8);
0035 
0036 struct mt76x02_sta {
0037     struct mt76_wcid wcid; /* must be first */
0038 
0039     struct mt76x02_vif *vif;
0040     struct mt76x02_tx_status status;
0041     int n_frames;
0042 
0043     struct ewma_pktlen pktlen;
0044 };
0045 
0046 #define MT_RXINFO_BA            BIT(0)
0047 #define MT_RXINFO_DATA          BIT(1)
0048 #define MT_RXINFO_NULL          BIT(2)
0049 #define MT_RXINFO_FRAG          BIT(3)
0050 #define MT_RXINFO_UNICAST       BIT(4)
0051 #define MT_RXINFO_MULTICAST     BIT(5)
0052 #define MT_RXINFO_BROADCAST     BIT(6)
0053 #define MT_RXINFO_MYBSS         BIT(7)
0054 #define MT_RXINFO_CRCERR        BIT(8)
0055 #define MT_RXINFO_ICVERR        BIT(9)
0056 #define MT_RXINFO_MICERR        BIT(10)
0057 #define MT_RXINFO_AMSDU         BIT(11)
0058 #define MT_RXINFO_HTC           BIT(12)
0059 #define MT_RXINFO_RSSI          BIT(13)
0060 #define MT_RXINFO_L2PAD         BIT(14)
0061 #define MT_RXINFO_AMPDU         BIT(15)
0062 #define MT_RXINFO_DECRYPT       BIT(16)
0063 #define MT_RXINFO_BSSIDX3       BIT(17)
0064 #define MT_RXINFO_WAPI_KEY      BIT(18)
0065 #define MT_RXINFO_PN_LEN        GENMASK(21, 19)
0066 #define MT_RXINFO_SW_FTYPE0     BIT(22)
0067 #define MT_RXINFO_SW_FTYPE1     BIT(23)
0068 #define MT_RXINFO_PROBE_RESP        BIT(24)
0069 #define MT_RXINFO_BEACON        BIT(25)
0070 #define MT_RXINFO_DISASSOC      BIT(26)
0071 #define MT_RXINFO_DEAUTH        BIT(27)
0072 #define MT_RXINFO_ACTION        BIT(28)
0073 #define MT_RXINFO_TCP_SUM_ERR       BIT(30)
0074 #define MT_RXINFO_IP_SUM_ERR        BIT(31)
0075 
0076 #define MT_RXWI_CTL_WCID        GENMASK(7, 0)
0077 #define MT_RXWI_CTL_KEY_IDX     GENMASK(9, 8)
0078 #define MT_RXWI_CTL_BSS_IDX     GENMASK(12, 10)
0079 #define MT_RXWI_CTL_UDF         GENMASK(15, 13)
0080 #define MT_RXWI_CTL_MPDU_LEN        GENMASK(29, 16)
0081 #define MT_RXWI_CTL_EOF         BIT(31)
0082 
0083 #define MT_RXWI_TID         GENMASK(3, 0)
0084 #define MT_RXWI_SN          GENMASK(15, 4)
0085 
0086 #define MT_RXWI_RATE_INDEX      GENMASK(5, 0)
0087 #define MT_RXWI_RATE_LDPC       BIT(6)
0088 #define MT_RXWI_RATE_BW         GENMASK(8, 7)
0089 #define MT_RXWI_RATE_SGI        BIT(9)
0090 #define MT_RXWI_RATE_STBC       BIT(10)
0091 #define MT_RXWI_RATE_LDPC_EXSYM     BIT(11)
0092 #define MT_RXWI_RATE_PHY        GENMASK(15, 13)
0093 
0094 #define MT_RATE_INDEX_VHT_IDX       GENMASK(3, 0)
0095 #define MT_RATE_INDEX_VHT_NSS       GENMASK(5, 4)
0096 
0097 struct mt76x02_rxwi {
0098     __le32 rxinfo;
0099 
0100     __le32 ctl;
0101 
0102     __le16 tid_sn;
0103     __le16 rate;
0104 
0105     u8 rssi[4];
0106 
0107     __le32 bbp_rxinfo[4];
0108 };
0109 
0110 #define MT_TX_PWR_ADJ           GENMASK(3, 0)
0111 
0112 enum mt76x2_phy_bandwidth {
0113     MT_PHY_BW_20,
0114     MT_PHY_BW_40,
0115     MT_PHY_BW_80,
0116 };
0117 
0118 #define MT_TXWI_FLAGS_FRAG      BIT(0)
0119 #define MT_TXWI_FLAGS_MMPS      BIT(1)
0120 #define MT_TXWI_FLAGS_CFACK     BIT(2)
0121 #define MT_TXWI_FLAGS_TS        BIT(3)
0122 #define MT_TXWI_FLAGS_AMPDU     BIT(4)
0123 #define MT_TXWI_FLAGS_MPDU_DENSITY  GENMASK(7, 5)
0124 #define MT_TXWI_FLAGS_TXOP      GENMASK(9, 8)
0125 #define MT_TXWI_FLAGS_NDPS      BIT(10)
0126 #define MT_TXWI_FLAGS_RTSBWSIG      BIT(11)
0127 #define MT_TXWI_FLAGS_NDP_BW        GENMASK(13, 12)
0128 #define MT_TXWI_FLAGS_SOUND     BIT(14)
0129 #define MT_TXWI_FLAGS_TX_RATE_LUT   BIT(15)
0130 
0131 #define MT_TXWI_ACK_CTL_REQ     BIT(0)
0132 #define MT_TXWI_ACK_CTL_NSEQ        BIT(1)
0133 #define MT_TXWI_ACK_CTL_BA_WINDOW   GENMASK(7, 2)
0134 
0135 struct mt76x02_txwi {
0136     __le16 flags;
0137     __le16 rate;
0138     u8 ack_ctl;
0139     u8 wcid;
0140     __le16 len_ctl;
0141     __le32 iv;
0142     __le32 eiv;
0143     u8 aid;
0144     u8 txstream;
0145     u8 ctl2;
0146     u8 pktid;
0147 } __packed __aligned(4);
0148 
0149 static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev)
0150 {
0151     const u32 MAC_CSR0 = 0x1000;
0152     int i;
0153 
0154     for (i = 0; i < 500; i++) {
0155         if (test_bit(MT76_REMOVED, &dev->phy.state))
0156             return false;
0157 
0158         switch (dev->bus->rr(dev, MAC_CSR0)) {
0159         case 0:
0160         case ~0:
0161             break;
0162         default:
0163             return true;
0164         }
0165         usleep_range(5000, 10000);
0166     }
0167     return false;
0168 }
0169 
0170 void mt76x02_mac_reset_counters(struct mt76x02_dev *dev);
0171 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable);
0172 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
0173                  u8 key_idx, struct ieee80211_key_conf *key);
0174 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
0175                  struct ieee80211_key_conf *key);
0176 void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
0177                   struct ieee80211_key_conf *key);
0178 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx,
0179                 u8 *mac);
0180 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop);
0181 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
0182                    const struct ieee80211_tx_rate *rate);
0183 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
0184                 struct mt76x02_tx_status *stat);
0185 void mt76x02_send_tx_status(struct mt76x02_dev *dev,
0186                 struct mt76x02_tx_status *stat, u8 *update);
0187 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
0188                void *rxi);
0189 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot,
0190                    int ht_mode);
0191 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val);
0192 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr);
0193 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
0194                 struct sk_buff *skb, struct mt76_wcid *wcid,
0195                 struct ieee80211_sta *sta, int len);
0196 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq);
0197 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e);
0198 void mt76x02_update_channel(struct mt76_phy *mphy);
0199 void mt76x02_mac_work(struct work_struct *work);
0200 
0201 void mt76x02_mac_cc_reset(struct mt76x02_dev *dev);
0202 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr);
0203 void mt76x02_mac_set_beacon(struct mt76x02_dev *dev, struct sk_buff *skb);
0204 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev,
0205                    struct ieee80211_vif *vif, bool enable);
0206 
0207 void mt76x02_edcca_init(struct mt76x02_dev *dev);
0208 #endif
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