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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
0005  */
0006 
0007 #include "mt76x02.h"
0008 #include "mt76x02_trace.h"
0009 #include "trace.h"
0010 
0011 void mt76x02_mac_reset_counters(struct mt76x02_dev *dev)
0012 {
0013     int i;
0014 
0015     mt76_rr(dev, MT_RX_STAT_0);
0016     mt76_rr(dev, MT_RX_STAT_1);
0017     mt76_rr(dev, MT_RX_STAT_2);
0018     mt76_rr(dev, MT_TX_STA_0);
0019     mt76_rr(dev, MT_TX_STA_1);
0020     mt76_rr(dev, MT_TX_STA_2);
0021 
0022     for (i = 0; i < 16; i++)
0023         mt76_rr(dev, MT_TX_AGG_CNT(i));
0024 
0025     for (i = 0; i < 16; i++)
0026         mt76_rr(dev, MT_TX_STAT_FIFO);
0027 
0028     memset(dev->mt76.aggr_stats, 0, sizeof(dev->mt76.aggr_stats));
0029 }
0030 EXPORT_SYMBOL_GPL(mt76x02_mac_reset_counters);
0031 
0032 static enum mt76x02_cipher_type
0033 mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
0034 {
0035     memset(key_data, 0, 32);
0036     if (!key)
0037         return MT76X02_CIPHER_NONE;
0038 
0039     if (key->keylen > 32)
0040         return MT76X02_CIPHER_NONE;
0041 
0042     memcpy(key_data, key->key, key->keylen);
0043 
0044     switch (key->cipher) {
0045     case WLAN_CIPHER_SUITE_WEP40:
0046         return MT76X02_CIPHER_WEP40;
0047     case WLAN_CIPHER_SUITE_WEP104:
0048         return MT76X02_CIPHER_WEP104;
0049     case WLAN_CIPHER_SUITE_TKIP:
0050         return MT76X02_CIPHER_TKIP;
0051     case WLAN_CIPHER_SUITE_CCMP:
0052         return MT76X02_CIPHER_AES_CCMP;
0053     default:
0054         return MT76X02_CIPHER_NONE;
0055     }
0056 }
0057 
0058 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
0059                  u8 key_idx, struct ieee80211_key_conf *key)
0060 {
0061     enum mt76x02_cipher_type cipher;
0062     u8 key_data[32];
0063     u32 val;
0064 
0065     cipher = mt76x02_mac_get_key_info(key, key_data);
0066     if (cipher == MT76X02_CIPHER_NONE && key)
0067         return -EOPNOTSUPP;
0068 
0069     val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
0070     val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
0071     val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
0072     mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
0073 
0074     mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data,
0075              sizeof(key_data));
0076 
0077     return 0;
0078 }
0079 EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup);
0080 
0081 void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
0082                   struct ieee80211_key_conf *key)
0083 {
0084     enum mt76x02_cipher_type cipher;
0085     u8 key_data[32];
0086     u32 iv, eiv;
0087     u64 pn;
0088 
0089     cipher = mt76x02_mac_get_key_info(key, key_data);
0090     iv = mt76_rr(dev, MT_WCID_IV(idx));
0091     eiv = mt76_rr(dev, MT_WCID_IV(idx) + 4);
0092 
0093     pn = (u64)eiv << 16;
0094     if (cipher == MT76X02_CIPHER_TKIP) {
0095         pn |= (iv >> 16) & 0xff;
0096         pn |= (iv & 0xff) << 8;
0097     } else if (cipher >= MT76X02_CIPHER_AES_CCMP) {
0098         pn |= iv & 0xffff;
0099     } else {
0100         return;
0101     }
0102 
0103     atomic64_set(&key->tx_pn, pn);
0104 }
0105 
0106 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
0107                  struct ieee80211_key_conf *key)
0108 {
0109     enum mt76x02_cipher_type cipher;
0110     u8 key_data[32];
0111     u8 iv_data[8];
0112     u64 pn;
0113 
0114     cipher = mt76x02_mac_get_key_info(key, key_data);
0115     if (cipher == MT76X02_CIPHER_NONE && key)
0116         return -EOPNOTSUPP;
0117 
0118     mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
0119     mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
0120 
0121     memset(iv_data, 0, sizeof(iv_data));
0122     if (key) {
0123         mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
0124                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
0125 
0126         pn = atomic64_read(&key->tx_pn);
0127 
0128         iv_data[3] = key->keyidx << 6;
0129         if (cipher >= MT76X02_CIPHER_TKIP) {
0130             iv_data[3] |= 0x20;
0131             put_unaligned_le32(pn >> 16, &iv_data[4]);
0132         }
0133 
0134         if (cipher == MT76X02_CIPHER_TKIP) {
0135             iv_data[0] = (pn >> 8) & 0xff;
0136             iv_data[1] = (iv_data[0] | 0x20) & 0x7f;
0137             iv_data[2] = pn & 0xff;
0138         } else if (cipher >= MT76X02_CIPHER_AES_CCMP) {
0139             put_unaligned_le16((pn & 0xffff), &iv_data[0]);
0140         }
0141     }
0142 
0143     mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
0144 
0145     return 0;
0146 }
0147 
0148 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx,
0149                 u8 vif_idx, u8 *mac)
0150 {
0151     struct mt76_wcid_addr addr = {};
0152     u32 attr;
0153 
0154     attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
0155            FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
0156 
0157     mt76_wr(dev, MT_WCID_ATTR(idx), attr);
0158 
0159     if (idx >= 128)
0160         return;
0161 
0162     if (mac)
0163         memcpy(addr.macaddr, mac, ETH_ALEN);
0164 
0165     mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
0166 }
0167 EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup);
0168 
0169 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop)
0170 {
0171     u32 val = mt76_rr(dev, MT_WCID_DROP(idx));
0172     u32 bit = MT_WCID_DROP_MASK(idx);
0173 
0174     /* prevent unnecessary writes */
0175     if ((val & bit) != (bit * drop))
0176         mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop));
0177 }
0178 
0179 static u16
0180 mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev,
0181             const struct ieee80211_tx_rate *rate, u8 *nss_val)
0182 {
0183     u8 phy, rate_idx, nss, bw = 0;
0184     u16 rateval;
0185 
0186     if (rate->flags & IEEE80211_TX_RC_VHT_MCS) {
0187         rate_idx = rate->idx;
0188         nss = 1 + (rate->idx >> 4);
0189         phy = MT_PHY_TYPE_VHT;
0190         if (rate->flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
0191             bw = 2;
0192         else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
0193             bw = 1;
0194     } else if (rate->flags & IEEE80211_TX_RC_MCS) {
0195         rate_idx = rate->idx;
0196         nss = 1 + (rate->idx >> 3);
0197         phy = MT_PHY_TYPE_HT;
0198         if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
0199             phy = MT_PHY_TYPE_HT_GF;
0200         if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
0201             bw = 1;
0202     } else {
0203         const struct ieee80211_rate *r;
0204         int band = dev->mphy.chandef.chan->band;
0205         u16 val;
0206 
0207         r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx];
0208         if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
0209             val = r->hw_value_short;
0210         else
0211             val = r->hw_value;
0212 
0213         phy = val >> 8;
0214         rate_idx = val & 0xff;
0215         nss = 1;
0216     }
0217 
0218     rateval = FIELD_PREP(MT_RXWI_RATE_INDEX, rate_idx);
0219     rateval |= FIELD_PREP(MT_RXWI_RATE_PHY, phy);
0220     rateval |= FIELD_PREP(MT_RXWI_RATE_BW, bw);
0221     if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
0222         rateval |= MT_RXWI_RATE_SGI;
0223 
0224     *nss_val = nss;
0225     return rateval;
0226 }
0227 
0228 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
0229                    const struct ieee80211_tx_rate *rate)
0230 {
0231     s8 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
0232     u16 rateval;
0233     u32 tx_info;
0234     s8 nss;
0235 
0236     rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss);
0237     tx_info = FIELD_PREP(MT_WCID_TX_INFO_RATE, rateval) |
0238           FIELD_PREP(MT_WCID_TX_INFO_NSS, nss) |
0239           FIELD_PREP(MT_WCID_TX_INFO_TXPWR_ADJ, max_txpwr_adj) |
0240           MT_WCID_TX_INFO_SET;
0241     wcid->tx_info = tx_info;
0242 }
0243 
0244 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable)
0245 {
0246     if (enable)
0247         mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
0248     else
0249         mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT);
0250 }
0251 
0252 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
0253                 struct mt76x02_tx_status *stat)
0254 {
0255     u32 stat1, stat2;
0256 
0257     stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT);
0258     stat1 = mt76_rr(dev, MT_TX_STAT_FIFO);
0259 
0260     stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID);
0261     if (!stat->valid)
0262         return false;
0263 
0264     stat->success = !!(stat1 & MT_TX_STAT_FIFO_SUCCESS);
0265     stat->aggr = !!(stat1 & MT_TX_STAT_FIFO_AGGR);
0266     stat->ack_req = !!(stat1 & MT_TX_STAT_FIFO_ACKREQ);
0267     stat->wcid = FIELD_GET(MT_TX_STAT_FIFO_WCID, stat1);
0268     stat->rate = FIELD_GET(MT_TX_STAT_FIFO_RATE, stat1);
0269 
0270     stat->retry = FIELD_GET(MT_TX_STAT_FIFO_EXT_RETRY, stat2);
0271     stat->pktid = FIELD_GET(MT_TX_STAT_FIFO_EXT_PKTID, stat2);
0272 
0273     trace_mac_txstat_fetch(dev, stat);
0274 
0275     return true;
0276 }
0277 
0278 static int
0279 mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
0280                 enum nl80211_band band)
0281 {
0282     u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
0283 
0284     txrate->idx = 0;
0285     txrate->flags = 0;
0286     txrate->count = 1;
0287 
0288     switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
0289     case MT_PHY_TYPE_OFDM:
0290         if (band == NL80211_BAND_2GHZ)
0291             idx += 4;
0292 
0293         txrate->idx = idx;
0294         return 0;
0295     case MT_PHY_TYPE_CCK:
0296         if (idx >= 8)
0297             idx -= 8;
0298 
0299         txrate->idx = idx;
0300         return 0;
0301     case MT_PHY_TYPE_HT_GF:
0302         txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD;
0303         fallthrough;
0304     case MT_PHY_TYPE_HT:
0305         txrate->flags |= IEEE80211_TX_RC_MCS;
0306         txrate->idx = idx;
0307         break;
0308     case MT_PHY_TYPE_VHT:
0309         txrate->flags |= IEEE80211_TX_RC_VHT_MCS;
0310         txrate->idx = idx;
0311         break;
0312     default:
0313         return -EINVAL;
0314     }
0315 
0316     switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
0317     case MT_PHY_BW_20:
0318         break;
0319     case MT_PHY_BW_40:
0320         txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
0321         break;
0322     case MT_PHY_BW_80:
0323         txrate->flags |= IEEE80211_TX_RC_80_MHZ_WIDTH;
0324         break;
0325     default:
0326         return -EINVAL;
0327     }
0328 
0329     if (rate & MT_RXWI_RATE_SGI)
0330         txrate->flags |= IEEE80211_TX_RC_SHORT_GI;
0331 
0332     return 0;
0333 }
0334 
0335 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
0336                 struct sk_buff *skb, struct mt76_wcid *wcid,
0337                 struct ieee80211_sta *sta, int len)
0338 {
0339     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
0340     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0341     struct ieee80211_tx_rate *rate = &info->control.rates[0];
0342     struct ieee80211_key_conf *key = info->control.hw_key;
0343     u32 wcid_tx_info;
0344     u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
0345     u16 txwi_flags = 0, rateval;
0346     u8 nss;
0347     s8 txpwr_adj, max_txpwr_adj;
0348     u8 ccmp_pn[8], nstreams = dev->mphy.chainmask & 0xf;
0349 
0350     memset(txwi, 0, sizeof(*txwi));
0351 
0352     mt76_tx_check_agg_ssn(sta, skb);
0353 
0354     if (!info->control.hw_key && wcid && wcid->hw_key_idx != 0xff &&
0355         ieee80211_has_protected(hdr->frame_control)) {
0356         wcid = NULL;
0357         ieee80211_get_tx_rates(info->control.vif, sta, skb,
0358                        info->control.rates, 1);
0359     }
0360 
0361     if (wcid)
0362         txwi->wcid = wcid->idx;
0363     else
0364         txwi->wcid = 0xff;
0365 
0366     if (wcid && wcid->sw_iv && key) {
0367         u64 pn = atomic64_inc_return(&key->tx_pn);
0368 
0369         ccmp_pn[0] = pn;
0370         ccmp_pn[1] = pn >> 8;
0371         ccmp_pn[2] = 0;
0372         ccmp_pn[3] = 0x20 | (key->keyidx << 6);
0373         ccmp_pn[4] = pn >> 16;
0374         ccmp_pn[5] = pn >> 24;
0375         ccmp_pn[6] = pn >> 32;
0376         ccmp_pn[7] = pn >> 40;
0377         txwi->iv = *((__le32 *)&ccmp_pn[0]);
0378         txwi->eiv = *((__le32 *)&ccmp_pn[4]);
0379     }
0380 
0381     if (wcid && (rate->idx < 0 || !rate->count)) {
0382         wcid_tx_info = wcid->tx_info;
0383         rateval = FIELD_GET(MT_WCID_TX_INFO_RATE, wcid_tx_info);
0384         max_txpwr_adj = FIELD_GET(MT_WCID_TX_INFO_TXPWR_ADJ,
0385                       wcid_tx_info);
0386         nss = FIELD_GET(MT_WCID_TX_INFO_NSS, wcid_tx_info);
0387     } else {
0388         rateval = mt76x02_mac_tx_rate_val(dev, rate, &nss);
0389         max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
0390     }
0391     txwi->rate = cpu_to_le16(rateval);
0392 
0393     txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->txpower_conf,
0394                          max_txpwr_adj);
0395     txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
0396 
0397     if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4)
0398         txwi->txstream = 0x13;
0399     else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 &&
0400          !(txwi->rate & cpu_to_le16(rate_ht_mask)))
0401         txwi->txstream = 0x93;
0402 
0403     if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC))
0404         txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC);
0405     if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1)
0406         txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC);
0407     if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC)
0408         txwi_flags |= MT_TXWI_FLAGS_MMPS;
0409     if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
0410         txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
0411     if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
0412         txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
0413     if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
0414         u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
0415         u8 ampdu_density = sta->deflink.ht_cap.ampdu_density;
0416 
0417         ba_size <<= sta->deflink.ht_cap.ampdu_factor;
0418         ba_size = min_t(int, 63, ba_size - 1);
0419         if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
0420             ba_size = 0;
0421         txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
0422 
0423         if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
0424             ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
0425 
0426         txwi_flags |= MT_TXWI_FLAGS_AMPDU |
0427              FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY, ampdu_density);
0428     }
0429 
0430     if (ieee80211_is_probe_resp(hdr->frame_control) ||
0431         ieee80211_is_beacon(hdr->frame_control))
0432         txwi_flags |= MT_TXWI_FLAGS_TS;
0433 
0434     txwi->flags |= cpu_to_le16(txwi_flags);
0435     txwi->len_ctl = cpu_to_le16(len);
0436 }
0437 EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi);
0438 
0439 static void
0440 mt76x02_tx_rate_fallback(struct ieee80211_tx_rate *rates, int idx, int phy)
0441 {
0442     u8 mcs, nss;
0443 
0444     if (!idx)
0445         return;
0446 
0447     rates += idx - 1;
0448     rates[1] = rates[0];
0449     switch (phy) {
0450     case MT_PHY_TYPE_VHT:
0451         mcs = ieee80211_rate_get_vht_mcs(rates);
0452         nss = ieee80211_rate_get_vht_nss(rates);
0453 
0454         if (mcs == 0)
0455             nss = max_t(int, nss - 1, 1);
0456         else
0457             mcs--;
0458 
0459         ieee80211_rate_set_vht(rates + 1, mcs, nss);
0460         break;
0461     case MT_PHY_TYPE_HT_GF:
0462     case MT_PHY_TYPE_HT:
0463         /* MCS 8 falls back to MCS 0 */
0464         if (rates[0].idx == 8) {
0465             rates[1].idx = 0;
0466             break;
0467         }
0468         fallthrough;
0469     default:
0470         rates[1].idx = max_t(int, rates[0].idx - 1, 0);
0471         break;
0472     }
0473 }
0474 
0475 static void
0476 mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev, struct mt76x02_sta *msta,
0477                struct ieee80211_tx_info *info,
0478                struct mt76x02_tx_status *st, int n_frames)
0479 {
0480     struct ieee80211_tx_rate *rate = info->status.rates;
0481     struct ieee80211_tx_rate last_rate;
0482     u16 first_rate;
0483     int retry = st->retry;
0484     int phy;
0485     int i;
0486 
0487     if (!n_frames)
0488         return;
0489 
0490     phy = FIELD_GET(MT_RXWI_RATE_PHY, st->rate);
0491 
0492     if (st->pktid & MT_PACKET_ID_HAS_RATE) {
0493         first_rate = st->rate & ~MT_PKTID_RATE;
0494         first_rate |= st->pktid & MT_PKTID_RATE;
0495 
0496         mt76x02_mac_process_tx_rate(&rate[0], first_rate,
0497                         dev->mphy.chandef.chan->band);
0498     } else if (rate[0].idx < 0) {
0499         if (!msta)
0500             return;
0501 
0502         mt76x02_mac_process_tx_rate(&rate[0], msta->wcid.tx_info,
0503                         dev->mphy.chandef.chan->band);
0504     }
0505 
0506     mt76x02_mac_process_tx_rate(&last_rate, st->rate,
0507                     dev->mphy.chandef.chan->band);
0508 
0509     for (i = 0; i < ARRAY_SIZE(info->status.rates); i++) {
0510         retry--;
0511         if (i + 1 == ARRAY_SIZE(info->status.rates)) {
0512             info->status.rates[i] = last_rate;
0513             info->status.rates[i].count = max_t(int, retry, 1);
0514             break;
0515         }
0516 
0517         mt76x02_tx_rate_fallback(info->status.rates, i, phy);
0518         if (info->status.rates[i].idx == last_rate.idx)
0519             break;
0520     }
0521 
0522     if (i + 1 < ARRAY_SIZE(info->status.rates)) {
0523         info->status.rates[i + 1].idx = -1;
0524         info->status.rates[i + 1].count = 0;
0525     }
0526 
0527     info->status.ampdu_len = n_frames;
0528     info->status.ampdu_ack_len = st->success ? n_frames : 0;
0529 
0530     if (st->aggr)
0531         info->flags |= IEEE80211_TX_CTL_AMPDU |
0532                    IEEE80211_TX_STAT_AMPDU;
0533 
0534     if (!st->ack_req)
0535         info->flags |= IEEE80211_TX_CTL_NO_ACK;
0536     else if (st->success)
0537         info->flags |= IEEE80211_TX_STAT_ACK;
0538 }
0539 
0540 void mt76x02_send_tx_status(struct mt76x02_dev *dev,
0541                 struct mt76x02_tx_status *stat, u8 *update)
0542 {
0543     struct ieee80211_tx_info info = {};
0544     struct ieee80211_tx_status status = {
0545         .info = &info
0546     };
0547     static const u8 ac_to_tid[4] = {
0548         [IEEE80211_AC_BE] = 0,
0549         [IEEE80211_AC_BK] = 1,
0550         [IEEE80211_AC_VI] = 4,
0551         [IEEE80211_AC_VO] = 6
0552     };
0553     struct mt76_wcid *wcid = NULL;
0554     struct mt76x02_sta *msta = NULL;
0555     struct mt76_dev *mdev = &dev->mt76;
0556     struct sk_buff_head list;
0557     u32 duration = 0;
0558     u8 cur_pktid;
0559     u32 ac = 0;
0560     int len = 0;
0561 
0562     if (stat->pktid == MT_PACKET_ID_NO_ACK)
0563         return;
0564 
0565     rcu_read_lock();
0566 
0567     if (stat->wcid < MT76x02_N_WCIDS)
0568         wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]);
0569 
0570     if (wcid && wcid->sta) {
0571         void *priv;
0572 
0573         priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
0574         status.sta = container_of(priv, struct ieee80211_sta,
0575                       drv_priv);
0576     }
0577 
0578     mt76_tx_status_lock(mdev, &list);
0579 
0580     if (wcid) {
0581         if (mt76_is_skb_pktid(stat->pktid))
0582             status.skb = mt76_tx_status_skb_get(mdev, wcid,
0583                                 stat->pktid, &list);
0584         if (status.skb)
0585             status.info = IEEE80211_SKB_CB(status.skb);
0586     }
0587 
0588     if (!status.skb && !(stat->pktid & MT_PACKET_ID_HAS_RATE)) {
0589         mt76_tx_status_unlock(mdev, &list);
0590         goto out;
0591     }
0592 
0593 
0594     if (msta && stat->aggr && !status.skb) {
0595         u32 stat_val, stat_cache;
0596 
0597         stat_val = stat->rate;
0598         stat_val |= ((u32)stat->retry) << 16;
0599         stat_cache = msta->status.rate;
0600         stat_cache |= ((u32)msta->status.retry) << 16;
0601 
0602         if (*update == 0 && stat_val == stat_cache &&
0603             stat->wcid == msta->status.wcid && msta->n_frames < 32) {
0604             msta->n_frames++;
0605             mt76_tx_status_unlock(mdev, &list);
0606             goto out;
0607         }
0608 
0609         cur_pktid = msta->status.pktid;
0610         mt76x02_mac_fill_tx_status(dev, msta, status.info,
0611                        &msta->status, msta->n_frames);
0612 
0613         msta->status = *stat;
0614         msta->n_frames = 1;
0615         *update = 0;
0616     } else {
0617         cur_pktid = stat->pktid;
0618         mt76x02_mac_fill_tx_status(dev, msta, status.info, stat, 1);
0619         *update = 1;
0620     }
0621 
0622     if (status.skb) {
0623         info = *status.info;
0624         len = status.skb->len;
0625         ac = skb_get_queue_mapping(status.skb);
0626         mt76_tx_status_skb_done(mdev, status.skb, &list);
0627     } else if (msta) {
0628         len = status.info->status.ampdu_len * ewma_pktlen_read(&msta->pktlen);
0629         ac = FIELD_GET(MT_PKTID_AC, cur_pktid);
0630     }
0631 
0632     mt76_tx_status_unlock(mdev, &list);
0633 
0634     if (!status.skb)
0635         ieee80211_tx_status_ext(mt76_hw(dev), &status);
0636 
0637     if (!len)
0638         goto out;
0639 
0640     duration = ieee80211_calc_tx_airtime(mt76_hw(dev), &info, len);
0641 
0642     spin_lock_bh(&dev->mt76.cc_lock);
0643     dev->tx_airtime += duration;
0644     spin_unlock_bh(&dev->mt76.cc_lock);
0645 
0646     if (msta)
0647         ieee80211_sta_register_airtime(status.sta, ac_to_tid[ac], duration, 0);
0648 
0649 out:
0650     rcu_read_unlock();
0651 }
0652 
0653 static int
0654 mt76x02_mac_process_rate(struct mt76x02_dev *dev,
0655              struct mt76_rx_status *status,
0656              u16 rate)
0657 {
0658     u8 idx = FIELD_GET(MT_RXWI_RATE_INDEX, rate);
0659 
0660     switch (FIELD_GET(MT_RXWI_RATE_PHY, rate)) {
0661     case MT_PHY_TYPE_OFDM:
0662         if (idx >= 8)
0663             idx = 0;
0664 
0665         if (status->band == NL80211_BAND_2GHZ)
0666             idx += 4;
0667 
0668         status->rate_idx = idx;
0669         return 0;
0670     case MT_PHY_TYPE_CCK:
0671         if (idx >= 8) {
0672             idx -= 8;
0673             status->enc_flags |= RX_ENC_FLAG_SHORTPRE;
0674         }
0675 
0676         if (idx >= 4)
0677             idx = 0;
0678 
0679         status->rate_idx = idx;
0680         return 0;
0681     case MT_PHY_TYPE_HT_GF:
0682         status->enc_flags |= RX_ENC_FLAG_HT_GF;
0683         fallthrough;
0684     case MT_PHY_TYPE_HT:
0685         status->encoding = RX_ENC_HT;
0686         status->rate_idx = idx;
0687         break;
0688     case MT_PHY_TYPE_VHT: {
0689         u8 n_rxstream = dev->mphy.chainmask & 0xf;
0690 
0691         status->encoding = RX_ENC_VHT;
0692         status->rate_idx = FIELD_GET(MT_RATE_INDEX_VHT_IDX, idx);
0693         status->nss = min_t(u8, n_rxstream,
0694                     FIELD_GET(MT_RATE_INDEX_VHT_NSS, idx) + 1);
0695         break;
0696     }
0697     default:
0698         return -EINVAL;
0699     }
0700 
0701     if (rate & MT_RXWI_RATE_LDPC)
0702         status->enc_flags |= RX_ENC_FLAG_LDPC;
0703 
0704     if (rate & MT_RXWI_RATE_SGI)
0705         status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
0706 
0707     if (rate & MT_RXWI_RATE_STBC)
0708         status->enc_flags |= 1 << RX_ENC_FLAG_STBC_SHIFT;
0709 
0710     switch (FIELD_GET(MT_RXWI_RATE_BW, rate)) {
0711     case MT_PHY_BW_20:
0712         break;
0713     case MT_PHY_BW_40:
0714         status->bw = RATE_INFO_BW_40;
0715         break;
0716     case MT_PHY_BW_80:
0717         status->bw = RATE_INFO_BW_80;
0718         break;
0719     default:
0720         break;
0721     }
0722 
0723     return 0;
0724 }
0725 
0726 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr)
0727 {
0728     static const u8 null_addr[ETH_ALEN] = {};
0729     int i;
0730 
0731     ether_addr_copy(dev->mphy.macaddr, addr);
0732 
0733     if (!is_valid_ether_addr(dev->mphy.macaddr)) {
0734         eth_random_addr(dev->mphy.macaddr);
0735         dev_info(dev->mt76.dev,
0736              "Invalid MAC address, using random address %pM\n",
0737              dev->mphy.macaddr);
0738     }
0739 
0740     mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mphy.macaddr));
0741     mt76_wr(dev, MT_MAC_ADDR_DW1,
0742         get_unaligned_le16(dev->mphy.macaddr + 4) |
0743         FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
0744 
0745     mt76_wr(dev, MT_MAC_BSSID_DW0,
0746         get_unaligned_le32(dev->mphy.macaddr));
0747     mt76_wr(dev, MT_MAC_BSSID_DW1,
0748         get_unaligned_le16(dev->mphy.macaddr + 4) |
0749         FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 APs + 8 STAs */
0750         MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
0751     /* enable 7 additional beacon slots and control them with bypass mask */
0752     mt76_rmw_field(dev, MT_MAC_BSSID_DW1, MT_MAC_BSSID_DW1_MBEACON_N, 7);
0753 
0754     for (i = 0; i < 16; i++)
0755         mt76x02_mac_set_bssid(dev, i, null_addr);
0756 }
0757 EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr);
0758 
0759 static int
0760 mt76x02_mac_get_rssi(struct mt76x02_dev *dev, s8 rssi, int chain)
0761 {
0762     struct mt76x02_rx_freq_cal *cal = &dev->cal.rx;
0763 
0764     rssi += cal->rssi_offset[chain];
0765     rssi -= cal->lna_gain;
0766 
0767     return rssi;
0768 }
0769 
0770 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
0771                void *rxi)
0772 {
0773     struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
0774     struct ieee80211_hdr *hdr;
0775     struct mt76x02_rxwi *rxwi = rxi;
0776     struct mt76x02_sta *sta;
0777     u32 rxinfo = le32_to_cpu(rxwi->rxinfo);
0778     u32 ctl = le32_to_cpu(rxwi->ctl);
0779     u16 rate = le16_to_cpu(rxwi->rate);
0780     u16 tid_sn = le16_to_cpu(rxwi->tid_sn);
0781     bool unicast = rxwi->rxinfo & cpu_to_le32(MT_RXINFO_UNICAST);
0782     int pad_len = 0, nstreams = dev->mphy.chainmask & 0xf;
0783     s8 signal;
0784     u8 pn_len;
0785     u8 wcid;
0786     int len;
0787 
0788     if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
0789         return -EINVAL;
0790 
0791     if (rxinfo & MT_RXINFO_L2PAD)
0792         pad_len += 2;
0793 
0794     if (rxinfo & MT_RXINFO_DECRYPT) {
0795         status->flag |= RX_FLAG_DECRYPTED;
0796         status->flag |= RX_FLAG_MMIC_STRIPPED;
0797         status->flag |= RX_FLAG_MIC_STRIPPED;
0798         status->flag |= RX_FLAG_IV_STRIPPED;
0799     }
0800 
0801     wcid = FIELD_GET(MT_RXWI_CTL_WCID, ctl);
0802     sta = mt76x02_rx_get_sta(&dev->mt76, wcid);
0803     status->wcid = mt76x02_rx_get_sta_wcid(sta, unicast);
0804 
0805     len = FIELD_GET(MT_RXWI_CTL_MPDU_LEN, ctl);
0806     pn_len = FIELD_GET(MT_RXINFO_PN_LEN, rxinfo);
0807     if (pn_len) {
0808         int offset = ieee80211_get_hdrlen_from_skb(skb) + pad_len;
0809         u8 *data = skb->data + offset;
0810 
0811         status->iv[0] = data[7];
0812         status->iv[1] = data[6];
0813         status->iv[2] = data[5];
0814         status->iv[3] = data[4];
0815         status->iv[4] = data[1];
0816         status->iv[5] = data[0];
0817 
0818         /*
0819          * Driver CCMP validation can't deal with fragments.
0820          * Let mac80211 take care of it.
0821          */
0822         if (rxinfo & MT_RXINFO_FRAG) {
0823             status->flag &= ~RX_FLAG_IV_STRIPPED;
0824         } else {
0825             pad_len += pn_len << 2;
0826             len -= pn_len << 2;
0827         }
0828     }
0829 
0830     mt76x02_remove_hdr_pad(skb, pad_len);
0831 
0832     if ((rxinfo & MT_RXINFO_BA) && !(rxinfo & MT_RXINFO_NULL))
0833         status->aggr = true;
0834 
0835     if (rxinfo & MT_RXINFO_AMPDU) {
0836         status->flag |= RX_FLAG_AMPDU_DETAILS;
0837         status->ampdu_ref = dev->ampdu_ref;
0838 
0839         /*
0840          * When receiving an A-MPDU subframe and RSSI info is not valid,
0841          * we can assume that more subframes belonging to the same A-MPDU
0842          * are coming. The last one will have valid RSSI info
0843          */
0844         if (rxinfo & MT_RXINFO_RSSI) {
0845             if (!++dev->ampdu_ref)
0846                 dev->ampdu_ref++;
0847         }
0848     }
0849 
0850     if (WARN_ON_ONCE(len > skb->len))
0851         return -EINVAL;
0852 
0853     pskb_trim(skb, len);
0854 
0855     status->chains = BIT(0);
0856     signal = mt76x02_mac_get_rssi(dev, rxwi->rssi[0], 0);
0857     status->chain_signal[0] = signal;
0858     if (nstreams > 1) {
0859         status->chains |= BIT(1);
0860         status->chain_signal[1] = mt76x02_mac_get_rssi(dev,
0861                                    rxwi->rssi[1],
0862                                    1);
0863     }
0864     status->freq = dev->mphy.chandef.chan->center_freq;
0865     status->band = dev->mphy.chandef.chan->band;
0866 
0867     hdr = (struct ieee80211_hdr *)skb->data;
0868     status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
0869     status->seqno = FIELD_GET(MT_RXWI_SN, tid_sn);
0870 
0871     return mt76x02_mac_process_rate(dev, status, rate);
0872 }
0873 
0874 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq)
0875 {
0876     struct mt76x02_tx_status stat = {};
0877     u8 update = 1;
0878     bool ret;
0879 
0880     if (!test_bit(MT76_STATE_RUNNING, &dev->mphy.state))
0881         return;
0882 
0883     trace_mac_txstat_poll(dev);
0884 
0885     while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) {
0886         if (!spin_trylock(&dev->txstatus_fifo_lock))
0887             break;
0888 
0889         ret = mt76x02_mac_load_tx_status(dev, &stat);
0890         spin_unlock(&dev->txstatus_fifo_lock);
0891 
0892         if (!ret)
0893             break;
0894 
0895         if (!irq) {
0896             mt76x02_send_tx_status(dev, &stat, &update);
0897             continue;
0898         }
0899 
0900         kfifo_put(&dev->txstatus_fifo, stat);
0901     }
0902 }
0903 
0904 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
0905 {
0906     struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
0907     struct mt76x02_txwi *txwi;
0908     u8 *txwi_ptr;
0909 
0910     if (!e->txwi) {
0911         dev_kfree_skb_any(e->skb);
0912         return;
0913     }
0914 
0915     mt76x02_mac_poll_tx_status(dev, false);
0916 
0917     txwi_ptr = mt76_get_txwi_ptr(mdev, e->txwi);
0918     txwi = (struct mt76x02_txwi *)txwi_ptr;
0919     trace_mac_txdone(mdev, txwi->wcid, txwi->pktid);
0920 
0921     mt76_tx_complete_skb(mdev, e->wcid, e->skb);
0922 }
0923 EXPORT_SYMBOL_GPL(mt76x02_tx_complete_skb);
0924 
0925 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val)
0926 {
0927     u32 data = 0;
0928 
0929     if (val != ~0)
0930         data = FIELD_PREP(MT_PROT_CFG_CTRL, 1) |
0931                MT_PROT_CFG_RTS_THRESH;
0932 
0933     mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, val);
0934 
0935     mt76_rmw(dev, MT_CCK_PROT_CFG,
0936          MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
0937     mt76_rmw(dev, MT_OFDM_PROT_CFG,
0938          MT_PROT_CFG_CTRL | MT_PROT_CFG_RTS_THRESH, data);
0939 }
0940 
0941 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot,
0942                    int ht_mode)
0943 {
0944     int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION;
0945     bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
0946     u32 prot[6];
0947     u32 vht_prot[3];
0948     int i;
0949     u16 rts_thr;
0950 
0951     for (i = 0; i < ARRAY_SIZE(prot); i++) {
0952         prot[i] = mt76_rr(dev, MT_CCK_PROT_CFG + i * 4);
0953         prot[i] &= ~MT_PROT_CFG_CTRL;
0954         if (i >= 2)
0955             prot[i] &= ~MT_PROT_CFG_RATE;
0956     }
0957 
0958     for (i = 0; i < ARRAY_SIZE(vht_prot); i++) {
0959         vht_prot[i] = mt76_rr(dev, MT_TX_PROT_CFG6 + i * 4);
0960         vht_prot[i] &= ~(MT_PROT_CFG_CTRL | MT_PROT_CFG_RATE);
0961     }
0962 
0963     rts_thr = mt76_get_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH);
0964 
0965     if (rts_thr != 0xffff)
0966         prot[0] |= MT_PROT_CTRL_RTS_CTS;
0967 
0968     if (legacy_prot) {
0969         prot[1] |= MT_PROT_CTRL_CTS2SELF;
0970 
0971         prot[2] |= MT_PROT_RATE_CCK_11;
0972         prot[3] |= MT_PROT_RATE_CCK_11;
0973         prot[4] |= MT_PROT_RATE_CCK_11;
0974         prot[5] |= MT_PROT_RATE_CCK_11;
0975 
0976         vht_prot[0] |= MT_PROT_RATE_CCK_11;
0977         vht_prot[1] |= MT_PROT_RATE_CCK_11;
0978         vht_prot[2] |= MT_PROT_RATE_CCK_11;
0979     } else {
0980         if (rts_thr != 0xffff)
0981             prot[1] |= MT_PROT_CTRL_RTS_CTS;
0982 
0983         prot[2] |= MT_PROT_RATE_OFDM_24;
0984         prot[3] |= MT_PROT_RATE_DUP_OFDM_24;
0985         prot[4] |= MT_PROT_RATE_OFDM_24;
0986         prot[5] |= MT_PROT_RATE_DUP_OFDM_24;
0987 
0988         vht_prot[0] |= MT_PROT_RATE_OFDM_24;
0989         vht_prot[1] |= MT_PROT_RATE_DUP_OFDM_24;
0990         vht_prot[2] |= MT_PROT_RATE_SGI_OFDM_24;
0991     }
0992 
0993     switch (mode) {
0994     case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
0995     case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
0996         prot[2] |= MT_PROT_CTRL_RTS_CTS;
0997         prot[3] |= MT_PROT_CTRL_RTS_CTS;
0998         prot[4] |= MT_PROT_CTRL_RTS_CTS;
0999         prot[5] |= MT_PROT_CTRL_RTS_CTS;
1000         vht_prot[0] |= MT_PROT_CTRL_RTS_CTS;
1001         vht_prot[1] |= MT_PROT_CTRL_RTS_CTS;
1002         vht_prot[2] |= MT_PROT_CTRL_RTS_CTS;
1003         break;
1004     case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1005         prot[3] |= MT_PROT_CTRL_RTS_CTS;
1006         prot[5] |= MT_PROT_CTRL_RTS_CTS;
1007         vht_prot[1] |= MT_PROT_CTRL_RTS_CTS;
1008         vht_prot[2] |= MT_PROT_CTRL_RTS_CTS;
1009         break;
1010     }
1011 
1012     if (non_gf) {
1013         prot[4] |= MT_PROT_CTRL_RTS_CTS;
1014         prot[5] |= MT_PROT_CTRL_RTS_CTS;
1015     }
1016 
1017     for (i = 0; i < ARRAY_SIZE(prot); i++)
1018         mt76_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]);
1019 
1020     for (i = 0; i < ARRAY_SIZE(vht_prot); i++)
1021         mt76_wr(dev, MT_TX_PROT_CFG6 + i * 4, vht_prot[i]);
1022 }
1023 
1024 void mt76x02_update_channel(struct mt76_phy *mphy)
1025 {
1026     struct mt76x02_dev *dev = container_of(mphy->dev, struct mt76x02_dev, mt76);
1027     struct mt76_channel_state *state;
1028 
1029     state = mphy->chan_state;
1030     state->cc_busy += mt76_rr(dev, MT_CH_BUSY);
1031 
1032     spin_lock_bh(&dev->mt76.cc_lock);
1033     state->cc_tx += dev->tx_airtime;
1034     dev->tx_airtime = 0;
1035     spin_unlock_bh(&dev->mt76.cc_lock);
1036 }
1037 EXPORT_SYMBOL_GPL(mt76x02_update_channel);
1038 
1039 static void mt76x02_check_mac_err(struct mt76x02_dev *dev)
1040 {
1041     if (dev->mt76.beacon_mask) {
1042         if (mt76_rr(dev, MT_TX_STA_0) & MT_TX_STA_0_BEACONS) {
1043             dev->beacon_hang_check = 0;
1044             return;
1045         }
1046 
1047         if (dev->beacon_hang_check < 10)
1048             return;
1049 
1050     } else {
1051         u32 val = mt76_rr(dev, 0x10f4);
1052         if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5))))
1053             return;
1054     }
1055 
1056     dev_err(dev->mt76.dev, "MAC error detected\n");
1057 
1058     mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
1059     if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) {
1060         dev_err(dev->mt76.dev, "MAC stop failed\n");
1061         goto out;
1062     }
1063 
1064     dev->beacon_hang_check = 0;
1065     mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR);
1066     udelay(10);
1067 
1068 out:
1069     mt76_wr(dev, MT_MAC_SYS_CTRL,
1070         MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
1071 }
1072 
1073 static void
1074 mt76x02_edcca_tx_enable(struct mt76x02_dev *dev, bool enable)
1075 {
1076     if (enable) {
1077         u32 data;
1078 
1079         mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
1080         mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN);
1081         /* enable pa-lna */
1082         data = mt76_rr(dev, MT_TX_PIN_CFG);
1083         data |= MT_TX_PIN_CFG_TXANT |
1084             MT_TX_PIN_CFG_RXANT |
1085             MT_TX_PIN_RFTR_EN |
1086             MT_TX_PIN_TRSW_EN;
1087         mt76_wr(dev, MT_TX_PIN_CFG, data);
1088     } else {
1089         mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
1090         mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_EN);
1091         /* disable pa-lna */
1092         mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_TXANT);
1093         mt76_clear(dev, MT_TX_PIN_CFG, MT_TX_PIN_CFG_RXANT);
1094     }
1095     dev->ed_tx_blocked = !enable;
1096 }
1097 
1098 void mt76x02_edcca_init(struct mt76x02_dev *dev)
1099 {
1100     dev->ed_trigger = 0;
1101     dev->ed_silent = 0;
1102 
1103     if (dev->ed_monitor) {
1104         struct ieee80211_channel *chan = dev->mphy.chandef.chan;
1105         u8 ed_th = chan->band == NL80211_BAND_5GHZ ? 0x0e : 0x20;
1106 
1107         mt76_clear(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN);
1108         mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
1109         mt76_rmw(dev, MT_BBP(AGC, 2), GENMASK(15, 0),
1110              ed_th << 8 | ed_th);
1111         mt76_set(dev, MT_TXOP_HLDR_ET, MT_TXOP_HLDR_TX40M_BLK_EN);
1112     } else {
1113         mt76_set(dev, MT_TX_LINK_CFG, MT_TX_CFACK_EN);
1114         mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
1115         if (is_mt76x2(dev)) {
1116             mt76_wr(dev, MT_BBP(AGC, 2), 0x00007070);
1117             mt76_set(dev, MT_TXOP_HLDR_ET,
1118                  MT_TXOP_HLDR_TX40M_BLK_EN);
1119         } else {
1120             mt76_wr(dev, MT_BBP(AGC, 2), 0x003a6464);
1121             mt76_clear(dev, MT_TXOP_HLDR_ET,
1122                    MT_TXOP_HLDR_TX40M_BLK_EN);
1123         }
1124     }
1125     mt76x02_edcca_tx_enable(dev, true);
1126     dev->ed_monitor_learning = true;
1127 
1128     /* clear previous CCA timer value */
1129     mt76_rr(dev, MT_ED_CCA_TIMER);
1130     dev->ed_time = ktime_get_boottime();
1131 }
1132 EXPORT_SYMBOL_GPL(mt76x02_edcca_init);
1133 
1134 #define MT_EDCCA_TH     92
1135 #define MT_EDCCA_BLOCK_TH   2
1136 #define MT_EDCCA_LEARN_TH   50
1137 #define MT_EDCCA_LEARN_CCA  180
1138 #define MT_EDCCA_LEARN_TIMEOUT  (20 * HZ)
1139 
1140 static void mt76x02_edcca_check(struct mt76x02_dev *dev)
1141 {
1142     ktime_t cur_time;
1143     u32 active, val, busy;
1144 
1145     cur_time = ktime_get_boottime();
1146     val = mt76_rr(dev, MT_ED_CCA_TIMER);
1147 
1148     active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1149     dev->ed_time = cur_time;
1150 
1151     busy = (val * 100) / active;
1152     busy = min_t(u32, busy, 100);
1153 
1154     if (busy > MT_EDCCA_TH) {
1155         dev->ed_trigger++;
1156         dev->ed_silent = 0;
1157     } else {
1158         dev->ed_silent++;
1159         dev->ed_trigger = 0;
1160     }
1161 
1162     if (dev->cal.agc_lowest_gain &&
1163         dev->cal.false_cca > MT_EDCCA_LEARN_CCA &&
1164         dev->ed_trigger > MT_EDCCA_LEARN_TH) {
1165         dev->ed_monitor_learning = false;
1166         dev->ed_trigger_timeout = jiffies + 20 * HZ;
1167     } else if (!dev->ed_monitor_learning &&
1168            time_is_after_jiffies(dev->ed_trigger_timeout)) {
1169         dev->ed_monitor_learning = true;
1170         mt76x02_edcca_tx_enable(dev, true);
1171     }
1172 
1173     if (dev->ed_monitor_learning)
1174         return;
1175 
1176     if (dev->ed_trigger > MT_EDCCA_BLOCK_TH && !dev->ed_tx_blocked)
1177         mt76x02_edcca_tx_enable(dev, false);
1178     else if (dev->ed_silent > MT_EDCCA_BLOCK_TH && dev->ed_tx_blocked)
1179         mt76x02_edcca_tx_enable(dev, true);
1180 }
1181 
1182 void mt76x02_mac_work(struct work_struct *work)
1183 {
1184     struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
1185                            mphy.mac_work.work);
1186     int i, idx;
1187 
1188     mutex_lock(&dev->mt76.mutex);
1189 
1190     mt76_update_survey(&dev->mphy);
1191     for (i = 0, idx = 0; i < 16; i++) {
1192         u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1193 
1194         dev->mt76.aggr_stats[idx++] += val & 0xffff;
1195         dev->mt76.aggr_stats[idx++] += val >> 16;
1196     }
1197 
1198     mt76x02_check_mac_err(dev);
1199 
1200     if (dev->ed_monitor)
1201         mt76x02_edcca_check(dev);
1202 
1203     mutex_unlock(&dev->mt76.mutex);
1204 
1205     mt76_tx_status_check(&dev->mt76, false);
1206 
1207     ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1208                      MT_MAC_WORK_INTERVAL);
1209 }
1210 
1211 void mt76x02_mac_cc_reset(struct mt76x02_dev *dev)
1212 {
1213     dev->mphy.survey_time = ktime_get_boottime();
1214 
1215     mt76_wr(dev, MT_CH_TIME_CFG,
1216         MT_CH_TIME_CFG_TIMER_EN |
1217         MT_CH_TIME_CFG_TX_AS_BUSY |
1218         MT_CH_TIME_CFG_RX_AS_BUSY |
1219         MT_CH_TIME_CFG_NAV_AS_BUSY |
1220         MT_CH_TIME_CFG_EIFS_AS_BUSY |
1221         MT_CH_CCA_RC_EN |
1222         FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
1223 
1224     /* channel cycle counters read-and-clear */
1225     mt76_rr(dev, MT_CH_BUSY);
1226     mt76_rr(dev, MT_CH_IDLE);
1227 }
1228 EXPORT_SYMBOL_GPL(mt76x02_mac_cc_reset);
1229 
1230 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr)
1231 {
1232     idx &= 7;
1233     mt76_wr(dev, MT_MAC_APC_BSSID_L(idx), get_unaligned_le32(addr));
1234     mt76_rmw_field(dev, MT_MAC_APC_BSSID_H(idx), MT_MAC_APC_BSSID_H_ADDR,
1235                get_unaligned_le16(addr + 4));
1236 }
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