mediatek/mt76/mt76x02_eeprom.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0005  */
0006
0007 #ifndef __MT76x02_EEPROM_H
0008 #define __MT76x02_EEPROM_H
0009
0010 #include "mt76x02.h"
0011
0012 enum mt76x02_eeprom_field {
0013     MT_EE_CHIP_ID =             0x000,
0014     MT_EE_VERSION =             0x002,
0015     MT_EE_MAC_ADDR =            0x004,
0016     MT_EE_PCI_ID =              0x00A,
0017     MT_EE_ANTENNA =             0x022,
0018     MT_EE_CFG1_INIT =           0x024,
0019     MT_EE_NIC_CONF_0 =          0x034,
0020     MT_EE_NIC_CONF_1 =          0x036,
0021     MT_EE_COUNTRY_REGION_5GHZ =     0x038,
0022     MT_EE_COUNTRY_REGION_2GHZ =     0x039,
0023     MT_EE_FREQ_OFFSET =         0x03a,
0024     MT_EE_NIC_CONF_2 =          0x042,
0025
0026     MT_EE_XTAL_TRIM_1 =         0x03a,
0027     MT_EE_XTAL_TRIM_2 =         0x09e,
0028
0029     MT_EE_LNA_GAIN =            0x044,
0030     MT_EE_RSSI_OFFSET_2G_0 =        0x046,
0031     MT_EE_RSSI_OFFSET_2G_1 =        0x048,
0032     MT_EE_LNA_GAIN_5GHZ_1 =         0x049,
0033     MT_EE_RSSI_OFFSET_5G_0 =        0x04a,
0034     MT_EE_RSSI_OFFSET_5G_1 =        0x04c,
0035     MT_EE_LNA_GAIN_5GHZ_2 =         0x04d,
0036
0037     MT_EE_TX_POWER_DELTA_BW40 =     0x050,
0038     MT_EE_TX_POWER_DELTA_BW80 =     0x052,
0039
0040     MT_EE_TX_POWER_EXT_PA_5G =      0x054,
0041
0042     MT_EE_TX_POWER_0_START_2G =     0x056,
0043     MT_EE_TX_POWER_1_START_2G =     0x05c,
0044
0045     /* used as byte arrays */
0046 #define MT_TX_POWER_GROUP_SIZE_5G       5
0047 #define MT_TX_POWER_GROUPS_5G           6
0048     MT_EE_TX_POWER_0_START_5G =     0x062,
0049     MT_EE_TSSI_SLOPE_2G =           0x06e,
0050
0051     MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA =  0x074,
0052     MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE =  0x076,
0053
0054     MT_EE_TX_POWER_1_START_5G =     0x080,
0055
0056     MT_EE_TX_POWER_CCK =            0x0a0,
0057     MT_EE_TX_POWER_OFDM_2G_6M =     0x0a2,
0058     MT_EE_TX_POWER_OFDM_2G_24M =        0x0a4,
0059     MT_EE_TX_POWER_OFDM_5G_6M =     0x0b2,
0060     MT_EE_TX_POWER_OFDM_5G_24M =        0x0b4,
0061     MT_EE_TX_POWER_HT_MCS0 =        0x0a6,
0062     MT_EE_TX_POWER_HT_MCS4 =        0x0a8,
0063     MT_EE_TX_POWER_HT_MCS8 =        0x0aa,
0064     MT_EE_TX_POWER_HT_MCS12 =       0x0ac,
0065     MT_EE_TX_POWER_VHT_MCS0 =       0x0ba,
0066     MT_EE_TX_POWER_VHT_MCS4 =       0x0bc,
0067     MT_EE_TX_POWER_VHT_MCS8 =       0x0be,
0068
0069     MT_EE_2G_TARGET_POWER =         0x0d0,
0070     MT_EE_TEMP_OFFSET =         0x0d1,
0071     MT_EE_5G_TARGET_POWER =         0x0d2,
0072     MT_EE_TSSI_BOUND1 =         0x0d4,
0073     MT_EE_TSSI_BOUND2 =         0x0d6,
0074     MT_EE_TSSI_BOUND3 =         0x0d8,
0075     MT_EE_TSSI_BOUND4 =         0x0da,
0076     MT_EE_FREQ_OFFSET_COMPENSATION =    0x0db,
0077     MT_EE_TSSI_BOUND5 =         0x0dc,
0078     MT_EE_TX_POWER_BYRATE_BASE =        0x0de,
0079
0080     MT_EE_TSSI_SLOPE_5G =           0x0f0,
0081     MT_EE_RF_TEMP_COMP_SLOPE_5G =       0x0f2,
0082     MT_EE_RF_TEMP_COMP_SLOPE_2G =       0x0f4,
0083
0084     MT_EE_RF_2G_TSSI_OFF_TXPOWER =      0x0f6,
0085     MT_EE_RF_2G_RX_HIGH_GAIN =      0x0f8,
0086     MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN =   0x0fa,
0087     MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN =   0x0fc,
0088     MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN =   0x0fe,
0089
0090     MT_EE_BT_RCAL_RESULT =          0x138,
0091     MT_EE_BT_VCDL_CALIBRATION =     0x13c,
0092     MT_EE_BT_PMUCFG =           0x13e,
0093
0094     MT_EE_USAGE_MAP_START =         0x1e0,
0095     MT_EE_USAGE_MAP_END =           0x1fc,
0096
0097     __MT_EE_MAX
0098 };
0099
0100 #define MT_EE_ANTENNA_DUAL          BIT(15)
0101
0102 #define MT_EE_NIC_CONF_0_RX_PATH        GENMASK(3, 0)
0103 #define MT_EE_NIC_CONF_0_TX_PATH        GENMASK(7, 4)
0104 #define MT_EE_NIC_CONF_0_PA_TYPE        GENMASK(9, 8)
0105 #define MT_EE_NIC_CONF_0_PA_INT_2G      BIT(8)
0106 #define MT_EE_NIC_CONF_0_PA_INT_5G      BIT(9)
0107 #define MT_EE_NIC_CONF_0_PA_IO_CURRENT      BIT(10)
0108 #define MT_EE_NIC_CONF_0_BOARD_TYPE     GENMASK(13, 12)
0109
0110 #define MT_EE_NIC_CONF_1_HW_RF_CTRL     BIT(0)
0111 #define MT_EE_NIC_CONF_1_TEMP_TX_ALC        BIT(1)
0112 #define MT_EE_NIC_CONF_1_LNA_EXT_2G     BIT(2)
0113 #define MT_EE_NIC_CONF_1_LNA_EXT_5G     BIT(3)
0114 #define MT_EE_NIC_CONF_1_TX_ALC_EN      BIT(13)
0115
0116 #define MT_EE_NIC_CONF_2_ANT_OPT        BIT(3)
0117 #define MT_EE_NIC_CONF_2_ANT_DIV        BIT(4)
0118 #define MT_EE_NIC_CONF_2_XTAL_OPTION        GENMASK(10, 9)
0119
0120 #define MT_EFUSE_USAGE_MAP_SIZE         (MT_EE_USAGE_MAP_END - \
0121                          MT_EE_USAGE_MAP_START + 1)
0122
0123 enum mt76x02_eeprom_modes {
0124     MT_EE_READ,
0125     MT_EE_PHYSICAL_READ,
0126 };
0127
0128 enum mt76x02_board_type {
0129     BOARD_TYPE_2GHZ = 1,
0130     BOARD_TYPE_5GHZ = 2,
0131 };
0132
0133 static inline bool mt76x02_field_valid(u8 val)
0134 {
0135     return val != 0 && val != 0xff;
0136 }
0137
0138 static inline int
0139 mt76x02_sign_extend(u32 val, unsigned int size)
0140 {
0141     bool sign = val & BIT(size - 1);
0142
0143     val &= BIT(size - 1) - 1;
0144
0145     return sign ? val : -val;
0146 }
0147
0148 static inline int
0149 mt76x02_sign_extend_optional(u32 val, unsigned int size)
0150 {
0151     bool enable = val & BIT(size);
0152
0153     return enable ? mt76x02_sign_extend(val, size) : 0;
0154 }
0155
0156 static inline s8 mt76x02_rate_power_val(u8 val)
0157 {
0158     if (!mt76x02_field_valid(val))
0159         return 0;
0160
0161     return mt76x02_sign_extend_optional(val, 7);
0162 }
0163
0164 static inline int
0165 mt76x02_eeprom_get(struct mt76x02_dev *dev,
0166            enum mt76x02_eeprom_field field)
0167 {
0168     if ((field & 1) || field >= __MT_EE_MAX)
0169         return -1;
0170
0171     return get_unaligned_le16(dev->mt76.eeprom.data + field);
0172 }
0173
0174 bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band);
0175 int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf,
0176                int len, enum mt76x02_eeprom_modes mode);
0177 void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band,
0178              u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g);
0179 u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev,
0180             s8 *lna_2g, s8 *lna_5g,
0181             struct ieee80211_channel *chan);
0182 void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev);
0183 int mt76x02_eeprom_copy(struct mt76x02_dev *dev,
0184             enum mt76x02_eeprom_field field,
0185             void *dest, int len);
0186
0187 #endif /* __MT76x02_EEPROM_H */