mediatek/mt76/mt76x02_dma.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005
0006 #ifndef __MT76x02_DMA_H
0007 #define __MT76x02_DMA_H
0008
0009 #include "mt76x02.h"
0010 #include "dma.h"
0011
0012 #define MT_TXD_INFO_LEN         GENMASK(15, 0)
0013 #define MT_TXD_INFO_NEXT_VLD        BIT(16)
0014 #define MT_TXD_INFO_TX_BURST        BIT(17)
0015 #define MT_TXD_INFO_80211       BIT(19)
0016 #define MT_TXD_INFO_TSO         BIT(20)
0017 #define MT_TXD_INFO_CSO         BIT(21)
0018 #define MT_TXD_INFO_WIV         BIT(24)
0019 #define MT_TXD_INFO_QSEL        GENMASK(26, 25)
0020 #define MT_TXD_INFO_DPORT       GENMASK(29, 27)
0021 #define MT_TXD_INFO_TYPE        GENMASK(31, 30)
0022
0023 #define MT_RX_FCE_INFO_LEN      GENMASK(13, 0)
0024 #define MT_RX_FCE_INFO_SELF_GEN     BIT(15)
0025 #define MT_RX_FCE_INFO_CMD_SEQ      GENMASK(19, 16)
0026 #define MT_RX_FCE_INFO_EVT_TYPE     GENMASK(23, 20)
0027 #define MT_RX_FCE_INFO_PCIE_INTR    BIT(24)
0028 #define MT_RX_FCE_INFO_QSEL     GENMASK(26, 25)
0029 #define MT_RX_FCE_INFO_D_PORT       GENMASK(29, 27)
0030 #define MT_RX_FCE_INFO_TYPE     GENMASK(31, 30)
0031
0032 /* MCU request message header  */
0033 #define MT_MCU_MSG_LEN          GENMASK(15, 0)
0034 #define MT_MCU_MSG_CMD_SEQ      GENMASK(19, 16)
0035 #define MT_MCU_MSG_CMD_TYPE     GENMASK(26, 20)
0036 #define MT_MCU_MSG_PORT         GENMASK(29, 27)
0037 #define MT_MCU_MSG_TYPE         GENMASK(31, 30)
0038 #define MT_MCU_MSG_TYPE_CMD     BIT(30)
0039
0040 #define MT_RX_HEADROOM          32
0041 #define MT76X02_RX_RING_SIZE        256
0042
0043 enum dma_msg_port {
0044     WLAN_PORT,
0045     CPU_RX_PORT,
0046     CPU_TX_PORT,
0047     HOST_PORT,
0048     VIRTUAL_CPU_RX_PORT,
0049     VIRTUAL_CPU_TX_PORT,
0050     DISCARD,
0051 };
0052
0053 static inline bool
0054 mt76x02_wait_for_wpdma(struct mt76_dev *dev, int timeout)
0055 {
0056     return __mt76_poll(dev, MT_WPDMA_GLO_CFG,
0057                MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0058                MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
0059                0, timeout);
0060 }
0061
0062 int mt76x02_dma_init(struct mt76x02_dev *dev);
0063 void mt76x02_dma_disable(struct mt76x02_dev *dev);
0064
0065 #endif /* __MT76x02_DMA_H */