mediatek/mt76/mt76x02_dfs.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
0004  */
0005
0006 #ifndef __MT76x02_DFS_H
0007 #define __MT76x02_DFS_H
0008
0009 #include <linux/types.h>
0010 #include <linux/nl80211.h>
0011
0012 #define MT_DFS_GP_INTERVAL      (10 << 4) /* 64 us unit */
0013 #define MT_DFS_NUM_ENGINES      4
0014
0015 /* bbp params */
0016 #define MT_DFS_SYM_ROUND        0
0017 #define MT_DFS_DELTA_DELAY      2
0018 #define MT_DFS_VGA_MASK         0
0019 #define MT_DFS_PWR_GAIN_OFFSET      3
0020 #define MT_DFS_PWR_DOWN_TIME        0xf
0021 #define MT_DFS_RX_PE_MASK       0xff
0022 #define MT_DFS_PKT_END_MASK     0
0023 #define MT_DFS_CH_EN            0xf
0024
0025 /* sw detector params */
0026 #define MT_DFS_EVENT_LOOP       64
0027 #define MT_DFS_SW_TIMEOUT       (HZ / 20)
0028 #define MT_DFS_EVENT_WINDOW     (HZ / 5)
0029 #define MT_DFS_SEQUENCE_WINDOW      (200 * (1 << 20))
0030 #define MT_DFS_EVENT_TIME_MARGIN    2000
0031 #define MT_DFS_PRI_MARGIN       4
0032 #define MT_DFS_SEQUENCE_TH      6
0033
0034 #define MT_DFS_FCC_MAX_PRI      ((28570 << 1) + 1000)
0035 #define MT_DFS_FCC_MIN_PRI      (3000 - 2)
0036 #define MT_DFS_JP_MAX_PRI       ((80000 << 1) + 1000)
0037 #define MT_DFS_JP_MIN_PRI       (28500 - 2)
0038 #define MT_DFS_ETSI_MAX_PRI     (133333 + 125000 + 117647 + 1000)
0039 #define MT_DFS_ETSI_MIN_PRI     (4500 - 20)
0040
0041 struct mt76x02_radar_specs {
0042     u8 mode;
0043     u16 avg_len;
0044     u16 e_low;
0045     u16 e_high;
0046     u16 w_low;
0047     u16 w_high;
0048     u16 w_margin;
0049     u32 t_low;
0050     u32 t_high;
0051     u16 t_margin;
0052     u32 b_low;
0053     u32 b_high;
0054     u32 event_expiration;
0055     u16 pwr_jmp;
0056 };
0057
0058 #define MT_DFS_CHECK_EVENT(x)       ((x) != GENMASK(31, 0))
0059 #define MT_DFS_EVENT_ENGINE(x)      (((x) & BIT(31)) ? 2 : 0)
0060 #define MT_DFS_EVENT_TIMESTAMP(x)   ((x) & GENMASK(21, 0))
0061 #define MT_DFS_EVENT_WIDTH(x)       ((x) & GENMASK(11, 0))
0062 struct mt76x02_dfs_event {
0063     unsigned long fetch_ts;
0064     u32 ts;
0065     u16 width;
0066     u8 engine;
0067 };
0068
0069 #define MT_DFS_EVENT_BUFLEN     256
0070 struct mt76x02_dfs_event_rb {
0071     struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN];
0072     int h_rb, t_rb;
0073 };
0074
0075 struct mt76x02_dfs_sequence {
0076     struct list_head head;
0077     u32 first_ts;
0078     u32 last_ts;
0079     u32 pri;
0080     u16 count;
0081     u8 engine;
0082 };
0083
0084 struct mt76x02_dfs_hw_pulse {
0085     u8 engine;
0086     u32 period;
0087     u32 w1;
0088     u32 w2;
0089     u32 burst;
0090 };
0091
0092 struct mt76x02_dfs_sw_detector_params {
0093     u32 min_pri;
0094     u32 max_pri;
0095     u32 pri_margin;
0096 };
0097
0098 struct mt76x02_dfs_engine_stats {
0099     u32 hw_pattern;
0100     u32 hw_pulse_discarded;
0101     u32 sw_pattern;
0102 };
0103
0104 struct mt76x02_dfs_seq_stats {
0105     u32 seq_pool_len;
0106     u32 seq_len;
0107 };
0108
0109 struct mt76x02_dfs_pattern_detector {
0110     u8 chirp_pulse_cnt;
0111     u32 chirp_pulse_ts;
0112
0113     struct mt76x02_dfs_sw_detector_params sw_dpd_params;
0114     struct mt76x02_dfs_event_rb event_rb[2];
0115
0116     struct list_head sequences;
0117     struct list_head seq_pool;
0118     struct mt76x02_dfs_seq_stats seq_stats;
0119
0120     unsigned long last_sw_check;
0121     u32 last_event_ts;
0122
0123     struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];
0124     struct tasklet_struct dfs_tasklet;
0125 };
0126
0127 void mt76x02_dfs_init_params(struct mt76x02_dev *dev);
0128 void mt76x02_dfs_init_detector(struct mt76x02_dev *dev);
0129 void mt76x02_regd_notifier(struct wiphy *wiphy,
0130                struct regulatory_request *request);
0131 void mt76x02_phy_dfs_adjust_agc(struct mt76x02_dev *dev);
0132 #endif /* __MT76x02_DFS_H */