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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * (c) Copyright 2002-2010, Ralink Technology, Inc.
0004  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0005  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0006  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/etherdevice.h>
0011 
0012 #include "mt76x0.h"
0013 #include "mcu.h"
0014 #include "eeprom.h"
0015 #include "phy.h"
0016 #include "initvals.h"
0017 #include "initvals_phy.h"
0018 #include "../mt76x02_phy.h"
0019 
0020 static int
0021 mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
0022 {
0023     int ret = 0;
0024     u8 bank, reg;
0025 
0026     if (test_bit(MT76_REMOVED, &dev->mphy.state))
0027         return -ENODEV;
0028 
0029     bank = MT_RF_BANK(offset);
0030     reg = MT_RF_REG(offset);
0031 
0032     if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))
0033         return -EINVAL;
0034 
0035     mutex_lock(&dev->phy_mutex);
0036 
0037     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) {
0038         ret = -ETIMEDOUT;
0039         goto out;
0040     }
0041 
0042     mt76_wr(dev, MT_RF_CSR_CFG,
0043         FIELD_PREP(MT_RF_CSR_CFG_DATA, value) |
0044         FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
0045         FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
0046         MT_RF_CSR_CFG_WR |
0047         MT_RF_CSR_CFG_KICK);
0048 
0049 out:
0050     mutex_unlock(&dev->phy_mutex);
0051 
0052     if (ret < 0)
0053         dev_err(dev->mt76.dev, "Error: RF write %d:%d failed:%d!!\n",
0054             bank, reg, ret);
0055 
0056     return ret;
0057 }
0058 
0059 static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
0060 {
0061     int ret = -ETIMEDOUT;
0062     u32 val;
0063     u8 bank, reg;
0064 
0065     if (test_bit(MT76_REMOVED, &dev->mphy.state))
0066         return -ENODEV;
0067 
0068     bank = MT_RF_BANK(offset);
0069     reg = MT_RF_REG(offset);
0070 
0071     if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))
0072         return -EINVAL;
0073 
0074     mutex_lock(&dev->phy_mutex);
0075 
0076     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
0077         goto out;
0078 
0079     mt76_wr(dev, MT_RF_CSR_CFG,
0080         FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) |
0081         FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) |
0082         MT_RF_CSR_CFG_KICK);
0083 
0084     if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100))
0085         goto out;
0086 
0087     val = mt76_rr(dev, MT_RF_CSR_CFG);
0088     if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == reg &&
0089         FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank)
0090         ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val);
0091 
0092 out:
0093     mutex_unlock(&dev->phy_mutex);
0094 
0095     if (ret < 0)
0096         dev_err(dev->mt76.dev, "Error: RF read %d:%d failed:%d!!\n",
0097             bank, reg, ret);
0098 
0099     return ret;
0100 }
0101 
0102 static int
0103 mt76x0_rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
0104 {
0105     if (mt76_is_usb(&dev->mt76)) {
0106         struct mt76_reg_pair pair = {
0107             .reg = offset,
0108             .value = val,
0109         };
0110 
0111         WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
0112                        &dev->mphy.state));
0113         return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
0114     } else {
0115         return mt76x0_rf_csr_wr(dev, offset, val);
0116     }
0117 }
0118 
0119 static int mt76x0_rf_rr(struct mt76x02_dev *dev, u32 offset)
0120 {
0121     int ret;
0122     u32 val;
0123 
0124     if (mt76_is_usb(&dev->mt76)) {
0125         struct mt76_reg_pair pair = {
0126             .reg = offset,
0127         };
0128 
0129         WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
0130                        &dev->mphy.state));
0131         ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
0132         val = pair.value;
0133     } else {
0134         ret = val = mt76x0_rf_csr_rr(dev, offset);
0135     }
0136 
0137     return (ret < 0) ? ret : val;
0138 }
0139 
0140 static int
0141 mt76x0_rf_rmw(struct mt76x02_dev *dev, u32 offset, u8 mask, u8 val)
0142 {
0143     int ret;
0144 
0145     ret = mt76x0_rf_rr(dev, offset);
0146     if (ret < 0)
0147         return ret;
0148 
0149     val |= ret & ~mask;
0150 
0151     ret = mt76x0_rf_wr(dev, offset, val);
0152     return ret ? ret : val;
0153 }
0154 
0155 static int
0156 mt76x0_rf_set(struct mt76x02_dev *dev, u32 offset, u8 val)
0157 {
0158     return mt76x0_rf_rmw(dev, offset, 0, val);
0159 }
0160 
0161 static int
0162 mt76x0_rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
0163 {
0164     return mt76x0_rf_rmw(dev, offset, mask, 0);
0165 }
0166 
0167 static void
0168 mt76x0_phy_rf_csr_wr_rp(struct mt76x02_dev *dev,
0169             const struct mt76_reg_pair *data,
0170             int n)
0171 {
0172     while (n-- > 0) {
0173         mt76x0_rf_csr_wr(dev, data->reg, data->value);
0174         data++;
0175     }
0176 }
0177 
0178 #define RF_RANDOM_WRITE(dev, tab) do {                  \
0179     if (mt76_is_mmio(&dev->mt76))                   \
0180         mt76x0_phy_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
0181     else                                \
0182         mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\
0183 } while (0)
0184 
0185 int mt76x0_phy_wait_bbp_ready(struct mt76x02_dev *dev)
0186 {
0187     int i = 20;
0188     u32 val;
0189 
0190     do {
0191         val = mt76_rr(dev, MT_BBP(CORE, 0));
0192         if (val && ~val)
0193             break;
0194     } while (--i);
0195 
0196     if (!i) {
0197         dev_err(dev->mt76.dev, "Error: BBP is not ready\n");
0198         return -EIO;
0199     }
0200 
0201     dev_dbg(dev->mt76.dev, "BBP version %08x\n", val);
0202     return 0;
0203 }
0204 
0205 static void
0206 mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
0207 {
0208     switch (band) {
0209     case NL80211_BAND_2GHZ:
0210         RF_RANDOM_WRITE(dev, mt76x0_rf_2g_channel_0_tab);
0211 
0212         mt76x0_rf_wr(dev, MT_RF(5, 0), 0x45);
0213         mt76x0_rf_wr(dev, MT_RF(6, 0), 0x44);
0214 
0215         mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007);
0216         mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002);
0217         break;
0218     case NL80211_BAND_5GHZ:
0219         RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab);
0220 
0221         mt76x0_rf_wr(dev, MT_RF(5, 0), 0x44);
0222         mt76x0_rf_wr(dev, MT_RF(6, 0), 0x45);
0223 
0224         mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005);
0225         mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102);
0226         break;
0227     default:
0228         break;
0229     }
0230 }
0231 
0232 static void
0233 mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel,
0234                   u16 rf_bw_band)
0235 {
0236     const struct mt76x0_freq_item *freq_item;
0237     u16 rf_band = rf_bw_band & 0xff00;
0238     u16 rf_bw = rf_bw_band & 0x00ff;
0239     enum nl80211_band band;
0240     bool b_sdm = false;
0241     u32 mac_reg;
0242     int i;
0243 
0244     for (i = 0; i < ARRAY_SIZE(mt76x0_sdm_channel); i++) {
0245         if (channel == mt76x0_sdm_channel[i]) {
0246             b_sdm = true;
0247             break;
0248         }
0249     }
0250 
0251     for (i = 0; i < ARRAY_SIZE(mt76x0_frequency_plan); i++) {
0252         if (channel == mt76x0_frequency_plan[i].channel) {
0253             rf_band = mt76x0_frequency_plan[i].band;
0254 
0255             if (b_sdm)
0256                 freq_item = &mt76x0_sdm_frequency_plan[i];
0257             else
0258                 freq_item = &mt76x0_frequency_plan[i];
0259 
0260             mt76x0_rf_wr(dev, MT_RF(0, 37), freq_item->pllR37);
0261             mt76x0_rf_wr(dev, MT_RF(0, 36), freq_item->pllR36);
0262             mt76x0_rf_wr(dev, MT_RF(0, 35), freq_item->pllR35);
0263             mt76x0_rf_wr(dev, MT_RF(0, 34), freq_item->pllR34);
0264             mt76x0_rf_wr(dev, MT_RF(0, 33), freq_item->pllR33);
0265 
0266             mt76x0_rf_rmw(dev, MT_RF(0, 32), 0xe0,
0267                       freq_item->pllR32_b7b5);
0268 
0269             /* R32<4:0> pll_den: (Denomina - 8) */
0270             mt76x0_rf_rmw(dev, MT_RF(0, 32), MT_RF_PLL_DEN_MASK,
0271                       freq_item->pllR32_b4b0);
0272 
0273             /* R31<7:5> */
0274             mt76x0_rf_rmw(dev, MT_RF(0, 31), 0xe0,
0275                       freq_item->pllR31_b7b5);
0276 
0277             /* R31<4:0> pll_k(Nominator) */
0278             mt76x0_rf_rmw(dev, MT_RF(0, 31), MT_RF_PLL_K_MASK,
0279                       freq_item->pllR31_b4b0);
0280 
0281             /* R30<7> sdm_reset_n */
0282             if (b_sdm) {
0283                 mt76x0_rf_clear(dev, MT_RF(0, 30),
0284                         MT_RF_SDM_RESET_MASK);
0285                 mt76x0_rf_set(dev, MT_RF(0, 30),
0286                           MT_RF_SDM_RESET_MASK);
0287             } else {
0288                 mt76x0_rf_rmw(dev, MT_RF(0, 30),
0289                           MT_RF_SDM_RESET_MASK,
0290                           freq_item->pllR30_b7);
0291             }
0292 
0293             /* R30<6:2> sdmmash_prbs,sin */
0294             mt76x0_rf_rmw(dev, MT_RF(0, 30),
0295                       MT_RF_SDM_MASH_PRBS_MASK,
0296                       freq_item->pllR30_b6b2);
0297 
0298             /* R30<1> sdm_bp */
0299             mt76x0_rf_rmw(dev, MT_RF(0, 30), MT_RF_SDM_BP_MASK,
0300                       freq_item->pllR30_b1 << 1);
0301 
0302             /* R30<0> R29<7:0> (hex) pll_n */
0303             mt76x0_rf_wr(dev, MT_RF(0, 29),
0304                      freq_item->pll_n & 0xff);
0305 
0306             mt76x0_rf_rmw(dev, MT_RF(0, 30), 0x1,
0307                       (freq_item->pll_n >> 8) & 0x1);
0308 
0309             /* R28<7:6> isi_iso */
0310             mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_ISI_ISO_MASK,
0311                       freq_item->pllR28_b7b6);
0312 
0313             /* R28<5:4> pfd_dly */
0314             mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_PFD_DLY_MASK,
0315                       freq_item->pllR28_b5b4);
0316 
0317             /* R28<3:2> clksel option */
0318             mt76x0_rf_rmw(dev, MT_RF(0, 28), MT_RF_CLK_SEL_MASK,
0319                       freq_item->pllR28_b3b2);
0320 
0321             /* R28<1:0> R27<7:0> R26<7:0> (hex) sdm_k */
0322             mt76x0_rf_wr(dev, MT_RF(0, 26),
0323                      freq_item->pll_sdm_k & 0xff);
0324             mt76x0_rf_wr(dev, MT_RF(0, 27),
0325                      (freq_item->pll_sdm_k >> 8) & 0xff);
0326 
0327             mt76x0_rf_rmw(dev, MT_RF(0, 28), 0x3,
0328                       (freq_item->pll_sdm_k >> 16) & 0x3);
0329 
0330             /* R24<1:0> xo_div */
0331             mt76x0_rf_rmw(dev, MT_RF(0, 24), MT_RF_XO_DIV_MASK,
0332                       freq_item->pllR24_b1b0);
0333 
0334             break;
0335         }
0336     }
0337 
0338     for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) {
0339         if (rf_bw == mt76x0_rf_bw_switch_tab[i].bw_band) {
0340             mt76x0_rf_wr(dev,
0341                      mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
0342                      mt76x0_rf_bw_switch_tab[i].value);
0343         } else if ((rf_bw == (mt76x0_rf_bw_switch_tab[i].bw_band & 0xFF)) &&
0344                (rf_band & mt76x0_rf_bw_switch_tab[i].bw_band)) {
0345             mt76x0_rf_wr(dev,
0346                      mt76x0_rf_bw_switch_tab[i].rf_bank_reg,
0347                      mt76x0_rf_bw_switch_tab[i].value);
0348         }
0349     }
0350 
0351     for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
0352         if (mt76x0_rf_band_switch_tab[i].bw_band & rf_band) {
0353             mt76x0_rf_wr(dev,
0354                      mt76x0_rf_band_switch_tab[i].rf_bank_reg,
0355                      mt76x0_rf_band_switch_tab[i].value);
0356         }
0357     }
0358 
0359     mt76_clear(dev, MT_RF_MISC, 0xc);
0360 
0361     band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
0362     if (mt76x02_ext_pa_enabled(dev, band)) {
0363         /* MT_RF_MISC (offset: 0x0518)
0364          * [2]1'b1: enable external A band PA
0365          *    1'b0: disable external A band PA
0366          * [3]1'b1: enable external G band PA
0367          *    1'b0: disable external G band PA
0368          */
0369         if (rf_band & RF_A_BAND)
0370             mt76_set(dev, MT_RF_MISC, BIT(2));
0371         else
0372             mt76_set(dev, MT_RF_MISC, BIT(3));
0373 
0374         /* External PA */
0375         for (i = 0; i < ARRAY_SIZE(mt76x0_rf_ext_pa_tab); i++)
0376             if (mt76x0_rf_ext_pa_tab[i].bw_band & rf_band)
0377                 mt76x0_rf_wr(dev,
0378                     mt76x0_rf_ext_pa_tab[i].rf_bank_reg,
0379                     mt76x0_rf_ext_pa_tab[i].value);
0380     }
0381 
0382     if (rf_band & RF_G_BAND) {
0383         mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x63707400);
0384         /* Set Atten mode = 2 For G band, Disable Tx Inc dcoc. */
0385         mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1);
0386         mac_reg &= 0x896400FF;
0387         mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg);
0388     } else {
0389         mt76_wr(dev, MT_TX0_RF_GAIN_ATTEN, 0x686A7800);
0390         /* Set Atten mode = 0
0391          * For Ext A band, Disable Tx Inc dcoc Cal.
0392          */
0393         mac_reg = mt76_rr(dev, MT_TX_ALC_CFG_1);
0394         mac_reg &= 0x890400FF;
0395         mt76_wr(dev, MT_TX_ALC_CFG_1, mac_reg);
0396     }
0397 }
0398 
0399 static void
0400 mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band)
0401 {
0402     int i;
0403 
0404     for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) {
0405         const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i];
0406         const struct mt76_reg_pair *pair = &item->reg_pair;
0407 
0408         if ((rf_bw_band & item->bw_band) != rf_bw_band)
0409             continue;
0410 
0411         if (pair->reg == MT_BBP(AGC, 8)) {
0412             u32 val = pair->value;
0413             u8 gain;
0414 
0415             gain = FIELD_GET(MT_BBP_AGC_GAIN, val);
0416             gain -= dev->cal.rx.lna_gain * 2;
0417             val &= ~MT_BBP_AGC_GAIN;
0418             val |= FIELD_PREP(MT_BBP_AGC_GAIN, gain);
0419             mt76_wr(dev, pair->reg, val);
0420         } else {
0421             mt76_wr(dev, pair->reg, pair->value);
0422         }
0423     }
0424 }
0425 
0426 static void mt76x0_phy_ant_select(struct mt76x02_dev *dev)
0427 {
0428     u16 ee_ant = mt76x02_eeprom_get(dev, MT_EE_ANTENNA);
0429     u16 ee_cfg1 = mt76x02_eeprom_get(dev, MT_EE_CFG1_INIT);
0430     u16 nic_conf2 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
0431     u32 wlan, coex3;
0432     bool ant_div;
0433 
0434     wlan = mt76_rr(dev, MT_WLAN_FUN_CTRL);
0435     coex3 = mt76_rr(dev, MT_COEXCFG3);
0436 
0437     ee_ant &= ~(BIT(14) | BIT(12));
0438     wlan  &= ~(BIT(6) | BIT(5));
0439     coex3 &= ~GENMASK(5, 2);
0440 
0441     if (ee_ant & MT_EE_ANTENNA_DUAL) {
0442         /* dual antenna mode */
0443         ant_div = !(nic_conf2 & MT_EE_NIC_CONF_2_ANT_OPT) &&
0444               (nic_conf2 & MT_EE_NIC_CONF_2_ANT_DIV);
0445         if (ant_div)
0446             ee_ant |= BIT(12);
0447         else
0448             coex3 |= BIT(4);
0449         coex3 |= BIT(3);
0450         if (dev->mphy.cap.has_2ghz)
0451             wlan |= BIT(6);
0452     } else {
0453         /* sigle antenna mode */
0454         if (dev->mphy.cap.has_5ghz) {
0455             coex3 |= BIT(3) | BIT(4);
0456         } else {
0457             wlan |= BIT(6);
0458             coex3 |= BIT(1);
0459         }
0460     }
0461 
0462     if (is_mt7630(dev))
0463         ee_ant |= BIT(14) | BIT(11);
0464 
0465     mt76_wr(dev, MT_WLAN_FUN_CTRL, wlan);
0466     mt76_rmw(dev, MT_CMB_CTRL, GENMASK(15, 0), ee_ant);
0467     mt76_rmw(dev, MT_CSR_EE_CFG1, GENMASK(15, 0), ee_cfg1);
0468     mt76_clear(dev, MT_COEXCFG0, BIT(2));
0469     mt76_wr(dev, MT_COEXCFG3, coex3);
0470 }
0471 
0472 static void
0473 mt76x0_phy_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
0474 {
0475     enum { BW_20 = 0, BW_40 = 1, BW_80 = 2, BW_10 = 4};
0476     int bw;
0477 
0478     switch (width) {
0479     default:
0480     case NL80211_CHAN_WIDTH_20_NOHT:
0481     case NL80211_CHAN_WIDTH_20:
0482         bw = BW_20;
0483         break;
0484     case NL80211_CHAN_WIDTH_40:
0485         bw = BW_40;
0486         break;
0487     case NL80211_CHAN_WIDTH_80:
0488         bw = BW_80;
0489         break;
0490     case NL80211_CHAN_WIDTH_10:
0491         bw = BW_10;
0492         break;
0493     case NL80211_CHAN_WIDTH_80P80:
0494     case NL80211_CHAN_WIDTH_160:
0495     case NL80211_CHAN_WIDTH_5:
0496         /* TODO error */
0497         return;
0498     }
0499 
0500     mt76x02_mcu_function_select(dev, BW_SETTING, bw);
0501 }
0502 
0503 static void mt76x0_phy_tssi_dc_calibrate(struct mt76x02_dev *dev)
0504 {
0505     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0506     u32 val;
0507 
0508     if (chan->band == NL80211_BAND_5GHZ)
0509         mt76x0_rf_clear(dev, MT_RF(0, 67), 0xf);
0510 
0511     /* bypass ADDA control */
0512     mt76_wr(dev, MT_RF_SETTING_0, 0x60002237);
0513     mt76_wr(dev, MT_RF_BYPASS_0, 0xffffffff);
0514 
0515     /* bbp sw reset */
0516     mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
0517     usleep_range(500, 1000);
0518     mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
0519 
0520     val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
0521     mt76_wr(dev, MT_BBP(CORE, 34), val);
0522 
0523     /* enable TX with DAC0 input */
0524     mt76_wr(dev, MT_BBP(TXBE, 6), BIT(31));
0525 
0526     mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200);
0527     dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
0528 
0529     /* stop bypass ADDA */
0530     mt76_wr(dev, MT_RF_BYPASS_0, 0);
0531     /* stop TX */
0532     mt76_wr(dev, MT_BBP(TXBE, 6), 0);
0533     /* bbp sw reset */
0534     mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
0535     usleep_range(500, 1000);
0536     mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
0537 
0538     if (chan->band == NL80211_BAND_5GHZ)
0539         mt76x0_rf_rmw(dev, MT_RF(0, 67), 0xf, 0x4);
0540 }
0541 
0542 static int
0543 mt76x0_phy_tssi_adc_calibrate(struct mt76x02_dev *dev, s16 *ltssi,
0544                   u8 *info)
0545 {
0546     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0547     u32 val;
0548 
0549     val = (chan->band == NL80211_BAND_5GHZ) ? 0x80055 : 0x80050;
0550     mt76_wr(dev, MT_BBP(CORE, 34), val);
0551 
0552     if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
0553         mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
0554         return -ETIMEDOUT;
0555     }
0556 
0557     *ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
0558     if (chan->band == NL80211_BAND_5GHZ)
0559         *ltssi += 128;
0560 
0561     /* set packet info#1 mode */
0562     mt76_wr(dev, MT_BBP(CORE, 34), 0x80041);
0563     info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
0564 
0565     /* set packet info#2 mode */
0566     mt76_wr(dev, MT_BBP(CORE, 34), 0x80042);
0567     info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
0568 
0569     /* set packet info#3 mode */
0570     mt76_wr(dev, MT_BBP(CORE, 34), 0x80043);
0571     info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
0572 
0573     return 0;
0574 }
0575 
0576 static u8 mt76x0_phy_get_rf_pa_mode(struct mt76x02_dev *dev,
0577                     int index, u8 tx_rate)
0578 {
0579     u32 val, reg;
0580 
0581     reg = (index == 1) ? MT_RF_PA_MODE_CFG1 : MT_RF_PA_MODE_CFG0;
0582     val = mt76_rr(dev, reg);
0583     return (val & (3 << (tx_rate * 2))) >> (tx_rate * 2);
0584 }
0585 
0586 static int
0587 mt76x0_phy_get_target_power(struct mt76x02_dev *dev, u8 tx_mode,
0588                 u8 *info, s8 *target_power,
0589                 s8 *target_pa_power)
0590 {
0591     u8 tx_rate, cur_power;
0592 
0593     cur_power = mt76_rr(dev, MT_TX_ALC_CFG_0) & MT_TX_ALC_CFG_0_CH_INIT_0;
0594     switch (tx_mode) {
0595     case 0:
0596         /* cck rates */
0597         tx_rate = (info[0] & 0x60) >> 5;
0598         if (tx_rate > 3)
0599             return -EINVAL;
0600 
0601         *target_power = cur_power + dev->mt76.rate_power.cck[tx_rate];
0602         *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, tx_rate);
0603         break;
0604     case 1: {
0605         u8 index;
0606 
0607         /* ofdm rates */
0608         tx_rate = (info[0] & 0xf0) >> 4;
0609         switch (tx_rate) {
0610         case 0xb:
0611             index = 0;
0612             break;
0613         case 0xf:
0614             index = 1;
0615             break;
0616         case 0xa:
0617             index = 2;
0618             break;
0619         case 0xe:
0620             index = 3;
0621             break;
0622         case 0x9:
0623             index = 4;
0624             break;
0625         case 0xd:
0626             index = 5;
0627             break;
0628         case 0x8:
0629             index = 6;
0630             break;
0631         case 0xc:
0632             index = 7;
0633             break;
0634         default:
0635             return -EINVAL;
0636         }
0637 
0638         *target_power = cur_power + dev->mt76.rate_power.ofdm[index];
0639         *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 0, index + 4);
0640         break;
0641     }
0642     case 4:
0643         /* vht rates */
0644         tx_rate = info[1] & 0xf;
0645         if (tx_rate > 9)
0646             return -EINVAL;
0647 
0648         *target_power = cur_power + dev->mt76.rate_power.vht[tx_rate];
0649         *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
0650         break;
0651     default:
0652         /* ht rates */
0653         tx_rate = info[1] & 0x7f;
0654         if (tx_rate > 9)
0655             return -EINVAL;
0656 
0657         *target_power = cur_power + dev->mt76.rate_power.ht[tx_rate];
0658         *target_pa_power = mt76x0_phy_get_rf_pa_mode(dev, 1, tx_rate);
0659         break;
0660     }
0661 
0662     return 0;
0663 }
0664 
0665 static s16 mt76x0_phy_lin2db(u16 val)
0666 {
0667     u32 mantissa = val << 4;
0668     int ret, data;
0669     s16 exp = -4;
0670 
0671     while (mantissa < BIT(15)) {
0672         mantissa <<= 1;
0673         if (--exp < -20)
0674             return -10000;
0675     }
0676     while (mantissa > 0xffff) {
0677         mantissa >>= 1;
0678         if (++exp > 20)
0679             return -10000;
0680     }
0681 
0682     /* s(15,0) */
0683     if (mantissa <= 47104)
0684         data = mantissa + (mantissa >> 3) + (mantissa >> 4) - 38400;
0685     else
0686         data = mantissa - (mantissa >> 3) - (mantissa >> 6) - 23040;
0687     data = max_t(int, 0, data);
0688 
0689     ret = ((15 + exp) << 15) + data;
0690     ret = (ret << 2) + (ret << 1) + (ret >> 6) + (ret >> 7);
0691     return ret >> 10;
0692 }
0693 
0694 static int
0695 mt76x0_phy_get_delta_power(struct mt76x02_dev *dev, u8 tx_mode,
0696                s8 target_power, s8 target_pa_power,
0697                s16 ltssi)
0698 {
0699     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0700     int tssi_target = target_power << 12, tssi_slope;
0701     int tssi_offset, tssi_db, ret;
0702     u32 data;
0703     u16 val;
0704 
0705     if (chan->band == NL80211_BAND_5GHZ) {
0706         u8 bound[7];
0707         int i, err;
0708 
0709         err = mt76x02_eeprom_copy(dev, MT_EE_TSSI_BOUND1, bound,
0710                       sizeof(bound));
0711         if (err < 0)
0712             return err;
0713 
0714         for (i = 0; i < ARRAY_SIZE(bound); i++) {
0715             if (chan->hw_value <= bound[i] || !bound[i])
0716                 break;
0717         }
0718         val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_5G + i * 2);
0719 
0720         tssi_offset = val >> 8;
0721         if ((tssi_offset >= 64 && tssi_offset <= 127) ||
0722             (tssi_offset & BIT(7)))
0723             tssi_offset -= BIT(8);
0724     } else {
0725         val = mt76x02_eeprom_get(dev, MT_EE_TSSI_SLOPE_2G);
0726 
0727         tssi_offset = val >> 8;
0728         if (tssi_offset & BIT(7))
0729             tssi_offset -= BIT(8);
0730     }
0731     tssi_slope = val & 0xff;
0732 
0733     switch (target_pa_power) {
0734     case 1:
0735         if (chan->band == NL80211_BAND_2GHZ)
0736             tssi_target += 29491; /* 3.6 * 8192 */
0737         fallthrough;
0738     case 0:
0739         break;
0740     default:
0741         tssi_target += 4424; /* 0.54 * 8192 */
0742         break;
0743     }
0744 
0745     if (!tx_mode) {
0746         data = mt76_rr(dev, MT_BBP(CORE, 1));
0747         if (is_mt7630(dev) && mt76_is_mmio(&dev->mt76)) {
0748             int offset;
0749 
0750             /* 2.3 * 8192 or 1.5 * 8192 */
0751             offset = (data & BIT(5)) ? 18841 : 12288;
0752             tssi_target += offset;
0753         } else if (data & BIT(5)) {
0754             /* 0.8 * 8192 */
0755             tssi_target += 6554;
0756         }
0757     }
0758 
0759     data = mt76_rr(dev, MT_BBP(TXBE, 4));
0760     switch (data & 0x3) {
0761     case 1:
0762         tssi_target -= 49152; /* -6db * 8192 */
0763         break;
0764     case 2:
0765         tssi_target -= 98304; /* -12db * 8192 */
0766         break;
0767     case 3:
0768         tssi_target += 49152; /* 6db * 8192 */
0769         break;
0770     default:
0771         break;
0772     }
0773 
0774     tssi_db = mt76x0_phy_lin2db(ltssi - dev->cal.tssi_dc) * tssi_slope;
0775     if (chan->band == NL80211_BAND_5GHZ) {
0776         tssi_db += ((tssi_offset - 50) << 10); /* offset s4.3 */
0777         tssi_target -= tssi_db;
0778         if (ltssi > 254 && tssi_target > 0) {
0779             /* upper saturate */
0780             tssi_target = 0;
0781         }
0782     } else {
0783         tssi_db += (tssi_offset << 9); /* offset s3.4 */
0784         tssi_target -= tssi_db;
0785         /* upper-lower saturate */
0786         if ((ltssi > 126 && tssi_target > 0) ||
0787             ((ltssi - dev->cal.tssi_dc) < 1 && tssi_target < 0)) {
0788             tssi_target = 0;
0789         }
0790     }
0791 
0792     if ((dev->cal.tssi_target ^ tssi_target) < 0 &&
0793         dev->cal.tssi_target > -4096 && dev->cal.tssi_target < 4096 &&
0794         tssi_target > -4096 && tssi_target < 4096) {
0795         if ((tssi_target < 0 &&
0796              tssi_target + dev->cal.tssi_target > 0) ||
0797             (tssi_target > 0 &&
0798              tssi_target + dev->cal.tssi_target <= 0))
0799             tssi_target = 0;
0800         else
0801             dev->cal.tssi_target = tssi_target;
0802     } else {
0803         dev->cal.tssi_target = tssi_target;
0804     }
0805 
0806     /* make the compensate value to the nearest compensate code */
0807     if (tssi_target > 0)
0808         tssi_target += 2048;
0809     else
0810         tssi_target -= 2048;
0811     tssi_target >>= 12;
0812 
0813     ret = mt76_get_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP);
0814     if (ret & BIT(5))
0815         ret -= BIT(6);
0816     ret += tssi_target;
0817 
0818     ret = min_t(int, 31, ret);
0819     return max_t(int, -32, ret);
0820 }
0821 
0822 static void mt76x0_phy_tssi_calibrate(struct mt76x02_dev *dev)
0823 {
0824     s8 target_power, target_pa_power;
0825     u8 tssi_info[3], tx_mode;
0826     s16 ltssi;
0827     s8 val;
0828 
0829     if (mt76x0_phy_tssi_adc_calibrate(dev, &ltssi, tssi_info) < 0)
0830         return;
0831 
0832     tx_mode = tssi_info[0] & 0x7;
0833     if (mt76x0_phy_get_target_power(dev, tx_mode, tssi_info,
0834                     &target_power, &target_pa_power) < 0)
0835         return;
0836 
0837     val = mt76x0_phy_get_delta_power(dev, tx_mode, target_power,
0838                      target_pa_power, ltssi);
0839     mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, val);
0840 }
0841 
0842 void mt76x0_phy_set_txpower(struct mt76x02_dev *dev)
0843 {
0844     struct mt76_rate_power *t = &dev->mt76.rate_power;
0845     s8 info;
0846 
0847     mt76x0_get_tx_power_per_rate(dev, dev->mphy.chandef.chan, t);
0848     mt76x0_get_power_info(dev, dev->mphy.chandef.chan, &info);
0849 
0850     mt76x02_add_rate_power_offset(t, info);
0851     mt76x02_limit_rate_power(t, dev->txpower_conf);
0852     dev->mphy.txpower_cur = mt76x02_get_max_rate_power(t);
0853     mt76x02_add_rate_power_offset(t, -info);
0854 
0855     dev->target_power = info;
0856     mt76x02_phy_set_txpower(dev, info, info);
0857 }
0858 
0859 void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on)
0860 {
0861     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0862     int is_5ghz = (chan->band == NL80211_BAND_5GHZ) ? 1 : 0;
0863     u32 val, tx_alc, reg_val;
0864 
0865     if (is_mt7630(dev))
0866         return;
0867 
0868     if (power_on) {
0869         mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0);
0870         mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value);
0871         usleep_range(10, 20);
0872 
0873         if (mt76x0_tssi_enabled(dev)) {
0874             mt76_wr(dev, MT_MAC_SYS_CTRL,
0875                 MT_MAC_SYS_CTRL_ENABLE_RX);
0876             mt76x0_phy_tssi_dc_calibrate(dev);
0877             mt76_wr(dev, MT_MAC_SYS_CTRL,
0878                 MT_MAC_SYS_CTRL_ENABLE_TX |
0879                 MT_MAC_SYS_CTRL_ENABLE_RX);
0880         }
0881     }
0882 
0883     tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
0884     mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
0885     usleep_range(500, 700);
0886 
0887     reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
0888     mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
0889 
0890     if (is_5ghz) {
0891         if (chan->hw_value < 100)
0892             val = 0x701;
0893         else if (chan->hw_value < 140)
0894             val = 0x801;
0895         else
0896             val = 0x901;
0897     } else {
0898         val = 0x600;
0899     }
0900 
0901     mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val);
0902     mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz);
0903     usleep_range(15000, 20000);
0904 
0905     mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
0906     mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
0907     mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1);
0908 }
0909 EXPORT_SYMBOL_GPL(mt76x0_phy_calibrate);
0910 
0911 void mt76x0_phy_set_channel(struct mt76x02_dev *dev,
0912                 struct cfg80211_chan_def *chandef)
0913 {
0914     u32 ext_cca_chan[4] = {
0915         [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) |
0916               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) |
0917               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
0918               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
0919               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)),
0920         [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) |
0921               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) |
0922               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) |
0923               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) |
0924               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)),
0925         [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) |
0926               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) |
0927               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
0928               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
0929               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(2)),
0930         [3] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 3) |
0931               FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 2) |
0932               FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 1) |
0933               FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 0) |
0934               FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(3)),
0935     };
0936     bool scan = test_bit(MT76_SCANNING, &dev->mphy.state);
0937     int ch_group_index, freq, freq1;
0938     u8 channel;
0939     u32 val;
0940     u16 rf_bw_band;
0941 
0942     freq = chandef->chan->center_freq;
0943     freq1 = chandef->center_freq1;
0944     channel = chandef->chan->hw_value;
0945     rf_bw_band = (channel <= 14) ? RF_G_BAND : RF_A_BAND;
0946 
0947     switch (chandef->width) {
0948     case NL80211_CHAN_WIDTH_40:
0949         if (freq1 > freq)
0950             ch_group_index = 0;
0951         else
0952             ch_group_index = 1;
0953         channel += 2 - ch_group_index * 4;
0954         rf_bw_band |= RF_BW_40;
0955         break;
0956     case NL80211_CHAN_WIDTH_80:
0957         ch_group_index = (freq - freq1 + 30) / 20;
0958         if (WARN_ON(ch_group_index < 0 || ch_group_index > 3))
0959             ch_group_index = 0;
0960         channel += 6 - ch_group_index * 4;
0961         rf_bw_band |= RF_BW_80;
0962         break;
0963     default:
0964         ch_group_index = 0;
0965         rf_bw_band |= RF_BW_20;
0966         break;
0967     }
0968 
0969     if (mt76_is_usb(&dev->mt76)) {
0970         mt76x0_phy_bbp_set_bw(dev, chandef->width);
0971     } else {
0972         if (chandef->width == NL80211_CHAN_WIDTH_80 ||
0973             chandef->width == NL80211_CHAN_WIDTH_40)
0974             val = 0x201;
0975         else
0976             val = 0x601;
0977         mt76_wr(dev, MT_TX_SW_CFG0, val);
0978     }
0979     mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
0980     mt76x02_phy_set_band(dev, chandef->chan->band,
0981                  ch_group_index & 1);
0982 
0983     mt76_rmw(dev, MT_EXT_CCA_CFG,
0984          (MT_EXT_CCA_CFG_CCA0 |
0985           MT_EXT_CCA_CFG_CCA1 |
0986           MT_EXT_CCA_CFG_CCA2 |
0987           MT_EXT_CCA_CFG_CCA3 |
0988           MT_EXT_CCA_CFG_CCA_MASK),
0989          ext_cca_chan[ch_group_index]);
0990 
0991     mt76x0_phy_set_band(dev, chandef->chan->band);
0992     mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
0993 
0994     /* set Japan Tx filter at channel 14 */
0995     if (channel == 14)
0996         mt76_set(dev, MT_BBP(CORE, 1), 0x20);
0997     else
0998         mt76_clear(dev, MT_BBP(CORE, 1), 0x20);
0999 
1000     mt76x0_read_rx_gain(dev);
1001     mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band);
1002 
1003     /* enable vco */
1004     mt76x0_rf_set(dev, MT_RF(0, 4), BIT(7));
1005     if (scan)
1006         return;
1007 
1008     mt76x02_init_agc_gain(dev);
1009     mt76x0_phy_calibrate(dev, false);
1010     mt76x0_phy_set_txpower(dev);
1011 
1012     ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
1013                      MT_CALIBRATE_INTERVAL);
1014 }
1015 
1016 static void mt76x0_phy_temp_sensor(struct mt76x02_dev *dev)
1017 {
1018     u8 rf_b7_73, rf_b0_66, rf_b0_67;
1019     s8 val;
1020 
1021     rf_b7_73 = mt76x0_rf_rr(dev, MT_RF(7, 73));
1022     rf_b0_66 = mt76x0_rf_rr(dev, MT_RF(0, 66));
1023     rf_b0_67 = mt76x0_rf_rr(dev, MT_RF(0, 67));
1024 
1025     mt76x0_rf_wr(dev, MT_RF(7, 73), 0x02);
1026     mt76x0_rf_wr(dev, MT_RF(0, 66), 0x23);
1027     mt76x0_rf_wr(dev, MT_RF(0, 67), 0x01);
1028 
1029     mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
1030     if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
1031         mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
1032         goto done;
1033     }
1034 
1035     val = mt76_rr(dev, MT_BBP(CORE, 35));
1036     val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25;
1037 
1038     if (abs(val - dev->cal.temp_vco) > 20) {
1039         mt76x02_mcu_calibrate(dev, MCU_CAL_VCO,
1040                       dev->mphy.chandef.chan->hw_value);
1041         dev->cal.temp_vco = val;
1042     }
1043     if (abs(val - dev->cal.temp) > 30) {
1044         mt76x0_phy_calibrate(dev, false);
1045         dev->cal.temp = val;
1046     }
1047 
1048 done:
1049     mt76x0_rf_wr(dev, MT_RF(7, 73), rf_b7_73);
1050     mt76x0_rf_wr(dev, MT_RF(0, 66), rf_b0_66);
1051     mt76x0_rf_wr(dev, MT_RF(0, 67), rf_b0_67);
1052 }
1053 
1054 static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev)
1055 {
1056     u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
1057 
1058     mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, gain);
1059 
1060     if ((dev->mphy.chandef.chan->flags & IEEE80211_CHAN_RADAR) &&
1061         !is_mt7630(dev))
1062         mt76x02_phy_dfs_adjust_agc(dev);
1063 }
1064 
1065 static void
1066 mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev)
1067 {
1068     bool gain_change;
1069     u8 gain_delta;
1070     int low_gain;
1071 
1072     dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76, false);
1073     if (!dev->cal.avg_rssi_all)
1074         dev->cal.avg_rssi_all = -75;
1075 
1076     low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
1077         (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));
1078 
1079     gain_change = dev->cal.low_gain < 0 ||
1080               (dev->cal.low_gain & 2) ^ (low_gain & 2);
1081     dev->cal.low_gain = low_gain;
1082 
1083     if (!gain_change) {
1084         if (mt76x02_phy_adjust_vga_gain(dev))
1085             mt76x0_phy_set_gain_val(dev);
1086         return;
1087     }
1088 
1089     dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10;
1090     gain_delta = (low_gain == 2) ? 10 : 0;
1091 
1092     dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta;
1093     mt76x0_phy_set_gain_val(dev);
1094 
1095     /* clear false CCA counters */
1096     mt76_rr(dev, MT_RX_STAT_1);
1097 }
1098 
1099 static void mt76x0_phy_calibration_work(struct work_struct *work)
1100 {
1101     struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
1102                            cal_work.work);
1103 
1104     mt76x0_phy_update_channel_gain(dev);
1105     if (mt76x0_tssi_enabled(dev))
1106         mt76x0_phy_tssi_calibrate(dev);
1107     else
1108         mt76x0_phy_temp_sensor(dev);
1109 
1110     ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
1111                      4 * MT_CALIBRATE_INTERVAL);
1112 }
1113 
1114 static void mt76x0_rf_patch_reg_array(struct mt76x02_dev *dev,
1115                       const struct mt76_reg_pair *rp, int len)
1116 {
1117     int i;
1118 
1119     for (i = 0; i < len; i++) {
1120         u32 reg = rp[i].reg;
1121         u8 val = rp[i].value;
1122 
1123         switch (reg) {
1124         case MT_RF(0, 3):
1125             if (mt76_is_mmio(&dev->mt76)) {
1126                 if (is_mt7630(dev))
1127                     val = 0x70;
1128                 else
1129                     val = 0x63;
1130             } else {
1131                 val = 0x73;
1132             }
1133             break;
1134         case MT_RF(0, 21):
1135             if (is_mt7610e(dev))
1136                 val = 0x10;
1137             else
1138                 val = 0x12;
1139             break;
1140         case MT_RF(5, 2):
1141             if (is_mt7630(dev))
1142                 val = 0x1d;
1143             else if (is_mt7610e(dev))
1144                 val = 0x00;
1145             else
1146                 val = 0x0c;
1147             break;
1148         default:
1149             break;
1150         }
1151         mt76x0_rf_wr(dev, reg, val);
1152     }
1153 }
1154 
1155 static void mt76x0_phy_rf_init(struct mt76x02_dev *dev)
1156 {
1157     int i;
1158 
1159     mt76x0_rf_patch_reg_array(dev, mt76x0_rf_central_tab,
1160                   ARRAY_SIZE(mt76x0_rf_central_tab));
1161     mt76x0_rf_patch_reg_array(dev, mt76x0_rf_2g_channel_0_tab,
1162                   ARRAY_SIZE(mt76x0_rf_2g_channel_0_tab));
1163     RF_RANDOM_WRITE(dev, mt76x0_rf_5g_channel_0_tab);
1164     RF_RANDOM_WRITE(dev, mt76x0_rf_vga_channel_0_tab);
1165 
1166     for (i = 0; i < ARRAY_SIZE(mt76x0_rf_bw_switch_tab); i++) {
1167         const struct mt76x0_rf_switch_item *item = &mt76x0_rf_bw_switch_tab[i];
1168 
1169         if (item->bw_band == RF_BW_20)
1170             mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
1171         else if (((RF_G_BAND | RF_BW_20) & item->bw_band) ==
1172               (RF_G_BAND | RF_BW_20))
1173             mt76x0_rf_wr(dev, item->rf_bank_reg, item->value);
1174     }
1175 
1176     for (i = 0; i < ARRAY_SIZE(mt76x0_rf_band_switch_tab); i++) {
1177         if (mt76x0_rf_band_switch_tab[i].bw_band & RF_G_BAND) {
1178             mt76x0_rf_wr(dev,
1179                      mt76x0_rf_band_switch_tab[i].rf_bank_reg,
1180                      mt76x0_rf_band_switch_tab[i].value);
1181         }
1182     }
1183 
1184     /* Frequency calibration
1185      * E1: B0.R22<6:0>: xo_cxo<6:0>
1186      * E2: B0.R21<0>: xo_cxo<0>, B0.R22<7:0>: xo_cxo<8:1>
1187      */
1188     mt76x0_rf_wr(dev, MT_RF(0, 22),
1189              min_t(u8, dev->cal.rx.freq_offset, 0xbf));
1190     mt76x0_rf_rr(dev, MT_RF(0, 22));
1191 
1192     /* Reset procedure DAC during power-up:
1193      * - set B0.R73<7>
1194      * - clear B0.R73<7>
1195      * - set B0.R73<7>
1196      */
1197     mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
1198     mt76x0_rf_clear(dev, MT_RF(0, 73), BIT(7));
1199     mt76x0_rf_set(dev, MT_RF(0, 73), BIT(7));
1200 
1201     /* vcocal_en: initiate VCO calibration (reset after completion)) */
1202     mt76x0_rf_set(dev, MT_RF(0, 4), 0x80);
1203 }
1204 
1205 void mt76x0_phy_init(struct mt76x02_dev *dev)
1206 {
1207     INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work);
1208 
1209     mt76x0_phy_ant_select(dev);
1210     mt76x0_phy_rf_init(dev);
1211     mt76x02_phy_set_rxpath(dev);
1212     mt76x02_phy_set_txdac(dev);
1213 }
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