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0009 #ifndef __MT76X0U_INITVALS_INIT_H
0010 #define __MT76X0U_INITVALS_INIT_H
0011
0012 #include "phy.h"
0013
0014 static const struct mt76_reg_pair common_mac_reg_table[] = {
0015 { MT_BCN_OFFSET(0), 0xf8f0e8e0 },
0016 { MT_BCN_OFFSET(1), 0x6f77d0c8 },
0017 { MT_LEGACY_BASIC_RATE, 0x0000013f },
0018 { MT_HT_BASIC_RATE, 0x00008003 },
0019 { MT_MAC_SYS_CTRL, 0x00000000 },
0020 { MT_RX_FILTR_CFG, 0x00017f97 },
0021 { MT_BKOFF_SLOT_CFG, 0x00000209 },
0022 { MT_TX_SW_CFG0, 0x00000000 },
0023 { MT_TX_SW_CFG1, 0x00080606 },
0024 { MT_TX_LINK_CFG, 0x00001020 },
0025 { MT_TX_TIMEOUT_CFG, 0x000a2090 },
0026 { MT_MAX_LEN_CFG, 0xa0fff | 0x00001000 },
0027 { MT_LED_CFG, 0x7f031e46 },
0028 { MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f },
0029 { MT_PBF_RX_MAX_PCNT, 0x0000fe9f },
0030 { MT_TX_RETRY_CFG, 0x47d01f0f },
0031 { MT_AUTO_RSP_CFG, 0x00000013 },
0032 { MT_CCK_PROT_CFG, 0x07f40003 },
0033 { MT_OFDM_PROT_CFG, 0x07f42004 },
0034 { MT_PBF_CFG, 0x00f40006 },
0035 { MT_WPDMA_GLO_CFG, 0x00000030 },
0036 { MT_GF20_PROT_CFG, 0x01742004 },
0037 { MT_GF40_PROT_CFG, 0x03f42084 },
0038 { MT_MM20_PROT_CFG, 0x01742004 },
0039 { MT_MM40_PROT_CFG, 0x03f42084 },
0040 { MT_TXOP_CTRL_CFG, 0x0000583f },
0041 { MT_TX_RTS_CFG, 0x00ffff20 },
0042 { MT_EXP_ACK_TIME, 0x002400ca },
0043 { MT_TXOP_HLDR_ET, 0x00000002 },
0044 { MT_XIFS_TIME_CFG, 0x33a41010 },
0045 { MT_PWR_PIN_CFG, 0x00000000 },
0046 };
0047
0048 static const struct mt76_reg_pair mt76x0_mac_reg_table[] = {
0049 { MT_IOCFG_6, 0xa0040080 },
0050 { MT_PBF_SYS_CTRL, 0x00080c00 },
0051 { MT_PBF_CFG, 0x77723c1f },
0052 { MT_FCE_PSE_CTRL, 0x00000001 },
0053 { MT_AMPDU_MAX_LEN_20M1S, 0xAAA99887 },
0054 { MT_TX_SW_CFG0, 0x00000601 },
0055 { MT_TX_SW_CFG1, 0x00040000 },
0056 { MT_TX_SW_CFG2, 0x00000000 },
0057 { 0xa44, 0x00000000 },
0058 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
0059 { MT_TSO_CTRL, 0x00000000 },
0060 { MT_BB_PA_MODE_CFG1, 0x00500055 },
0061 { MT_RF_PA_MODE_CFG1, 0x00500055 },
0062 { MT_TX_ALC_CFG_0, 0x2F2F000C },
0063 { MT_TX0_BB_GAIN_ATTEN, 0x00000000 },
0064 { MT_TX_PWR_CFG_0, 0x3A3A3A3A },
0065 { MT_TX_PWR_CFG_1, 0x3A3A3A3A },
0066 { MT_TX_PWR_CFG_2, 0x3A3A3A3A },
0067 { MT_TX_PWR_CFG_3, 0x3A3A3A3A },
0068 { MT_TX_PWR_CFG_4, 0x3A3A3A3A },
0069 { MT_TX_PWR_CFG_7, 0x3A3A3A3A },
0070 { MT_TX_PWR_CFG_8, 0x0000003A },
0071 { MT_TX_PWR_CFG_9, 0x0000003A },
0072 { 0x150C, 0x00000002 },
0073 { 0x1238, 0x001700C8 },
0074 { MT_LDO_CTRL_0, 0x00A647B6 },
0075 { MT_LDO_CTRL_1, 0x6B006464 },
0076 { MT_HT_BASIC_RATE, 0x00004003 },
0077 { MT_HT_CTRL_CFG, 0x000001FF },
0078 { MT_TXOP_HLDR_ET, 0x00000000 },
0079 { MT_PN_PAD_MODE, 0x00000003 },
0080 { MT_TX_PROT_CFG6, 0xe3f42004 },
0081 { MT_TX_PROT_CFG7, 0xe3f42084 },
0082 { MT_TX_PROT_CFG8, 0xe3f42104 },
0083 { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
0084 };
0085
0086 static const struct mt76_reg_pair mt76x0_bbp_init_tab[] = {
0087 { MT_BBP(CORE, 1), 0x00000002 },
0088 { MT_BBP(CORE, 4), 0x00000000 },
0089 { MT_BBP(CORE, 24), 0x00000000 },
0090 { MT_BBP(CORE, 32), 0x4003000a },
0091 { MT_BBP(CORE, 42), 0x00000000 },
0092 { MT_BBP(CORE, 44), 0x00000000 },
0093 { MT_BBP(IBI, 11), 0x0FDE8081 },
0094 { MT_BBP(AGC, 0), 0x00021400 },
0095 { MT_BBP(AGC, 1), 0x00000003 },
0096 { MT_BBP(AGC, 2), 0x003A6464 },
0097 { MT_BBP(AGC, 15), 0x88A28CB8 },
0098 { MT_BBP(AGC, 22), 0x00001E21 },
0099 { MT_BBP(AGC, 23), 0x0000272C },
0100 { MT_BBP(AGC, 24), 0x00002F3A },
0101 { MT_BBP(AGC, 25), 0x8000005A },
0102 { MT_BBP(AGC, 26), 0x007C2005 },
0103 { MT_BBP(AGC, 33), 0x00003238 },
0104 { MT_BBP(AGC, 34), 0x000A0C0C },
0105 { MT_BBP(AGC, 37), 0x2121262C },
0106 { MT_BBP(AGC, 41), 0x38383E45 },
0107 { MT_BBP(AGC, 57), 0x00001010 },
0108 { MT_BBP(AGC, 59), 0xBAA20E96 },
0109 { MT_BBP(AGC, 63), 0x00000001 },
0110 { MT_BBP(TXC, 0), 0x00280403 },
0111 { MT_BBP(TXC, 1), 0x00000000 },
0112 { MT_BBP(RXC, 1), 0x00000012 },
0113 { MT_BBP(RXC, 2), 0x00000011 },
0114 { MT_BBP(RXC, 3), 0x00000005 },
0115 { MT_BBP(RXC, 4), 0x00000000 },
0116 { MT_BBP(RXC, 5), 0xF977C4EC },
0117 { MT_BBP(RXC, 7), 0x00000090 },
0118 { MT_BBP(TXO, 8), 0x00000000 },
0119 { MT_BBP(TXBE, 0), 0x00000000 },
0120 { MT_BBP(TXBE, 4), 0x00000004 },
0121 { MT_BBP(TXBE, 6), 0x00000000 },
0122 { MT_BBP(TXBE, 8), 0x00000014 },
0123 { MT_BBP(TXBE, 9), 0x20000000 },
0124 { MT_BBP(TXBE, 10), 0x00000000 },
0125 { MT_BBP(TXBE, 12), 0x00000000 },
0126 { MT_BBP(TXBE, 13), 0x00000000 },
0127 { MT_BBP(TXBE, 14), 0x00000000 },
0128 { MT_BBP(TXBE, 15), 0x00000000 },
0129 { MT_BBP(TXBE, 16), 0x00000000 },
0130 { MT_BBP(TXBE, 17), 0x00000000 },
0131 { MT_BBP(RXFE, 1), 0x00008800 },
0132 { MT_BBP(RXFE, 3), 0x00000000 },
0133 { MT_BBP(RXFE, 4), 0x00000000 },
0134 { MT_BBP(RXO, 13), 0x00000192 },
0135 { MT_BBP(RXO, 14), 0x00060612 },
0136 { MT_BBP(RXO, 15), 0xC8321B18 },
0137 { MT_BBP(RXO, 16), 0x0000001E },
0138 { MT_BBP(RXO, 17), 0x00000000 },
0139 { MT_BBP(RXO, 18), 0xCC00A993 },
0140 { MT_BBP(RXO, 19), 0xB9CB9CB9 },
0141 { MT_BBP(RXO, 20), 0x26c00057 },
0142 { MT_BBP(RXO, 21), 0x00000001 },
0143 { MT_BBP(RXO, 24), 0x00000006 },
0144 { MT_BBP(RXO, 28), 0x0000003F },
0145 };
0146
0147 static const struct mt76_reg_pair mt76x0_dcoc_tab[] = {
0148 { MT_BBP(CAL, 47), 0x000010F0 },
0149 { MT_BBP(CAL, 48), 0x00008080 },
0150 { MT_BBP(CAL, 49), 0x00000F07 },
0151 { MT_BBP(CAL, 50), 0x00000040 },
0152 { MT_BBP(CAL, 51), 0x00000404 },
0153 { MT_BBP(CAL, 52), 0x00080803 },
0154 { MT_BBP(CAL, 53), 0x00000704 },
0155 { MT_BBP(CAL, 54), 0x00002828 },
0156 { MT_BBP(CAL, 55), 0x00005050 },
0157 };
0158
0159 #endif
