mt76/mt76x0/eeprom.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
0004  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
0005  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/of.h>
0010 #include <linux/mtd/mtd.h>
0011 #include <linux/mtd/partitions.h>
0012 #include <linux/etherdevice.h>
0013 #include <asm/unaligned.h>
0014 #include "mt76x0.h"
0015 #include "eeprom.h"
0016 #include "../mt76x02_phy.h"
0017
0018 #define MT_MAP_READS    DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16)
0019 static int
0020 mt76x0_efuse_physical_size_check(struct mt76x02_dev *dev)
0021 {
0022     u8 data[MT_MAP_READS * 16];
0023     int ret, i;
0024     u32 start = 0, end = 0, cnt_free;
0025
0026     ret = mt76x02_get_efuse_data(dev, MT_EE_USAGE_MAP_START, data,
0027                      sizeof(data), MT_EE_PHYSICAL_READ);
0028     if (ret)
0029         return ret;
0030
0031     for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++)
0032         if (!data[i]) {
0033             if (!start)
0034                 start = MT_EE_USAGE_MAP_START + i;
0035             end = MT_EE_USAGE_MAP_START + i;
0036         }
0037     cnt_free = end - start + 1;
0038
0039     if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) {
0040         dev_err(dev->mt76.dev,
0041             "driver does not support default EEPROM\n");
0042         return -EINVAL;
0043     }
0044
0045     return 0;
0046 }
0047
0048 static void mt76x0_set_chip_cap(struct mt76x02_dev *dev)
0049 {
0050     u16 nic_conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
0051     u16 nic_conf1 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
0052
0053     mt76x02_eeprom_parse_hw_cap(dev);
0054     dev_dbg(dev->mt76.dev, "2GHz %d 5GHz %d\n",
0055         dev->mphy.cap.has_2ghz, dev->mphy.cap.has_5ghz);
0056
0057     if (dev->no_2ghz) {
0058         dev->mphy.cap.has_2ghz = false;
0059         dev_dbg(dev->mt76.dev, "mask out 2GHz support\n");
0060     }
0061
0062     if (is_mt7630(dev)) {
0063         dev->mphy.cap.has_5ghz = false;
0064         dev_dbg(dev->mt76.dev, "mask out 5GHz support\n");
0065     }
0066
0067     if (!mt76x02_field_valid(nic_conf1 & 0xff))
0068         nic_conf1 &= 0xff00;
0069
0070     if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL)
0071         dev_dbg(dev->mt76.dev,
0072             "driver does not support HW RF ctrl\n");
0073
0074     if (!mt76x02_field_valid(nic_conf0 >> 8))
0075         return;
0076
0077     if (FIELD_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||
0078         FIELD_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)
0079         dev_err(dev->mt76.dev, "invalid tx-rx stream\n");
0080 }
0081
0082 static void mt76x0_set_temp_offset(struct mt76x02_dev *dev)
0083 {
0084     u8 val;
0085
0086     val = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER) >> 8;
0087     if (mt76x02_field_valid(val))
0088         dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8);
0089     else
0090         dev->cal.rx.temp_offset = -10;
0091 }
0092
0093 static void mt76x0_set_freq_offset(struct mt76x02_dev *dev)
0094 {
0095     struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx;
0096     u8 val;
0097
0098     val = mt76x02_eeprom_get(dev, MT_EE_FREQ_OFFSET);
0099     if (!mt76x02_field_valid(val))
0100         val = 0;
0101     caldata->freq_offset = val;
0102
0103     val = mt76x02_eeprom_get(dev, MT_EE_TSSI_BOUND4) >> 8;
0104     if (!mt76x02_field_valid(val))
0105         val = 0;
0106
0107     caldata->freq_offset -= mt76x02_sign_extend(val, 8);
0108 }
0109
0110 void mt76x0_read_rx_gain(struct mt76x02_dev *dev)
0111 {
0112     struct ieee80211_channel *chan = dev->mphy.chandef.chan;
0113     struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx;
0114     s8 val, lna_5g[3], lna_2g;
0115     u16 rssi_offset;
0116     int i;
0117
0118     mt76x02_get_rx_gain(dev, chan->band, &rssi_offset, &lna_2g, lna_5g);
0119     caldata->lna_gain = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
0120
0121     for (i = 0; i < ARRAY_SIZE(caldata->rssi_offset); i++) {
0122         val = rssi_offset >> (8 * i);
0123         if (val < -10 || val > 10)
0124             val = 0;
0125
0126         caldata->rssi_offset[i] = val;
0127     }
0128 }
0129
0130 static s8 mt76x0_get_delta(struct mt76x02_dev *dev)
0131 {
0132     struct cfg80211_chan_def *chandef = &dev->mphy.chandef;
0133     u8 val;
0134
0135     if (chandef->width == NL80211_CHAN_WIDTH_80) {
0136         val = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER) >> 8;
0137     } else if (chandef->width == NL80211_CHAN_WIDTH_40) {
0138         u16 data;
0139
0140         data = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
0141         if (chandef->chan->band == NL80211_BAND_5GHZ)
0142             val = data >> 8;
0143         else
0144             val = data;
0145     } else {
0146         return 0;
0147     }
0148
0149     return mt76x02_rate_power_val(val);
0150 }
0151
0152 void mt76x0_get_tx_power_per_rate(struct mt76x02_dev *dev,
0153                   struct ieee80211_channel *chan,
0154                   struct mt76_rate_power *t)
0155 {
0156     bool is_2ghz = chan->band == NL80211_BAND_2GHZ;
0157     u16 val, addr;
0158     s8 delta;
0159
0160     memset(t, 0, sizeof(*t));
0161
0162     /* cck 1M, 2M, 5.5M, 11M */
0163     val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_BYRATE_BASE);
0164     t->cck[0] = t->cck[1] = s6_to_s8(val);
0165     t->cck[2] = t->cck[3] = s6_to_s8(val >> 8);
0166
0167     /* ofdm 6M, 9M, 12M, 18M */
0168     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 2 : 0x120;
0169     val = mt76x02_eeprom_get(dev, addr);
0170     t->ofdm[0] = t->ofdm[1] = s6_to_s8(val);
0171     t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8);
0172
0173     /* ofdm 24M, 36M, 48M, 54M */
0174     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 4 : 0x122;
0175     val = mt76x02_eeprom_get(dev, addr);
0176     t->ofdm[4] = t->ofdm[5] = s6_to_s8(val);
0177     t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8);
0178
0179     /* ht-vht mcs 1ss 0, 1, 2, 3 */
0180     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 6 : 0x124;
0181     val = mt76x02_eeprom_get(dev, addr);
0182     t->ht[0] = t->ht[1] = t->vht[0] = t->vht[1] = s6_to_s8(val);
0183     t->ht[2] = t->ht[3] = t->vht[2] = t->vht[3] = s6_to_s8(val >> 8);
0184
0185     /* ht-vht mcs 1ss 4, 5, 6 */
0186     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 8 : 0x126;
0187     val = mt76x02_eeprom_get(dev, addr);
0188     t->ht[4] = t->ht[5] = t->vht[4] = t->vht[5] = s6_to_s8(val);
0189     t->ht[6] = t->ht[7] = t->vht[6] = t->vht[7] = s6_to_s8(val >> 8);
0190
0191     /* ht-vht mcs 1ss 0, 1, 2, 3 stbc */
0192     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 14 : 0xec;
0193     val = mt76x02_eeprom_get(dev, addr);
0194     t->stbc[0] = t->stbc[1] = s6_to_s8(val);
0195     t->stbc[2] = t->stbc[3] = s6_to_s8(val >> 8);
0196
0197     /* ht-vht mcs 1ss 4, 5, 6 stbc */
0198     addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 16 : 0xee;
0199     val = mt76x02_eeprom_get(dev, addr);
0200     t->stbc[4] = t->stbc[5] = s6_to_s8(val);
0201     t->stbc[6] = t->stbc[7] = s6_to_s8(val >> 8);
0202
0203     /* vht mcs 8, 9 5GHz */
0204     val = mt76x02_eeprom_get(dev, 0x12c);
0205     t->vht[8] = s6_to_s8(val);
0206     t->vht[9] = s6_to_s8(val >> 8);
0207
0208     delta = mt76x0_tssi_enabled(dev) ? 0 : mt76x0_get_delta(dev);
0209     mt76x02_add_rate_power_offset(t, delta);
0210 }
0211
0212 void mt76x0_get_power_info(struct mt76x02_dev *dev,
0213                struct ieee80211_channel *chan, s8 *tp)
0214 {
0215     static const struct mt76x0_chan_map {
0216         u8 chan;
0217         u8 offset;
0218     } chan_map[] = {
0219         {   2,  0 }, {   4,  2 }, {   6,  4 }, {   8,  6 },
0220         {  10,  8 }, {  12, 10 }, {  14, 12 }, {  38,  0 },
0221         {  44,  2 }, {  48,  4 }, {  54,  6 }, {  60,  8 },
0222         {  64, 10 }, { 102, 12 }, { 108, 14 }, { 112, 16 },
0223         { 118, 18 }, { 124, 20 }, { 128, 22 }, { 134, 24 },
0224         { 140, 26 }, { 151, 28 }, { 157, 30 }, { 161, 32 },
0225         { 167, 34 }, { 171, 36 }, { 175, 38 },
0226     };
0227     u8 offset, addr;
0228     int i, idx = 0;
0229     u16 data;
0230
0231     if (mt76x0_tssi_enabled(dev)) {
0232         s8 target_power;
0233
0234         if (chan->band == NL80211_BAND_5GHZ)
0235             data = mt76x02_eeprom_get(dev, MT_EE_5G_TARGET_POWER);
0236         else
0237             data = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER);
0238         target_power = (data & 0xff) - dev->mt76.rate_power.ofdm[7];
0239         *tp = target_power + mt76x0_get_delta(dev);
0240
0241         return;
0242     }
0243
0244     for (i = 0; i < ARRAY_SIZE(chan_map); i++) {
0245         if (chan->hw_value <= chan_map[i].chan) {
0246             idx = (chan->hw_value == chan_map[i].chan);
0247             offset = chan_map[i].offset;
0248             break;
0249         }
0250     }
0251     if (i == ARRAY_SIZE(chan_map))
0252         offset = chan_map[0].offset;
0253
0254     if (chan->band == NL80211_BAND_2GHZ) {
0255         addr = MT_EE_TX_POWER_DELTA_BW80 + offset;
0256     } else {
0257         switch (chan->hw_value) {
0258         case 42:
0259             offset = 2;
0260             break;
0261         case 58:
0262             offset = 8;
0263             break;
0264         case 106:
0265             offset = 14;
0266             break;
0267         case 122:
0268             offset = 20;
0269             break;
0270         case 155:
0271             offset = 30;
0272             break;
0273         default:
0274             break;
0275         }
0276         addr = MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE + 2 + offset;
0277     }
0278
0279     data = mt76x02_eeprom_get(dev, addr);
0280     *tp = data >> (8 * idx);
0281     if (*tp < 0 || *tp > 0x3f)
0282         *tp = 5;
0283 }
0284
0285 static int mt76x0_check_eeprom(struct mt76x02_dev *dev)
0286 {
0287     u16 val;
0288
0289     val = get_unaligned_le16(dev->mt76.eeprom.data);
0290     if (!val)
0291         val = get_unaligned_le16(dev->mt76.eeprom.data +
0292                      MT_EE_PCI_ID);
0293
0294     switch (val) {
0295     case 0x7650:
0296     case 0x7610:
0297         return 0;
0298     default:
0299         dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n",
0300             val);
0301         return -EINVAL;
0302     }
0303 }
0304
0305 static int mt76x0_load_eeprom(struct mt76x02_dev *dev)
0306 {
0307     int found;
0308
0309     found = mt76_eeprom_init(&dev->mt76, MT76X0_EEPROM_SIZE);
0310     if (found < 0)
0311         return found;
0312
0313     if (found && !mt76x0_check_eeprom(dev))
0314         return 0;
0315
0316     found = mt76x0_efuse_physical_size_check(dev);
0317     if (found < 0)
0318         return found;
0319
0320     return mt76x02_get_efuse_data(dev, 0, dev->mt76.eeprom.data,
0321                       MT76X0_EEPROM_SIZE, MT_EE_READ);
0322 }
0323
0324 int mt76x0_eeprom_init(struct mt76x02_dev *dev)
0325 {
0326     u8 version, fae;
0327     u16 data;
0328     int err;
0329
0330     err = mt76x0_load_eeprom(dev);
0331     if (err < 0)
0332         return err;
0333
0334     data = mt76x02_eeprom_get(dev, MT_EE_VERSION);
0335     version = data >> 8;
0336     fae = data;
0337
0338     if (version > MT76X0U_EE_MAX_VER)
0339         dev_warn(dev->mt76.dev,
0340              "Warning: unsupported EEPROM version %02hhx\n",
0341              version);
0342     dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n",
0343          version, fae);
0344
0345     memcpy(dev->mphy.macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
0346            ETH_ALEN);
0347     mt76_eeprom_override(&dev->mphy);
0348     mt76x02_mac_setaddr(dev, dev->mphy.macaddr);
0349
0350     mt76x0_set_chip_cap(dev);
0351     mt76x0_set_freq_offset(dev);
0352     mt76x0_set_temp_offset(dev);
0353
0354     return 0;
0355 }
0356
0357 MODULE_LICENSE("Dual BSD/GPL");