Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003 
0004 #ifndef __MT76_CONNAC_MCU_H
0005 #define __MT76_CONNAC_MCU_H
0006 
0007 #include "mt76_connac.h"
0008 
0009 #define FW_FEATURE_SET_ENCRYPT      BIT(0)
0010 #define FW_FEATURE_SET_KEY_IDX      GENMASK(2, 1)
0011 #define FW_FEATURE_ENCRY_MODE       BIT(4)
0012 #define FW_FEATURE_OVERRIDE_ADDR    BIT(5)
0013 
0014 #define DL_MODE_ENCRYPT         BIT(0)
0015 #define DL_MODE_KEY_IDX         GENMASK(2, 1)
0016 #define DL_MODE_RESET_SEC_IV        BIT(3)
0017 #define DL_MODE_WORKING_PDA_CR4     BIT(4)
0018 #define DL_MODE_VALID_RAM_ENTRY         BIT(5)
0019 #define DL_CONFIG_ENCRY_MODE_SEL    BIT(6)
0020 #define DL_MODE_NEED_RSP        BIT(31)
0021 
0022 #define FW_START_OVERRIDE       BIT(0)
0023 #define FW_START_WORKING_PDA_CR4    BIT(2)
0024 
0025 #define PATCH_SEC_NOT_SUPPORT       GENMASK(31, 0)
0026 #define PATCH_SEC_TYPE_MASK     GENMASK(15, 0)
0027 #define PATCH_SEC_TYPE_INFO     0x2
0028 
0029 #define PATCH_SEC_ENC_TYPE_MASK         GENMASK(31, 24)
0030 #define PATCH_SEC_ENC_TYPE_PLAIN        0x00
0031 #define PATCH_SEC_ENC_TYPE_AES          0x01
0032 #define PATCH_SEC_ENC_TYPE_SCRAMBLE     0x02
0033 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK    GENMASK(15, 0)
0034 #define PATCH_SEC_ENC_AES_KEY_MASK      GENMASK(7, 0)
0035 
0036 #define MCU_PQ_ID(p, q)     (((p) << 15) | ((q) << 10))
0037 #define MCU_PKT_ID      0xa0
0038 
0039 struct mt76_connac2_mcu_txd {
0040     __le32 txd[8];
0041 
0042     __le16 len;
0043     __le16 pq_id;
0044 
0045     u8 cid;
0046     u8 pkt_type;
0047     u8 set_query; /* FW don't care */
0048     u8 seq;
0049 
0050     u8 uc_d2b0_rev;
0051     u8 ext_cid;
0052     u8 s2d_index;
0053     u8 ext_cid_ack;
0054 
0055     u32 rsv[5];
0056 } __packed __aligned(4);
0057 
0058 /**
0059  * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for firmware v3
0060  * @txd: hardware descriptor
0061  * @len: total length not including txd
0062  * @cid: command identifier
0063  * @pkt_type: must be 0xa0 (cmd packet by long format)
0064  * @frag_n: fragment number
0065  * @seq: sequence number
0066  * @checksum: 0 mean there is no checksum
0067  * @s2d_index: index for command source and destination
0068  *  Definition              | value | note
0069  *  CMD_S2D_IDX_H2N         | 0x00  | command from HOST to WM
0070  *  CMD_S2D_IDX_C2N         | 0x01  | command from WA to WM
0071  *  CMD_S2D_IDX_H2C         | 0x02  | command from HOST to WA
0072  *  CMD_S2D_IDX_H2N_AND_H2C | 0x03  | command from HOST to WA and WM
0073  *
0074  * @option: command option
0075  *  BIT[0]: UNI_CMD_OPT_BIT_ACK
0076  *          set to 1 to request a fw reply
0077  *          if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
0078  *          is set, mcu firmware will send response event EID = 0x01
0079  *          (UNI_EVENT_ID_CMD_RESULT) to the host.
0080  *  BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
0081  *          0: original command
0082  *          1: unified command
0083  *  BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
0084  *          0: QUERY command
0085  *          1: SET command
0086  */
0087 struct mt76_connac2_mcu_uni_txd {
0088     __le32 txd[8];
0089 
0090     /* DW1 */
0091     __le16 len;
0092     __le16 cid;
0093 
0094     /* DW2 */
0095     u8 rsv;
0096     u8 pkt_type;
0097     u8 frag_n;
0098     u8 seq;
0099 
0100     /* DW3 */
0101     __le16 checksum;
0102     u8 s2d_index;
0103     u8 option;
0104 
0105     /* DW4 */
0106     u8 rsv1[4];
0107 } __packed __aligned(4);
0108 
0109 struct mt76_connac2_mcu_rxd {
0110     __le32 rxd[6];
0111 
0112     __le16 len;
0113     __le16 pkt_type_id;
0114 
0115     u8 eid;
0116     u8 seq;
0117     u8 rsv[2];
0118 
0119     u8 ext_eid;
0120     u8 rsv1[2];
0121     u8 s2d_index;
0122 };
0123 
0124 struct mt76_connac2_patch_hdr {
0125     char build_date[16];
0126     char platform[4];
0127     __be32 hw_sw_ver;
0128     __be32 patch_ver;
0129     __be16 checksum;
0130     u16 rsv;
0131     struct {
0132         __be32 patch_ver;
0133         __be32 subsys;
0134         __be32 feature;
0135         __be32 n_region;
0136         __be32 crc;
0137         u32 rsv[11];
0138     } desc;
0139 } __packed;
0140 
0141 struct mt76_connac2_patch_sec {
0142     __be32 type;
0143     __be32 offs;
0144     __be32 size;
0145     union {
0146         __be32 spec[13];
0147         struct {
0148             __be32 addr;
0149             __be32 len;
0150             __be32 sec_key_idx;
0151             __be32 align_len;
0152             u32 rsv[9];
0153         } info;
0154     };
0155 } __packed;
0156 
0157 struct mt76_connac2_fw_trailer {
0158     u8 chip_id;
0159     u8 eco_code;
0160     u8 n_region;
0161     u8 format_ver;
0162     u8 format_flag;
0163     u8 rsv[2];
0164     char fw_ver[10];
0165     char build_date[15];
0166     __le32 crc;
0167 } __packed;
0168 
0169 struct mt76_connac2_fw_region {
0170     __le32 decomp_crc;
0171     __le32 decomp_len;
0172     __le32 decomp_blk_sz;
0173     u8 rsv[4];
0174     __le32 addr;
0175     __le32 len;
0176     u8 feature_set;
0177     u8 rsv1[15];
0178 } __packed;
0179 
0180 struct tlv {
0181     __le16 tag;
0182     __le16 len;
0183 } __packed;
0184 
0185 struct bss_info_omac {
0186     __le16 tag;
0187     __le16 len;
0188     u8 hw_bss_idx;
0189     u8 omac_idx;
0190     u8 band_idx;
0191     u8 rsv0;
0192     __le32 conn_type;
0193     u32 rsv1;
0194 } __packed;
0195 
0196 struct bss_info_basic {
0197     __le16 tag;
0198     __le16 len;
0199     __le32 network_type;
0200     u8 active;
0201     u8 rsv0;
0202     __le16 bcn_interval;
0203     u8 bssid[ETH_ALEN];
0204     u8 wmm_idx;
0205     u8 dtim_period;
0206     u8 bmc_wcid_lo;
0207     u8 cipher;
0208     u8 phy_mode;
0209     u8 max_bssid;   /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
0210     u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
0211     u8 bmc_wcid_hi; /* high Byte and version */
0212     u8 rsv[2];
0213 } __packed;
0214 
0215 struct bss_info_rf_ch {
0216     __le16 tag;
0217     __le16 len;
0218     u8 pri_ch;
0219     u8 center_ch0;
0220     u8 center_ch1;
0221     u8 bw;
0222     u8 he_ru26_block;   /* 1: don't send HETB in RU26, 0: allow */
0223     u8 he_all_disable;  /* 1: disallow all HETB, 0: allow */
0224     u8 rsv[2];
0225 } __packed;
0226 
0227 struct bss_info_ext_bss {
0228     __le16 tag;
0229     __le16 len;
0230     __le32 mbss_tsf_offset; /* in unit of us */
0231     u8 rsv[8];
0232 } __packed;
0233 
0234 enum {
0235     BSS_INFO_OMAC,
0236     BSS_INFO_BASIC,
0237     BSS_INFO_RF_CH,     /* optional, for BT/LTE coex */
0238     BSS_INFO_PM,        /* sta only */
0239     BSS_INFO_UAPSD,     /* sta only */
0240     BSS_INFO_ROAM_DETECT,   /* obsoleted */
0241     BSS_INFO_LQ_RM,     /* obsoleted */
0242     BSS_INFO_EXT_BSS,
0243     BSS_INFO_BMC_RATE,  /* for bmc rate control in CR4 */
0244     BSS_INFO_SYNC_MODE, /* obsoleted */
0245     BSS_INFO_RA,
0246     BSS_INFO_HW_AMSDU,
0247     BSS_INFO_BSS_COLOR,
0248     BSS_INFO_HE_BASIC,
0249     BSS_INFO_PROTECT_INFO,
0250     BSS_INFO_OFFLOAD,
0251     BSS_INFO_11V_MBSSID,
0252     BSS_INFO_MAX_NUM
0253 };
0254 
0255 /* sta_rec */
0256 
0257 struct sta_ntlv_hdr {
0258     u8 rsv[2];
0259     __le16 tlv_num;
0260 } __packed;
0261 
0262 struct sta_req_hdr {
0263     u8 bss_idx;
0264     u8 wlan_idx_lo;
0265     __le16 tlv_num;
0266     u8 is_tlv_append;
0267     u8 muar_idx;
0268     u8 wlan_idx_hi;
0269     u8 rsv;
0270 } __packed;
0271 
0272 struct sta_rec_basic {
0273     __le16 tag;
0274     __le16 len;
0275     __le32 conn_type;
0276     u8 conn_state;
0277     u8 qos;
0278     __le16 aid;
0279     u8 peer_addr[ETH_ALEN];
0280 #define EXTRA_INFO_VER  BIT(0)
0281 #define EXTRA_INFO_NEW  BIT(1)
0282     __le16 extra_info;
0283 } __packed;
0284 
0285 struct sta_rec_ht {
0286     __le16 tag;
0287     __le16 len;
0288     __le16 ht_cap;
0289     u16 rsv;
0290 } __packed;
0291 
0292 struct sta_rec_vht {
0293     __le16 tag;
0294     __le16 len;
0295     __le32 vht_cap;
0296     __le16 vht_rx_mcs_map;
0297     __le16 vht_tx_mcs_map;
0298     /* mt7915 - mt7921 */
0299     u8 rts_bw_sig;
0300     u8 rsv[3];
0301 } __packed;
0302 
0303 struct sta_rec_uapsd {
0304     __le16 tag;
0305     __le16 len;
0306     u8 dac_map;
0307     u8 tac_map;
0308     u8 max_sp;
0309     u8 rsv0;
0310     __le16 listen_interval;
0311     u8 rsv1[2];
0312 } __packed;
0313 
0314 struct sta_rec_ba {
0315     __le16 tag;
0316     __le16 len;
0317     u8 tid;
0318     u8 ba_type;
0319     u8 amsdu;
0320     u8 ba_en;
0321     __le16 ssn;
0322     __le16 winsize;
0323 } __packed;
0324 
0325 struct sta_rec_he {
0326     __le16 tag;
0327     __le16 len;
0328 
0329     __le32 he_cap;
0330 
0331     u8 t_frame_dur;
0332     u8 max_ampdu_exp;
0333     u8 bw_set;
0334     u8 device_class;
0335     u8 dcm_tx_mode;
0336     u8 dcm_tx_max_nss;
0337     u8 dcm_rx_mode;
0338     u8 dcm_rx_max_nss;
0339     u8 dcm_max_ru;
0340     u8 punc_pream_rx;
0341     u8 pkt_ext;
0342     u8 rsv1;
0343 
0344     __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
0345 
0346     u8 rsv2[2];
0347 } __packed;
0348 
0349 struct sta_rec_amsdu {
0350     __le16 tag;
0351     __le16 len;
0352     u8 max_amsdu_num;
0353     u8 max_mpdu_size;
0354     u8 amsdu_en;
0355     u8 rsv;
0356 } __packed;
0357 
0358 struct sta_rec_state {
0359     __le16 tag;
0360     __le16 len;
0361     __le32 flags;
0362     u8 state;
0363     u8 vht_opmode;
0364     u8 action;
0365     u8 rsv[1];
0366 } __packed;
0367 
0368 #define RA_LEGACY_OFDM GENMASK(13, 6)
0369 #define RA_LEGACY_CCK  GENMASK(3, 0)
0370 #define HT_MCS_MASK_NUM 10
0371 struct sta_rec_ra_info {
0372     __le16 tag;
0373     __le16 len;
0374     __le16 legacy;
0375     u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
0376 } __packed;
0377 
0378 struct sta_rec_phy {
0379     __le16 tag;
0380     __le16 len;
0381     __le16 basic_rate;
0382     u8 phy_type;
0383     u8 ampdu;
0384     u8 rts_policy;
0385     u8 rcpi;
0386     u8 rsv[2];
0387 } __packed;
0388 
0389 struct sta_rec_he_6g_capa {
0390     __le16 tag;
0391     __le16 len;
0392     __le16 capa;
0393     u8 rsv[2];
0394 } __packed;
0395 
0396 struct sec_key {
0397     u8 cipher_id;
0398     u8 cipher_len;
0399     u8 key_id;
0400     u8 key_len;
0401     u8 key[32];
0402 } __packed;
0403 
0404 struct sta_rec_sec {
0405     __le16 tag;
0406     __le16 len;
0407     u8 add;
0408     u8 n_cipher;
0409     u8 rsv[2];
0410 
0411     struct sec_key key[2];
0412 } __packed;
0413 
0414 struct sta_rec_bf {
0415     __le16 tag;
0416     __le16 len;
0417 
0418     __le16 pfmu;        /* 0xffff: no access right for PFMU */
0419     bool su_mu;     /* 0: SU, 1: MU */
0420     u8 bf_cap;      /* 0: iBF, 1: eBF */
0421     u8 sounding_phy;    /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
0422     u8 ndpa_rate;
0423     u8 ndp_rate;
0424     u8 rept_poll_rate;
0425     u8 tx_mode;     /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
0426     u8 ncol;
0427     u8 nrow;
0428     u8 bw;          /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
0429 
0430     u8 mem_total;
0431     u8 mem_20m;
0432     struct {
0433         u8 row;
0434         u8 col: 6, row_msb: 2;
0435     } mem[4];
0436 
0437     __le16 smart_ant;
0438     u8 se_idx;
0439     u8 auto_sounding;   /* b7: low traffic indicator
0440                  * b6: Stop sounding for this entry
0441                  * b5 ~ b0: postpone sounding
0442                  */
0443     u8 ibf_timeout;
0444     u8 ibf_dbw;
0445     u8 ibf_ncol;
0446     u8 ibf_nrow;
0447     u8 nrow_bw160;
0448     u8 ncol_bw160;
0449     u8 ru_start_idx;
0450     u8 ru_end_idx;
0451 
0452     bool trigger_su;
0453     bool trigger_mu;
0454     bool ng16_su;
0455     bool ng16_mu;
0456     bool codebook42_su;
0457     bool codebook75_mu;
0458 
0459     u8 he_ltf;
0460     u8 rsv[3];
0461 } __packed;
0462 
0463 struct sta_rec_bfee {
0464     __le16 tag;
0465     __le16 len;
0466     bool fb_identity_matrix;    /* 1: feedback identity matrix */
0467     bool ignore_feedback;       /* 1: ignore */
0468     u8 rsv[2];
0469 } __packed;
0470 
0471 struct sta_rec_muru {
0472     __le16 tag;
0473     __le16 len;
0474 
0475     struct {
0476         bool ofdma_dl_en;
0477         bool ofdma_ul_en;
0478         bool mimo_dl_en;
0479         bool mimo_ul_en;
0480         u8 rsv[4];
0481     } cfg;
0482 
0483     struct {
0484         u8 punc_pream_rx;
0485         bool he_20m_in_40m_2g;
0486         bool he_20m_in_160m;
0487         bool he_80m_in_160m;
0488         bool lt16_sigb;
0489         bool rx_su_comp_sigb;
0490         bool rx_su_non_comp_sigb;
0491         u8 rsv;
0492     } ofdma_dl;
0493 
0494     struct {
0495         u8 t_frame_dur;
0496         u8 mu_cascading;
0497         u8 uo_ra;
0498         u8 he_2x996_tone;
0499         u8 rx_t_frame_11ac;
0500         u8 rsv[3];
0501     } ofdma_ul;
0502 
0503     struct {
0504         bool vht_mu_bfee;
0505         bool partial_bw_dl_mimo;
0506         u8 rsv[2];
0507     } mimo_dl;
0508 
0509     struct {
0510         bool full_ul_mimo;
0511         bool partial_ul_mimo;
0512         u8 rsv[2];
0513     } mimo_ul;
0514 } __packed;
0515 
0516 struct sta_phy {
0517     u8 type;
0518     u8 flag;
0519     u8 stbc;
0520     u8 sgi;
0521     u8 bw;
0522     u8 ldpc;
0523     u8 mcs;
0524     u8 nss;
0525     u8 he_ltf;
0526 };
0527 
0528 struct sta_rec_ra {
0529     __le16 tag;
0530     __le16 len;
0531 
0532     u8 valid;
0533     u8 auto_rate;
0534     u8 phy_mode;
0535     u8 channel;
0536     u8 bw;
0537     u8 disable_cck;
0538     u8 ht_mcs32;
0539     u8 ht_gf;
0540     u8 ht_mcs[4];
0541     u8 mmps_mode;
0542     u8 gband_256;
0543     u8 af;
0544     u8 auth_wapi_mode;
0545     u8 rate_len;
0546 
0547     u8 supp_mode;
0548     u8 supp_cck_rate;
0549     u8 supp_ofdm_rate;
0550     __le32 supp_ht_mcs;
0551     __le16 supp_vht_mcs[4];
0552 
0553     u8 op_mode;
0554     u8 op_vht_chan_width;
0555     u8 op_vht_rx_nss;
0556     u8 op_vht_rx_nss_type;
0557 
0558     __le32 sta_cap;
0559 
0560     struct sta_phy phy;
0561 } __packed;
0562 
0563 struct sta_rec_ra_fixed {
0564     __le16 tag;
0565     __le16 len;
0566 
0567     __le32 field;
0568     u8 op_mode;
0569     u8 op_vht_chan_width;
0570     u8 op_vht_rx_nss;
0571     u8 op_vht_rx_nss_type;
0572 
0573     struct sta_phy phy;
0574 
0575     u8 spe_en;
0576     u8 short_preamble;
0577     u8 is_5g;
0578     u8 mmps_mode;
0579 } __packed;
0580 
0581 /* wtbl_rec */
0582 
0583 struct wtbl_req_hdr {
0584     u8 wlan_idx_lo;
0585     u8 operation;
0586     __le16 tlv_num;
0587     u8 wlan_idx_hi;
0588     u8 rsv[3];
0589 } __packed;
0590 
0591 struct wtbl_generic {
0592     __le16 tag;
0593     __le16 len;
0594     u8 peer_addr[ETH_ALEN];
0595     u8 muar_idx;
0596     u8 skip_tx;
0597     u8 cf_ack;
0598     u8 qos;
0599     u8 mesh;
0600     u8 adm;
0601     __le16 partial_aid;
0602     u8 baf_en;
0603     u8 aad_om;
0604 } __packed;
0605 
0606 struct wtbl_rx {
0607     __le16 tag;
0608     __le16 len;
0609     u8 rcid;
0610     u8 rca1;
0611     u8 rca2;
0612     u8 rv;
0613     u8 rsv[4];
0614 } __packed;
0615 
0616 struct wtbl_ht {
0617     __le16 tag;
0618     __le16 len;
0619     u8 ht;
0620     u8 ldpc;
0621     u8 af;
0622     u8 mm;
0623     u8 rsv[4];
0624 } __packed;
0625 
0626 struct wtbl_vht {
0627     __le16 tag;
0628     __le16 len;
0629     u8 ldpc;
0630     u8 dyn_bw;
0631     u8 vht;
0632     u8 txop_ps;
0633     u8 rsv[4];
0634 } __packed;
0635 
0636 struct wtbl_tx_ps {
0637     __le16 tag;
0638     __le16 len;
0639     u8 txps;
0640     u8 rsv[3];
0641 } __packed;
0642 
0643 struct wtbl_hdr_trans {
0644     __le16 tag;
0645     __le16 len;
0646     u8 to_ds;
0647     u8 from_ds;
0648     u8 no_rx_trans;
0649     u8 rsv;
0650 } __packed;
0651 
0652 struct wtbl_ba {
0653     __le16 tag;
0654     __le16 len;
0655     /* common */
0656     u8 tid;
0657     u8 ba_type;
0658     u8 rsv0[2];
0659     /* originator only */
0660     __le16 sn;
0661     u8 ba_en;
0662     u8 ba_winsize_idx;
0663     /* originator & recipient */
0664     __le16 ba_winsize;
0665     /* recipient only */
0666     u8 peer_addr[ETH_ALEN];
0667     u8 rst_ba_tid;
0668     u8 rst_ba_sel;
0669     u8 rst_ba_sb;
0670     u8 band_idx;
0671     u8 rsv1[4];
0672 } __packed;
0673 
0674 struct wtbl_smps {
0675     __le16 tag;
0676     __le16 len;
0677     u8 smps;
0678     u8 rsv[3];
0679 } __packed;
0680 
0681 /* mt7615 only */
0682 
0683 struct wtbl_bf {
0684     __le16 tag;
0685     __le16 len;
0686     u8 ibf;
0687     u8 ebf;
0688     u8 ibf_vht;
0689     u8 ebf_vht;
0690     u8 gid;
0691     u8 pfmu_idx;
0692     u8 rsv[2];
0693 } __packed;
0694 
0695 struct wtbl_pn {
0696     __le16 tag;
0697     __le16 len;
0698     u8 pn[6];
0699     u8 rsv[2];
0700 } __packed;
0701 
0702 struct wtbl_spe {
0703     __le16 tag;
0704     __le16 len;
0705     u8 spe_idx;
0706     u8 rsv[3];
0707 } __packed;
0708 
0709 struct wtbl_raw {
0710     __le16 tag;
0711     __le16 len;
0712     u8 wtbl_idx;
0713     u8 dw;
0714     u8 rsv[2];
0715     __le32 msk;
0716     __le32 val;
0717 } __packed;
0718 
0719 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
0720                       sizeof(struct wtbl_generic) + \
0721                       sizeof(struct wtbl_rx) +  \
0722                       sizeof(struct wtbl_ht) +  \
0723                       sizeof(struct wtbl_vht) + \
0724                       sizeof(struct wtbl_tx_ps) +   \
0725                       sizeof(struct wtbl_hdr_trans) +\
0726                       sizeof(struct wtbl_ba) +  \
0727                       sizeof(struct wtbl_bf) +  \
0728                       sizeof(struct wtbl_smps) +    \
0729                       sizeof(struct wtbl_pn) +  \
0730                       sizeof(struct wtbl_spe))
0731 
0732 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) +   \
0733                      sizeof(struct sta_rec_basic) + \
0734                      sizeof(struct sta_rec_bf) +    \
0735                      sizeof(struct sta_rec_ht) +    \
0736                      sizeof(struct sta_rec_he) +    \
0737                      sizeof(struct sta_rec_ba) +    \
0738                      sizeof(struct sta_rec_vht) +   \
0739                      sizeof(struct sta_rec_uapsd) + \
0740                      sizeof(struct sta_rec_amsdu) + \
0741                      sizeof(struct sta_rec_muru) +  \
0742                      sizeof(struct sta_rec_bfee) +  \
0743                      sizeof(struct sta_rec_ra) +    \
0744                      sizeof(struct sta_rec_sec) +   \
0745                      sizeof(struct sta_rec_ra_fixed) + \
0746                      sizeof(struct sta_rec_he_6g_capa) + \
0747                      sizeof(struct tlv) +       \
0748                      MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
0749 
0750 enum {
0751     STA_REC_BASIC,
0752     STA_REC_RA,
0753     STA_REC_RA_CMM_INFO,
0754     STA_REC_RA_UPDATE,
0755     STA_REC_BF,
0756     STA_REC_AMSDU,
0757     STA_REC_BA,
0758     STA_REC_STATE,
0759     STA_REC_TX_PROC,    /* for hdr trans and CSO in CR4 */
0760     STA_REC_HT,
0761     STA_REC_VHT,
0762     STA_REC_APPS,
0763     STA_REC_KEY,
0764     STA_REC_WTBL,
0765     STA_REC_HE,
0766     STA_REC_HW_AMSDU,
0767     STA_REC_WTBL_AADOM,
0768     STA_REC_KEY_V2,
0769     STA_REC_MURU,
0770     STA_REC_MUEDCA,
0771     STA_REC_BFEE,
0772     STA_REC_PHY = 0x15,
0773     STA_REC_HE_6G = 0x17,
0774     STA_REC_MAX_NUM
0775 };
0776 
0777 enum {
0778     WTBL_GENERIC,
0779     WTBL_RX,
0780     WTBL_HT,
0781     WTBL_VHT,
0782     WTBL_PEER_PS,       /* not used */
0783     WTBL_TX_PS,
0784     WTBL_HDR_TRANS,
0785     WTBL_SEC_KEY,
0786     WTBL_BA,
0787     WTBL_RDG,       /* obsoleted */
0788     WTBL_PROTECT,       /* not used */
0789     WTBL_CLEAR,     /* not used */
0790     WTBL_BF,
0791     WTBL_SMPS,
0792     WTBL_RAW_DATA,      /* debug only */
0793     WTBL_PN,
0794     WTBL_SPE,
0795     WTBL_MAX_NUM
0796 };
0797 
0798 #define STA_TYPE_STA            BIT(0)
0799 #define STA_TYPE_AP         BIT(1)
0800 #define STA_TYPE_ADHOC          BIT(2)
0801 #define STA_TYPE_WDS            BIT(4)
0802 #define STA_TYPE_BC         BIT(5)
0803 
0804 #define NETWORK_INFRA           BIT(16)
0805 #define NETWORK_P2P         BIT(17)
0806 #define NETWORK_IBSS            BIT(18)
0807 #define NETWORK_WDS         BIT(21)
0808 
0809 #define SCAN_FUNC_RANDOM_MAC        BIT(0)
0810 #define SCAN_FUNC_SPLIT_SCAN        BIT(5)
0811 
0812 #define CONNECTION_INFRA_STA        (STA_TYPE_STA | NETWORK_INFRA)
0813 #define CONNECTION_INFRA_AP     (STA_TYPE_AP | NETWORK_INFRA)
0814 #define CONNECTION_P2P_GC       (STA_TYPE_STA | NETWORK_P2P)
0815 #define CONNECTION_P2P_GO       (STA_TYPE_AP | NETWORK_P2P)
0816 #define CONNECTION_IBSS_ADHOC       (STA_TYPE_ADHOC | NETWORK_IBSS)
0817 #define CONNECTION_WDS          (STA_TYPE_WDS | NETWORK_WDS)
0818 #define CONNECTION_INFRA_BC     (STA_TYPE_BC | NETWORK_INFRA)
0819 
0820 #define CONN_STATE_DISCONNECT       0
0821 #define CONN_STATE_CONNECT      1
0822 #define CONN_STATE_PORT_SECURE      2
0823 
0824 /* HE MAC */
0825 #define STA_REC_HE_CAP_HTC          BIT(0)
0826 #define STA_REC_HE_CAP_BQR          BIT(1)
0827 #define STA_REC_HE_CAP_BSR          BIT(2)
0828 #define STA_REC_HE_CAP_OM           BIT(3)
0829 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU       BIT(4)
0830 /* HE PHY */
0831 #define STA_REC_HE_CAP_DUAL_BAND        BIT(5)
0832 #define STA_REC_HE_CAP_LDPC         BIT(6)
0833 #define STA_REC_HE_CAP_TRIG_CQI_FK      BIT(7)
0834 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
0835 /* STBC */
0836 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC    BIT(9)
0837 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC    BIT(10)
0838 #define STA_REC_HE_CAP_GT_80M_TX_STBC       BIT(11)
0839 #define STA_REC_HE_CAP_GT_80M_RX_STBC       BIT(12)
0840 /* GI */
0841 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI  BIT(13)
0842 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI   BIT(14)
0843 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI   BIT(15)
0844 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI   BIT(16)
0845 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI  BIT(17)
0846 /* 242 TONE */
0847 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT   BIT(18)
0848 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242   BIT(19)
0849 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242   BIT(20)
0850 
0851 #define PHY_MODE_A              BIT(0)
0852 #define PHY_MODE_B              BIT(1)
0853 #define PHY_MODE_G              BIT(2)
0854 #define PHY_MODE_GN             BIT(3)
0855 #define PHY_MODE_AN             BIT(4)
0856 #define PHY_MODE_AC             BIT(5)
0857 #define PHY_MODE_AX_24G             BIT(6)
0858 #define PHY_MODE_AX_5G              BIT(7)
0859 
0860 #define PHY_MODE_AX_6G              BIT(0) /* phymode_ext */
0861 
0862 #define MODE_CCK                BIT(0)
0863 #define MODE_OFDM               BIT(1)
0864 #define MODE_HT                 BIT(2)
0865 #define MODE_VHT                BIT(3)
0866 #define MODE_HE                 BIT(4)
0867 
0868 #define STA_CAP_WMM             BIT(0)
0869 #define STA_CAP_SGI_20              BIT(4)
0870 #define STA_CAP_SGI_40              BIT(5)
0871 #define STA_CAP_TX_STBC             BIT(6)
0872 #define STA_CAP_RX_STBC             BIT(7)
0873 #define STA_CAP_VHT_SGI_80          BIT(16)
0874 #define STA_CAP_VHT_SGI_160         BIT(17)
0875 #define STA_CAP_VHT_TX_STBC         BIT(18)
0876 #define STA_CAP_VHT_RX_STBC         BIT(19)
0877 #define STA_CAP_VHT_LDPC            BIT(23)
0878 #define STA_CAP_LDPC                BIT(24)
0879 #define STA_CAP_HT              BIT(26)
0880 #define STA_CAP_VHT             BIT(27)
0881 #define STA_CAP_HE              BIT(28)
0882 
0883 enum {
0884     PHY_TYPE_HR_DSSS_INDEX = 0,
0885     PHY_TYPE_ERP_INDEX,
0886     PHY_TYPE_ERP_P2P_INDEX,
0887     PHY_TYPE_OFDM_INDEX,
0888     PHY_TYPE_HT_INDEX,
0889     PHY_TYPE_VHT_INDEX,
0890     PHY_TYPE_HE_INDEX,
0891     PHY_TYPE_INDEX_NUM
0892 };
0893 
0894 #define PHY_TYPE_BIT_HR_DSSS            BIT(PHY_TYPE_HR_DSSS_INDEX)
0895 #define PHY_TYPE_BIT_ERP            BIT(PHY_TYPE_ERP_INDEX)
0896 #define PHY_TYPE_BIT_OFDM           BIT(PHY_TYPE_OFDM_INDEX)
0897 #define PHY_TYPE_BIT_HT             BIT(PHY_TYPE_HT_INDEX)
0898 #define PHY_TYPE_BIT_VHT            BIT(PHY_TYPE_VHT_INDEX)
0899 #define PHY_TYPE_BIT_HE             BIT(PHY_TYPE_HE_INDEX)
0900 
0901 #define MT_WTBL_RATE_TX_MODE            GENMASK(9, 6)
0902 #define MT_WTBL_RATE_MCS            GENMASK(5, 0)
0903 #define MT_WTBL_RATE_NSS            GENMASK(12, 10)
0904 #define MT_WTBL_RATE_HE_GI          GENMASK(7, 4)
0905 #define MT_WTBL_RATE_GI             GENMASK(3, 0)
0906 
0907 #define MT_WTBL_W5_CHANGE_BW_RATE       GENMASK(7, 5)
0908 #define MT_WTBL_W5_SHORT_GI_20          BIT(8)
0909 #define MT_WTBL_W5_SHORT_GI_40          BIT(9)
0910 #define MT_WTBL_W5_SHORT_GI_80          BIT(10)
0911 #define MT_WTBL_W5_SHORT_GI_160         BIT(11)
0912 #define MT_WTBL_W5_BW_CAP           GENMASK(13, 12)
0913 #define MT_WTBL_W5_MPDU_FAIL_COUNT      GENMASK(25, 23)
0914 #define MT_WTBL_W5_MPDU_OK_COUNT        GENMASK(28, 26)
0915 #define MT_WTBL_W5_RATE_IDX         GENMASK(31, 29)
0916 
0917 enum {
0918     WTBL_RESET_AND_SET = 1,
0919     WTBL_SET,
0920     WTBL_QUERY,
0921     WTBL_RESET_ALL
0922 };
0923 
0924 enum {
0925     MT_BA_TYPE_INVALID,
0926     MT_BA_TYPE_ORIGINATOR,
0927     MT_BA_TYPE_RECIPIENT
0928 };
0929 
0930 enum {
0931     RST_BA_MAC_TID_MATCH,
0932     RST_BA_MAC_MATCH,
0933     RST_BA_NO_MATCH
0934 };
0935 
0936 enum {
0937     DEV_INFO_ACTIVE,
0938     DEV_INFO_MAX_NUM
0939 };
0940 
0941 /* event table */
0942 enum {
0943     MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
0944     MCU_EVENT_FW_START = 0x01,
0945     MCU_EVENT_GENERIC = 0x01,
0946     MCU_EVENT_ACCESS_REG = 0x02,
0947     MCU_EVENT_MT_PATCH_SEM = 0x04,
0948     MCU_EVENT_REG_ACCESS = 0x05,
0949     MCU_EVENT_LP_INFO = 0x07,
0950     MCU_EVENT_SCAN_DONE = 0x0d,
0951     MCU_EVENT_TX_DONE = 0x0f,
0952     MCU_EVENT_ROC = 0x10,
0953     MCU_EVENT_BSS_ABSENCE  = 0x11,
0954     MCU_EVENT_BSS_BEACON_LOSS = 0x13,
0955     MCU_EVENT_CH_PRIVILEGE = 0x18,
0956     MCU_EVENT_SCHED_SCAN_DONE = 0x23,
0957     MCU_EVENT_DBG_MSG = 0x27,
0958     MCU_EVENT_TXPWR = 0xd0,
0959     MCU_EVENT_EXT = 0xed,
0960     MCU_EVENT_RESTART_DL = 0xef,
0961     MCU_EVENT_COREDUMP = 0xf0,
0962 };
0963 
0964 /* ext event table */
0965 enum {
0966     MCU_EXT_EVENT_PS_SYNC = 0x5,
0967     MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
0968     MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
0969     MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
0970     MCU_EXT_EVENT_RDD_REPORT = 0x3a,
0971     MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
0972     MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
0973     MCU_EXT_EVENT_MURU_CTRL = 0x9f,
0974 };
0975 
0976 enum {
0977     MCU_Q_QUERY,
0978     MCU_Q_SET,
0979     MCU_Q_RESERVED,
0980     MCU_Q_NA
0981 };
0982 
0983 enum {
0984     MCU_S2D_H2N,
0985     MCU_S2D_C2N,
0986     MCU_S2D_H2C,
0987     MCU_S2D_H2CN
0988 };
0989 
0990 enum {
0991     PATCH_NOT_DL_SEM_FAIL,
0992     PATCH_IS_DL,
0993     PATCH_NOT_DL_SEM_SUCCESS,
0994     PATCH_REL_SEM_SUCCESS
0995 };
0996 
0997 enum {
0998     FW_STATE_INITIAL,
0999     FW_STATE_FW_DOWNLOAD,
1000     FW_STATE_NORMAL_OPERATION,
1001     FW_STATE_NORMAL_TRX,
1002     FW_STATE_RDY = 7
1003 };
1004 
1005 enum {
1006     CH_SWITCH_NORMAL = 0,
1007     CH_SWITCH_SCAN = 3,
1008     CH_SWITCH_MCC = 4,
1009     CH_SWITCH_DFS = 5,
1010     CH_SWITCH_BACKGROUND_SCAN_START = 6,
1011     CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1012     CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1013     CH_SWITCH_SCAN_BYPASS_DPD = 9
1014 };
1015 
1016 enum {
1017     THERMAL_SENSOR_TEMP_QUERY,
1018     THERMAL_SENSOR_MANUAL_CTRL,
1019     THERMAL_SENSOR_INFO_QUERY,
1020     THERMAL_SENSOR_TASK_CTRL,
1021 };
1022 
1023 enum mcu_cipher_type {
1024     MCU_CIPHER_NONE = 0,
1025     MCU_CIPHER_WEP40,
1026     MCU_CIPHER_WEP104,
1027     MCU_CIPHER_WEP128,
1028     MCU_CIPHER_TKIP,
1029     MCU_CIPHER_AES_CCMP,
1030     MCU_CIPHER_CCMP_256,
1031     MCU_CIPHER_GCMP,
1032     MCU_CIPHER_GCMP_256,
1033     MCU_CIPHER_WAPI,
1034     MCU_CIPHER_BIP_CMAC_128,
1035 };
1036 
1037 enum {
1038     EE_MODE_EFUSE,
1039     EE_MODE_BUFFER,
1040 };
1041 
1042 enum {
1043     EE_FORMAT_BIN,
1044     EE_FORMAT_WHOLE,
1045     EE_FORMAT_MULTIPLE,
1046 };
1047 
1048 enum {
1049     MCU_PHY_STATE_TX_RATE,
1050     MCU_PHY_STATE_RX_RATE,
1051     MCU_PHY_STATE_RSSI,
1052     MCU_PHY_STATE_CONTENTION_RX_RATE,
1053     MCU_PHY_STATE_OFDMLQ_CNINFO,
1054 };
1055 
1056 #define MCU_CMD_ACK             BIT(0)
1057 #define MCU_CMD_UNI             BIT(1)
1058 #define MCU_CMD_QUERY               BIT(2)
1059 
1060 #define MCU_CMD_UNI_EXT_ACK         (MCU_CMD_ACK | MCU_CMD_UNI | \
1061                          MCU_CMD_QUERY)
1062 
1063 #define __MCU_CMD_FIELD_ID          GENMASK(7, 0)
1064 #define __MCU_CMD_FIELD_EXT_ID          GENMASK(15, 8)
1065 #define __MCU_CMD_FIELD_QUERY           BIT(16)
1066 #define __MCU_CMD_FIELD_UNI         BIT(17)
1067 #define __MCU_CMD_FIELD_CE          BIT(18)
1068 #define __MCU_CMD_FIELD_WA          BIT(19)
1069 
1070 #define MCU_CMD(_t)             FIELD_PREP(__MCU_CMD_FIELD_ID,      \
1071                                MCU_CMD_##_t)
1072 #define MCU_EXT_CMD(_t)             (MCU_CMD(EXT_CID) | \
1073                          FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1074                                 MCU_EXT_CMD_##_t))
1075 #define MCU_EXT_QUERY(_t)           (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1076 #define MCU_UNI_CMD(_t)             (__MCU_CMD_FIELD_UNI |          \
1077                          FIELD_PREP(__MCU_CMD_FIELD_ID,     \
1078                                 MCU_UNI_CMD_##_t))
1079 #define MCU_CE_CMD(_t)              (__MCU_CMD_FIELD_CE |           \
1080                          FIELD_PREP(__MCU_CMD_FIELD_ID,     \
1081                                MCU_CE_CMD_##_t))
1082 #define MCU_CE_QUERY(_t)            (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1083 
1084 #define MCU_WA_CMD(_t)              (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1085 #define MCU_WA_EXT_CMD(_t)          (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1086 #define MCU_WA_PARAM_CMD(_t)            (MCU_WA_CMD(WA_PARAM) | \
1087                          FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1088                                 MCU_WA_PARAM_CMD_##_t))
1089 
1090 enum {
1091     MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1092     MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1093     MCU_EXT_CMD_RF_TEST = 0x04,
1094     MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1095     MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1096     MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1097     MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1098     MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1099     MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1100     MCU_EXT_CMD_THERMAL_PROT = 0x23,
1101     MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1102     MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1103     MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1104     MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1105     MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1106     MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1107     MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1108     MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1109     MCU_EXT_CMD_ATE_CTRL = 0x3d,
1110     MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1111     MCU_EXT_CMD_DBDC_CTRL = 0x45,
1112     MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1113     MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1114     MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1115     MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1116     MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1117     MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1118     MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1119     MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1120     MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1121     MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1122     MCU_EXT_CMD_TXDPD_CAL = 0x60,
1123     MCU_EXT_CMD_CAL_CACHE = 0x67,
1124     MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1125     MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1126     MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1127     MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1128     MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1129     MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1130     MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1131     MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1132     MCU_EXT_CMD_MURU_CTRL = 0x9f,
1133     MCU_EXT_CMD_SET_SPR = 0xa8,
1134     MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1135     MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1136     MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1137 };
1138 
1139 enum {
1140     MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1141     MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1142     MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1143     MCU_UNI_CMD_SUSPEND = 0x05,
1144     MCU_UNI_CMD_OFFLOAD = 0x06,
1145     MCU_UNI_CMD_HIF_CTRL = 0x07,
1146     MCU_UNI_CMD_SNIFFER = 0x24,
1147 };
1148 
1149 enum {
1150     MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1151     MCU_CMD_FW_START_REQ = 0x02,
1152     MCU_CMD_INIT_ACCESS_REG = 0x3,
1153     MCU_CMD_NIC_POWER_CTRL = 0x4,
1154     MCU_CMD_PATCH_START_REQ = 0x05,
1155     MCU_CMD_PATCH_FINISH_REQ = 0x07,
1156     MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1157     MCU_CMD_WA_PARAM = 0xc4,
1158     MCU_CMD_EXT_CID = 0xed,
1159     MCU_CMD_FW_SCATTER = 0xee,
1160     MCU_CMD_RESTART_DL_REQ = 0xef,
1161 };
1162 
1163 /* offload mcu commands */
1164 enum {
1165     MCU_CE_CMD_TEST_CTRL = 0x01,
1166     MCU_CE_CMD_START_HW_SCAN = 0x03,
1167     MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1168     MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1169     MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1170     MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1171     MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1172     MCU_CE_CMD_SET_ROC = 0x1c,
1173     MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1174     MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1175     MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1176     MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1177     MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1178     MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1179     MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1180     MCU_CE_CMD_REG_WRITE = 0xc0,
1181     MCU_CE_CMD_REG_READ = 0xc0,
1182     MCU_CE_CMD_CHIP_CONFIG = 0xca,
1183     MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1184     MCU_CE_CMD_GET_WTBL = 0xcd,
1185     MCU_CE_CMD_GET_TXPWR = 0xd0,
1186 };
1187 
1188 enum {
1189     PATCH_SEM_RELEASE,
1190     PATCH_SEM_GET
1191 };
1192 
1193 enum {
1194     UNI_BSS_INFO_BASIC = 0,
1195     UNI_BSS_INFO_RLM = 2,
1196     UNI_BSS_INFO_BSS_COLOR = 4,
1197     UNI_BSS_INFO_HE_BASIC = 5,
1198     UNI_BSS_INFO_BCN_CONTENT = 7,
1199     UNI_BSS_INFO_QBSS = 15,
1200     UNI_BSS_INFO_UAPSD = 19,
1201     UNI_BSS_INFO_PS = 21,
1202     UNI_BSS_INFO_BCNFT = 22,
1203 };
1204 
1205 enum {
1206     UNI_OFFLOAD_OFFLOAD_ARP,
1207     UNI_OFFLOAD_OFFLOAD_ND,
1208     UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1209     UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1210 };
1211 
1212 enum {
1213     MT_NIC_CAP_TX_RESOURCE,
1214     MT_NIC_CAP_TX_EFUSE_ADDR,
1215     MT_NIC_CAP_COEX,
1216     MT_NIC_CAP_SINGLE_SKU,
1217     MT_NIC_CAP_CSUM_OFFLOAD,
1218     MT_NIC_CAP_HW_VER,
1219     MT_NIC_CAP_SW_VER,
1220     MT_NIC_CAP_MAC_ADDR,
1221     MT_NIC_CAP_PHY,
1222     MT_NIC_CAP_MAC,
1223     MT_NIC_CAP_FRAME_BUF,
1224     MT_NIC_CAP_BEAM_FORM,
1225     MT_NIC_CAP_LOCATION,
1226     MT_NIC_CAP_MUMIMO,
1227     MT_NIC_CAP_BUFFER_MODE_INFO,
1228     MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1229     MT_NIC_CAP_ANTSWP = 0x16,
1230     MT_NIC_CAP_WFDMA_REALLOC,
1231     MT_NIC_CAP_6G,
1232 };
1233 
1234 #define UNI_WOW_DETECT_TYPE_MAGIC       BIT(0)
1235 #define UNI_WOW_DETECT_TYPE_ANY         BIT(1)
1236 #define UNI_WOW_DETECT_TYPE_DISCONNECT      BIT(2)
1237 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL  BIT(3)
1238 #define UNI_WOW_DETECT_TYPE_BCN_LOST        BIT(4)
1239 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT    BIT(5)
1240 #define UNI_WOW_DETECT_TYPE_BITMAP      BIT(6)
1241 
1242 enum {
1243     UNI_SUSPEND_MODE_SETTING,
1244     UNI_SUSPEND_WOW_CTRL,
1245     UNI_SUSPEND_WOW_GPIO_PARAM,
1246     UNI_SUSPEND_WOW_WAKEUP_PORT,
1247     UNI_SUSPEND_WOW_PATTERN,
1248 };
1249 
1250 enum {
1251     WOW_USB = 1,
1252     WOW_PCIE = 2,
1253     WOW_GPIO = 3,
1254 };
1255 
1256 struct mt76_connac_bss_basic_tlv {
1257     __le16 tag;
1258     __le16 len;
1259     u8 active;
1260     u8 omac_idx;
1261     u8 hw_bss_idx;
1262     u8 band_idx;
1263     __le32 conn_type;
1264     u8 conn_state;
1265     u8 wmm_idx;
1266     u8 bssid[ETH_ALEN];
1267     __le16 bmc_tx_wlan_idx;
1268     __le16 bcn_interval;
1269     u8 dtim_period;
1270     u8 phymode; /* bit(0): A
1271              * bit(1): B
1272              * bit(2): G
1273              * bit(3): GN
1274              * bit(4): AN
1275              * bit(5): AC
1276              * bit(6): AX2
1277              * bit(7): AX5
1278              * bit(8): AX6
1279              */
1280     __le16 sta_idx;
1281     __le16 nonht_basic_phy;
1282     u8 phymode_ext; /* bit(0) AX_6G */
1283     u8 pad[1];
1284 } __packed;
1285 
1286 struct mt76_connac_bss_qos_tlv {
1287     __le16 tag;
1288     __le16 len;
1289     u8 qos;
1290     u8 pad[3];
1291 } __packed;
1292 
1293 struct mt76_connac_beacon_loss_event {
1294     u8 bss_idx;
1295     u8 reason;
1296     u8 pad[2];
1297 } __packed;
1298 
1299 struct mt76_connac_mcu_bss_event {
1300     u8 bss_idx;
1301     u8 is_absent;
1302     u8 free_quota;
1303     u8 pad;
1304 } __packed;
1305 
1306 struct mt76_connac_mcu_scan_ssid {
1307     __le32 ssid_len;
1308     u8 ssid[IEEE80211_MAX_SSID_LEN];
1309 } __packed;
1310 
1311 struct mt76_connac_mcu_scan_channel {
1312     u8 band; /* 1: 2.4GHz
1313           * 2: 5.0GHz
1314           * Others: Reserved
1315           */
1316     u8 channel_num;
1317 } __packed;
1318 
1319 struct mt76_connac_mcu_scan_match {
1320     __le32 rssi_th;
1321     u8 ssid[IEEE80211_MAX_SSID_LEN];
1322     u8 ssid_len;
1323     u8 rsv[3];
1324 } __packed;
1325 
1326 struct mt76_connac_hw_scan_req {
1327     u8 seq_num;
1328     u8 bss_idx;
1329     u8 scan_type; /* 0: PASSIVE SCAN
1330                * 1: ACTIVE SCAN
1331                */
1332     u8 ssid_type; /* BIT(0) wildcard SSID
1333                * BIT(1) P2P wildcard SSID
1334                * BIT(2) specified SSID + wildcard SSID
1335                * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1336                */
1337     u8 ssids_num;
1338     u8 probe_req_num; /* Number of probe request for each SSID */
1339     u8 scan_func; /* BIT(0) Enable random MAC scan
1340                * BIT(1) Disable DBDC scan type 1~3.
1341                * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1342                */
1343     u8 version; /* 0: Not support fields after ies.
1344              * 1: Support fields after ies.
1345              */
1346     struct mt76_connac_mcu_scan_ssid ssids[4];
1347     __le16 probe_delay_time;
1348     __le16 channel_dwell_time; /* channel Dwell interval */
1349     __le16 timeout_value;
1350     u8 channel_type; /* 0: Full channels
1351               * 1: Only 2.4GHz channels
1352               * 2: Only 5GHz channels
1353               * 3: P2P social channel only (channel #1, #6 and #11)
1354               * 4: Specified channels
1355               * Others: Reserved
1356               */
1357     u8 channels_num; /* valid when channel_type is 4 */
1358     /* valid when channels_num is set */
1359     struct mt76_connac_mcu_scan_channel channels[32];
1360     __le16 ies_len;
1361     u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1362     /* following fields are valid if version > 0 */
1363     u8 ext_channels_num;
1364     u8 ext_ssids_num;
1365     __le16 channel_min_dwell_time;
1366     struct mt76_connac_mcu_scan_channel ext_channels[32];
1367     struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1368     u8 bssid[ETH_ALEN];
1369     u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1370     u8 pad[63];
1371     u8 ssid_type_ext;
1372 } __packed;
1373 
1374 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM     64
1375 
1376 struct mt76_connac_hw_scan_done {
1377     u8 seq_num;
1378     u8 sparse_channel_num;
1379     struct mt76_connac_mcu_scan_channel sparse_channel;
1380     u8 complete_channel_num;
1381     u8 current_state;
1382     u8 version;
1383     u8 pad;
1384     __le32 beacon_scan_num;
1385     u8 pno_enabled;
1386     u8 pad2[3];
1387     u8 sparse_channel_valid_num;
1388     u8 pad3[3];
1389     u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1390     /* idle format for channel_idle_time
1391      * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1392      * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1393      * 2: dwell time (16us)
1394      */
1395     __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1396     /* beacon and probe response count */
1397     u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1398     u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1399     __le32 beacon_2g_num;
1400     __le32 beacon_5g_num;
1401 } __packed;
1402 
1403 struct mt76_connac_sched_scan_req {
1404     u8 version;
1405     u8 seq_num;
1406     u8 stop_on_match;
1407     u8 ssids_num;
1408     u8 match_num;
1409     u8 pad;
1410     __le16 ie_len;
1411     struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1412     struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1413     u8 channel_type;
1414     u8 channels_num;
1415     u8 intervals_num;
1416     u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1417     struct mt76_connac_mcu_scan_channel channels[64];
1418     __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1419     union {
1420         struct {
1421             u8 random_mac[ETH_ALEN];
1422             u8 pad2[58];
1423         } mt7663;
1424         struct {
1425             u8 bss_idx;
1426             u8 pad1[3];
1427             __le32 delay;
1428             u8 pad2[12];
1429             u8 random_mac[ETH_ALEN];
1430             u8 pad3[38];
1431         } mt7921;
1432     };
1433 } __packed;
1434 
1435 struct mt76_connac_sched_scan_done {
1436     u8 seq_num;
1437     u8 status; /* 0: ssid found */
1438     __le16 pad;
1439 } __packed;
1440 
1441 struct bss_info_uni_bss_color {
1442     __le16 tag;
1443     __le16 len;
1444     u8 enable;
1445     u8 bss_color;
1446     u8 rsv[2];
1447 } __packed;
1448 
1449 struct bss_info_uni_he {
1450     __le16 tag;
1451     __le16 len;
1452     __le16 he_rts_thres;
1453     u8 he_pe_duration;
1454     u8 su_disable;
1455     __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1456     u8 rsv[2];
1457 } __packed;
1458 
1459 struct mt76_connac_gtk_rekey_tlv {
1460     __le16 tag;
1461     __le16 len;
1462     u8 kek[NL80211_KEK_LEN];
1463     u8 kck[NL80211_KCK_LEN];
1464     u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1465     u8 rekey_mode; /* 0: rekey offload enable
1466             * 1: rekey offload disable
1467             * 2: rekey update
1468             */
1469     u8 keyid;
1470     u8 option; /* 1: rekey data update without enabling offload */
1471     u8 pad[1];
1472     __le32 proto; /* WPA-RSN-WAPI-OPSN */
1473     __le32 pairwise_cipher;
1474     __le32 group_cipher;
1475     __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1476     __le32 mgmt_group_cipher;
1477     u8 reserverd[4];
1478 } __packed;
1479 
1480 #define MT76_CONNAC_WOW_MASK_MAX_LEN            16
1481 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN          128
1482 
1483 struct mt76_connac_wow_pattern_tlv {
1484     __le16 tag;
1485     __le16 len;
1486     u8 index; /* pattern index */
1487     u8 enable; /* 0: disable
1488             * 1: enable
1489             */
1490     u8 data_len; /* pattern length */
1491     u8 pad;
1492     u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1493     u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1494     u8 rsv[4];
1495 } __packed;
1496 
1497 struct mt76_connac_wow_ctrl_tlv {
1498     __le16 tag;
1499     __le16 len;
1500     u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1501          * 0x2: PM_WOWLAN_REQ_STOP
1502          * 0x3: PM_WOWLAN_PARAM_CLEAR
1503          */
1504     u8 trigger; /* 0: NONE
1505              * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1506              * BIT(1): NL80211_WOWLAN_TRIG_ANY
1507              * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1508              * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1509              * BIT(4): BEACON_LOST
1510              * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1511              */
1512     u8 wakeup_hif; /* 0x0: HIF_SDIO
1513             * 0x1: HIF_USB
1514             * 0x2: HIF_PCIE
1515             * 0x3: HIF_GPIO
1516             */
1517     u8 pad;
1518     u8 rsv[4];
1519 } __packed;
1520 
1521 struct mt76_connac_wow_gpio_param_tlv {
1522     __le16 tag;
1523     __le16 len;
1524     u8 gpio_pin;
1525     u8 trigger_lvl;
1526     u8 pad[2];
1527     __le32 gpio_interval;
1528     u8 rsv[4];
1529 } __packed;
1530 
1531 struct mt76_connac_arpns_tlv {
1532     __le16 tag;
1533     __le16 len;
1534     u8 mode;
1535     u8 ips_num;
1536     u8 option;
1537     u8 pad[1];
1538 } __packed;
1539 
1540 struct mt76_connac_suspend_tlv {
1541     __le16 tag;
1542     __le16 len;
1543     u8 enable; /* 0: suspend mode disabled
1544             * 1: suspend mode enabled
1545             */
1546     u8 mdtim; /* LP parameter */
1547     u8 wow_suspend; /* 0: update by origin policy
1548              * 1: update by wow dtim
1549              */
1550     u8 pad[5];
1551 } __packed;
1552 
1553 enum mt76_sta_info_state {
1554     MT76_STA_INFO_STATE_NONE,
1555     MT76_STA_INFO_STATE_AUTH,
1556     MT76_STA_INFO_STATE_ASSOC
1557 };
1558 
1559 struct mt76_sta_cmd_info {
1560     struct ieee80211_sta *sta;
1561     struct mt76_wcid *wcid;
1562 
1563     struct ieee80211_vif *vif;
1564 
1565     bool offload_fw;
1566     bool enable;
1567     bool newly;
1568     int cmd;
1569     u8 rcpi;
1570     u8 state;
1571 };
1572 
1573 #define MT_SKU_POWER_LIMIT  161
1574 
1575 struct mt76_connac_sku_tlv {
1576     u8 channel;
1577     s8 pwr_limit[MT_SKU_POWER_LIMIT];
1578 } __packed;
1579 
1580 struct mt76_connac_tx_power_limit_tlv {
1581     /* DW0 - common info*/
1582     u8 ver;
1583     u8 pad0;
1584     __le16 len;
1585     /* DW1 - cmd hint */
1586     u8 n_chan; /* # channel */
1587     u8 band; /* 2.4GHz - 5GHz - 6GHz */
1588     u8 last_msg;
1589     u8 pad1;
1590     /* DW3 */
1591     u8 alpha2[4]; /* regulatory_request.alpha2 */
1592     u8 pad2[32];
1593 } __packed;
1594 
1595 struct mt76_connac_config {
1596     __le16 id;
1597     u8 type;
1598     u8 resp_type;
1599     __le16 data_size;
1600     __le16 resv;
1601     u8 data[320];
1602 } __packed;
1603 
1604 static inline enum mcu_cipher_type
1605 mt76_connac_mcu_get_cipher(int cipher)
1606 {
1607     switch (cipher) {
1608     case WLAN_CIPHER_SUITE_WEP40:
1609         return MCU_CIPHER_WEP40;
1610     case WLAN_CIPHER_SUITE_WEP104:
1611         return MCU_CIPHER_WEP104;
1612     case WLAN_CIPHER_SUITE_TKIP:
1613         return MCU_CIPHER_TKIP;
1614     case WLAN_CIPHER_SUITE_AES_CMAC:
1615         return MCU_CIPHER_BIP_CMAC_128;
1616     case WLAN_CIPHER_SUITE_CCMP:
1617         return MCU_CIPHER_AES_CCMP;
1618     case WLAN_CIPHER_SUITE_CCMP_256:
1619         return MCU_CIPHER_CCMP_256;
1620     case WLAN_CIPHER_SUITE_GCMP:
1621         return MCU_CIPHER_GCMP;
1622     case WLAN_CIPHER_SUITE_GCMP_256:
1623         return MCU_CIPHER_GCMP_256;
1624     case WLAN_CIPHER_SUITE_SMS4:
1625         return MCU_CIPHER_WAPI;
1626     default:
1627         return MCU_CIPHER_NONE;
1628     }
1629 }
1630 
1631 static inline u32
1632 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1633 {
1634     u32 ret = 0;
1635 
1636     ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1637            DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1638     if (is_mt7921(dev))
1639         ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1640                DL_CONFIG_ENCRY_MODE_SEL : 0;
1641     ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1642               FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1643     ret |= DL_MODE_NEED_RSP;
1644     ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1645 
1646     return ret;
1647 }
1648 
1649 #define to_wcid_lo(id)      FIELD_GET(GENMASK(7, 0), (u16)id)
1650 #define to_wcid_hi(id)      FIELD_GET(GENMASK(9, 8), (u16)id)
1651 
1652 static inline void
1653 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1654                  u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1655 {
1656     *wlan_idx_hi = 0;
1657 
1658     if (!is_connac_v1(dev)) {
1659         *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1660         *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1661     } else {
1662         *wlan_idx_lo = wcid ? wcid->idx : 0;
1663     }
1664 }
1665 
1666 struct sk_buff *
1667 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1668                 struct mt76_wcid *wcid, int len);
1669 static inline struct sk_buff *
1670 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1671                   struct mt76_wcid *wcid)
1672 {
1673     return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1674                            MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1675 }
1676 
1677 struct wtbl_req_hdr *
1678 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1679                    int cmd, void *sta_wtbl, struct sk_buff **skb);
1680 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1681                        int len, void *sta_ntlv,
1682                        void *sta_wtbl);
1683 static inline struct tlv *
1684 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1685 {
1686     return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1687 }
1688 
1689 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1690 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1691 void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1692                    struct ieee80211_vif *vif,
1693                    struct ieee80211_sta *sta, bool enable,
1694                    bool newly);
1695 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1696                       struct ieee80211_vif *vif,
1697                       struct ieee80211_sta *sta, void *sta_wtbl,
1698                       void *wtbl_tlv);
1699 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1700                     struct ieee80211_vif *vif,
1701                     struct mt76_wcid *wcid,
1702                     void *sta_wtbl, void *wtbl_tlv);
1703 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1704                      struct ieee80211_vif *vif,
1705                      struct mt76_wcid *wcid, int cmd);
1706 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1707                       struct ieee80211_vif *vif,
1708                       struct ieee80211_sta *sta);
1709 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1710                  struct ieee80211_sta *sta,
1711                  struct ieee80211_vif *vif,
1712                  u8 rcpi, u8 state);
1713 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1714                  struct ieee80211_sta *sta, void *sta_wtbl,
1715                  void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1716 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1717                  struct ieee80211_ampdu_params *params,
1718                  bool enable, bool tx, void *sta_wtbl,
1719                  void *wtbl_tlv);
1720 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1721                 struct ieee80211_ampdu_params *params,
1722                 bool enable, bool tx);
1723 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1724                 struct ieee80211_vif *vif,
1725                 struct mt76_wcid *wcid,
1726                 bool enable);
1727 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1728                struct ieee80211_ampdu_params *params,
1729                int cmd, bool enable, bool tx);
1730 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1731                 struct ieee80211_vif *vif,
1732                 struct mt76_wcid *wcid,
1733                 bool enable);
1734 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1735                 struct mt76_sta_cmd_info *info);
1736 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1737                       struct ieee80211_vif *vif);
1738 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1739 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1740                    bool hdr_trans);
1741 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1742                   u32 mode);
1743 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1744 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1745 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1746 int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1747 
1748 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1749                 struct ieee80211_scan_request *scan_req);
1750 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1751                    struct ieee80211_vif *vif);
1752 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1753                    struct ieee80211_vif *vif,
1754                    struct cfg80211_sched_scan_request *sreq);
1755 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1756                       struct ieee80211_vif *vif,
1757                       bool enable);
1758 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1759                       struct mt76_vif *vif,
1760                       struct ieee80211_bss_conf *info);
1761 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1762                      struct ieee80211_vif *vif,
1763                      struct cfg80211_gtk_rekey_data *key);
1764 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1765 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1766                       struct ieee80211_vif *vif);
1767 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1768                  enum ieee80211_sta_state old_state,
1769                  enum ieee80211_sta_state new_state);
1770 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1771 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1772 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1773                     struct mt76_connac_coredump *coredump);
1774 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1775 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1776                   struct ieee80211_vif *vif);
1777 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1778 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1779 
1780 const struct ieee80211_sta_he_cap *
1781 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1782 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1783                 enum nl80211_band band, struct ieee80211_sta *sta);
1784 
1785 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1786                 struct mt76_connac_sta_key_conf *sta_key_conf,
1787                 struct ieee80211_key_conf *key, int mcu_cmd,
1788                 struct mt76_wcid *wcid, enum set_key_cmd cmd);
1789 
1790 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1791 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1792                   struct ieee80211_vif *vif);
1793 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1794                   struct ieee80211_vif *vif,
1795                   struct ieee80211_sta *sta,
1796                   struct mt76_phy *phy, u16 wlan_idx,
1797                   bool enable);
1798 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1799                    struct ieee80211_sta *sta);
1800 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1801                    struct ieee80211_sta *sta,
1802                    void *sta_wtbl, void *wtbl_tlv);
1803 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1804 int mt76_connac_mcu_restart(struct mt76_dev *dev);
1805 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
1806                 u8 rx_sel, u8 val);
1807 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
1808               const char *fw_wa);
1809 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
1810 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
1811                   int cmd, int *wait_seq);
1812 #endif /* __MT76_CONNAC_MCU_H */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!