mediatek/mt76/mt76_connac.h

0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2020 MediaTek Inc. */
0003
0004 #ifndef __MT76_CONNAC_H
0005 #define __MT76_CONNAC_H
0006
0007 #include "mt76.h"
0008
0009 #define MT76_CONNAC_SCAN_IE_LEN         600
0010 #define MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL  10
0011 #define MT76_CONNAC_MAX_TIME_SCHED_SCAN_INTERVAL U16_MAX
0012 #define MT76_CONNAC_MAX_SCHED_SCAN_SSID     10
0013 #define MT76_CONNAC_MAX_SCAN_MATCH      16
0014
0015 #define MT76_CONNAC_MAX_WMM_SETS        4
0016
0017 #define MT76_CONNAC_COREDUMP_TIMEOUT        (HZ / 20)
0018 #define MT76_CONNAC_COREDUMP_SZ         (1300 * 1024)
0019
0020 #define MT_TXD_SIZE             (8 * 4)
0021
0022 #define MT_USB_TXD_SIZE             (MT_TXD_SIZE + 8 * 4)
0023 #define MT_USB_HDR_SIZE             4
0024 #define MT_USB_TAIL_SIZE            4
0025
0026 #define MT_SDIO_TXD_SIZE            (MT_TXD_SIZE + 8 * 4)
0027 #define MT_SDIO_TAIL_SIZE           8
0028 #define MT_SDIO_HDR_SIZE            4
0029
0030 #define MT_MSDU_ID_VALID        BIT(15)
0031
0032 #define MT_TXD_LEN_LAST         BIT(15)
0033 #define MT_TXD_LEN_MASK         GENMASK(11, 0)
0034 #define MT_TXD_LEN_MSDU_LAST        BIT(14)
0035 #define MT_TXD_LEN_AMSDU_LAST       BIT(15)
0036
0037 enum {
0038     CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20,
0039     CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40,
0040     CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80,
0041     CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160,
0042     CMD_CBW_10MHZ,
0043     CMD_CBW_5MHZ,
0044     CMD_CBW_8080MHZ,
0045
0046     CMD_HE_MCS_BW80 = 0,
0047     CMD_HE_MCS_BW160,
0048     CMD_HE_MCS_BW8080,
0049     CMD_HE_MCS_BW_NUM
0050 };
0051
0052 enum {
0053     HW_BSSID_0 = 0x0,
0054     HW_BSSID_1,
0055     HW_BSSID_2,
0056     HW_BSSID_3,
0057     HW_BSSID_MAX = HW_BSSID_3,
0058     EXT_BSSID_START = 0x10,
0059     EXT_BSSID_1,
0060     EXT_BSSID_15 = 0x1f,
0061     EXT_BSSID_MAX = EXT_BSSID_15,
0062     REPEATER_BSSID_START = 0x20,
0063     REPEATER_BSSID_MAX = 0x3f,
0064 };
0065
0066 struct mt76_connac_pm {
0067     bool enable:1;
0068     bool enable_user:1;
0069     bool ds_enable:1;
0070     bool ds_enable_user:1;
0071     bool suspended:1;
0072
0073     spinlock_t txq_lock;
0074     struct {
0075         struct mt76_wcid *wcid;
0076         struct sk_buff *skb;
0077     } tx_q[IEEE80211_NUM_ACS];
0078
0079     struct work_struct wake_work;
0080     wait_queue_head_t wait;
0081
0082     struct {
0083         spinlock_t lock;
0084         u32 count;
0085     } wake;
0086     struct mutex mutex;
0087
0088     struct delayed_work ps_work;
0089     unsigned long last_activity;
0090     unsigned long idle_timeout;
0091
0092     struct {
0093         unsigned long last_wake_event;
0094         unsigned long awake_time;
0095         unsigned long last_doze_event;
0096         unsigned long doze_time;
0097         unsigned int lp_wake;
0098     } stats;
0099 };
0100
0101 struct mt76_connac_coredump {
0102     struct sk_buff_head msg_list;
0103     struct delayed_work work;
0104     unsigned long last_activity;
0105 };
0106
0107 struct mt76_connac_sta_key_conf {
0108     s8 keyidx;
0109     u8 key[16];
0110 };
0111
0112 #define MT_TXP_MAX_BUF_NUM      6
0113
0114 struct mt76_connac_fw_txp {
0115     __le16 flags;
0116     __le16 token;
0117     u8 bss_idx;
0118     __le16 rept_wds_wcid;
0119     u8 nbuf;
0120     __le32 buf[MT_TXP_MAX_BUF_NUM];
0121     __le16 len[MT_TXP_MAX_BUF_NUM];
0122 } __packed __aligned(4);
0123
0124 #define MT_HW_TXP_MAX_MSDU_NUM      4
0125 #define MT_HW_TXP_MAX_BUF_NUM       4
0126
0127 struct mt76_connac_txp_ptr {
0128     __le32 buf0;
0129     __le16 len0;
0130     __le16 len1;
0131     __le32 buf1;
0132 } __packed __aligned(4);
0133
0134 struct mt76_connac_hw_txp {
0135     __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
0136     struct mt76_connac_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
0137 } __packed __aligned(4);
0138
0139 struct mt76_connac_txp_common {
0140     union {
0141         struct mt76_connac_fw_txp fw;
0142         struct mt76_connac_hw_txp hw;
0143     };
0144 };
0145
0146 struct mt76_connac_tx_free {
0147     __le16 rx_byte_cnt;
0148     __le16 ctrl;
0149     __le32 txd;
0150 } __packed __aligned(4);
0151
0152 extern const struct wiphy_wowlan_support mt76_connac_wowlan_support;
0153
0154 static inline bool is_mt7922(struct mt76_dev *dev)
0155 {
0156     return mt76_chip(dev) == 0x7922;
0157 }
0158
0159 static inline bool is_mt7921(struct mt76_dev *dev)
0160 {
0161     return mt76_chip(dev) == 0x7961 || is_mt7922(dev);
0162 }
0163
0164 static inline bool is_mt7663(struct mt76_dev *dev)
0165 {
0166     return mt76_chip(dev) == 0x7663;
0167 }
0168
0169 static inline bool is_mt7915(struct mt76_dev *dev)
0170 {
0171     return mt76_chip(dev) == 0x7915;
0172 }
0173
0174 static inline bool is_mt7916(struct mt76_dev *dev)
0175 {
0176     return mt76_chip(dev) == 0x7906;
0177 }
0178
0179 static inline bool is_mt7986(struct mt76_dev *dev)
0180 {
0181     return mt76_chip(dev) == 0x7986;
0182 }
0183
0184 static inline bool is_mt7622(struct mt76_dev *dev)
0185 {
0186     if (!IS_ENABLED(CONFIG_MT7622_WMAC))
0187         return false;
0188
0189     return mt76_chip(dev) == 0x7622;
0190 }
0191
0192 static inline bool is_mt7615(struct mt76_dev *dev)
0193 {
0194     return mt76_chip(dev) == 0x7615 || mt76_chip(dev) == 0x7611;
0195 }
0196
0197 static inline bool is_mt7611(struct mt76_dev *dev)
0198 {
0199     return mt76_chip(dev) == 0x7611;
0200 }
0201
0202 static inline bool is_connac_v1(struct mt76_dev *dev)
0203 {
0204     return is_mt7615(dev) || is_mt7663(dev) || is_mt7622(dev);
0205 }
0206
0207 static inline bool is_mt76_fw_txp(struct mt76_dev *dev)
0208 {
0209     switch (mt76_chip(dev)) {
0210     case 0x7961:
0211     case 0x7922:
0212     case 0x7663:
0213     case 0x7622:
0214         return false;
0215     default:
0216         return true;
0217     }
0218 }
0219
0220 static inline u8 mt76_connac_chan_bw(struct cfg80211_chan_def *chandef)
0221 {
0222     static const u8 width_to_bw[] = {
0223         [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
0224         [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
0225         [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
0226         [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
0227         [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
0228         [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
0229         [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
0230         [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
0231     };
0232
0233     if (chandef->width >= ARRAY_SIZE(width_to_bw))
0234         return 0;
0235
0236     return width_to_bw[chandef->width];
0237 }
0238
0239 static inline u8 mt76_connac_lmac_mapping(u8 ac)
0240 {
0241     /* LMAC uses the reverse order of mac80211 AC indexes */
0242     return 3 - ac;
0243 }
0244
0245 static inline void *
0246 mt76_connac_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
0247 {
0248     u8 *txwi;
0249
0250     if (!t)
0251         return NULL;
0252
0253     txwi = mt76_get_txwi_ptr(dev, t);
0254
0255     return (void *)(txwi + MT_TXD_SIZE);
0256 }
0257
0258 int mt76_connac_pm_wake(struct mt76_phy *phy, struct mt76_connac_pm *pm);
0259 void mt76_connac_power_save_sched(struct mt76_phy *phy,
0260                   struct mt76_connac_pm *pm);
0261 void mt76_connac_free_pending_tx_skbs(struct mt76_connac_pm *pm,
0262                       struct mt76_wcid *wcid);
0263
0264 static inline void mt76_connac_tx_cleanup(struct mt76_dev *dev)
0265 {
0266     dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WM], false);
0267     dev->queue_ops->tx_cleanup(dev, dev->q_mcu[MT_MCUQ_WA], false);
0268 }
0269
0270 static inline bool
0271 mt76_connac_pm_ref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
0272 {
0273     bool ret = false;
0274
0275     spin_lock_bh(&pm->wake.lock);
0276     if (test_bit(MT76_STATE_PM, &phy->state))
0277         goto out;
0278
0279     pm->wake.count++;
0280     ret = true;
0281 out:
0282     spin_unlock_bh(&pm->wake.lock);
0283
0284     return ret;
0285 }
0286
0287 static inline void
0288 mt76_connac_pm_unref(struct mt76_phy *phy, struct mt76_connac_pm *pm)
0289 {
0290     spin_lock_bh(&pm->wake.lock);
0291
0292     pm->last_activity = jiffies;
0293     if (--pm->wake.count == 0 &&
0294         test_bit(MT76_STATE_MCU_RUNNING, &phy->state))
0295         mt76_connac_power_save_sched(phy, pm);
0296
0297     spin_unlock_bh(&pm->wake.lock);
0298 }
0299
0300 static inline bool
0301 mt76_connac_skip_fw_pmctrl(struct mt76_phy *phy, struct mt76_connac_pm *pm)
0302 {
0303     struct mt76_dev *dev = phy->dev;
0304     bool ret;
0305
0306     if (dev->token_count)
0307         return true;
0308
0309     spin_lock_bh(&pm->wake.lock);
0310     ret = pm->wake.count || test_and_set_bit(MT76_STATE_PM, &phy->state);
0311     spin_unlock_bh(&pm->wake.lock);
0312
0313     return ret;
0314 }
0315
0316 static inline void
0317 mt76_connac_mutex_acquire(struct mt76_dev *dev, struct mt76_connac_pm *pm)
0318     __acquires(&dev->mutex)
0319 {
0320     mutex_lock(&dev->mutex);
0321     mt76_connac_pm_wake(&dev->phy, pm);
0322 }
0323
0324 static inline void
0325 mt76_connac_mutex_release(struct mt76_dev *dev, struct mt76_connac_pm *pm)
0326     __releases(&dev->mutex)
0327 {
0328     mt76_connac_power_save_sched(&dev->phy, pm);
0329     mutex_unlock(&dev->mutex);
0330 }
0331
0332 int mt76_connac_init_tx_queues(struct mt76_phy *phy, int idx, int n_desc,
0333                    int ring_base, u32 flags);
0334 void mt76_connac_write_hw_txp(struct mt76_dev *dev,
0335                   struct mt76_tx_info *tx_info,
0336                   void *txp_ptr, u32 id);
0337 void mt76_connac_txp_skb_unmap(struct mt76_dev *dev,
0338                    struct mt76_txwi_cache *txwi);
0339 void mt76_connac_tx_complete_skb(struct mt76_dev *mdev,
0340                  struct mt76_queue_entry *e);
0341 void mt76_connac_pm_queue_skb(struct ieee80211_hw *hw,
0342                   struct mt76_connac_pm *pm,
0343                   struct mt76_wcid *wcid,
0344                   struct sk_buff *skb);
0345 void mt76_connac_pm_dequeue_skbs(struct mt76_phy *phy,
0346                  struct mt76_connac_pm *pm);
0347 void mt76_connac2_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi,
0348                  struct sk_buff *skb, struct mt76_wcid *wcid,
0349                  struct ieee80211_key_conf *key, int pid,
0350                  enum mt76_txq_id qid, u32 changed);
0351 bool mt76_connac2_mac_add_txs_skb(struct mt76_dev *dev, struct mt76_wcid *wcid,
0352                   int pid, __le32 *txs_data,
0353                   struct mt76_sta_stats *stats);
0354 void mt76_connac2_mac_decode_he_radiotap(struct mt76_dev *dev,
0355                      struct sk_buff *skb,
0356                      __le32 *rxv, u32 mode);
0357 int mt76_connac2_reverse_frag0_hdr_trans(struct ieee80211_vif *vif,
0358                      struct sk_buff *skb, u16 hdr_offset);
0359 int mt76_connac2_mac_fill_rx_rate(struct mt76_dev *dev,
0360                   struct mt76_rx_status *status,
0361                   struct ieee80211_supported_band *sband,
0362                   __le32 *rxv, u8 *mode);
0363
0364 #endif /* __MT76_CONNAC_H */