mt76/mt7615/pci_mac.c

0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2020 MediaTek Inc.
0003  *
0004  * Author: Ryder Lee <ryder.lee@mediatek.com>
0005  *         Roy Luo <royluo@google.com>
0006  *         Felix Fietkau <nbd@nbd.name>
0007  *         Lorenzo Bianconi <lorenzo@kernel.org>
0008  */
0009
0010 #include <linux/etherdevice.h>
0011 #include <linux/timekeeping.h>
0012
0013 #include "mt7615.h"
0014 #include "../dma.h"
0015 #include "mac.h"
0016
0017 static void
0018 mt7615_write_fw_txp(struct mt7615_dev *dev, struct mt76_tx_info *tx_info,
0019             void *txp_ptr, u32 id)
0020 {
0021     struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
0022     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
0023     struct ieee80211_key_conf *key = info->control.hw_key;
0024     struct ieee80211_vif *vif = info->control.vif;
0025     struct mt76_connac_fw_txp *txp = txp_ptr;
0026     u8 *rept_wds_wcid = (u8 *)&txp->rept_wds_wcid;
0027     int nbuf = tx_info->nbuf - 1;
0028     int i;
0029
0030     for (i = 0; i < nbuf; i++) {
0031         txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
0032         txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
0033     }
0034     txp->nbuf = nbuf;
0035
0036     /* pass partial skb header to fw */
0037     tx_info->buf[0].len = MT_TXD_SIZE + sizeof(*txp);
0038     tx_info->buf[1].len = MT_CT_PARSE_LEN;
0039     tx_info->buf[1].skip_unmap = true;
0040     tx_info->nbuf = MT_CT_DMA_BUF_NUM;
0041
0042     txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
0043
0044     if (!key)
0045         txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
0046
0047     if (ieee80211_is_mgmt(hdr->frame_control))
0048         txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
0049
0050     if (vif) {
0051         struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv;
0052
0053         txp->bss_idx = mvif->idx;
0054     }
0055
0056     txp->token = cpu_to_le16(id);
0057     *rept_wds_wcid = 0xff;
0058 }
0059
0060 int mt7615_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
0061               enum mt76_txq_id qid, struct mt76_wcid *wcid,
0062               struct ieee80211_sta *sta,
0063               struct mt76_tx_info *tx_info)
0064 {
0065     struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0066     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
0067     struct ieee80211_key_conf *key = info->control.hw_key;
0068     int pid, id;
0069     u8 *txwi = (u8 *)txwi_ptr;
0070     struct mt76_txwi_cache *t;
0071     struct mt7615_sta *msta;
0072     void *txp;
0073
0074     msta = wcid ? container_of(wcid, struct mt7615_sta, wcid) : NULL;
0075     if (!wcid)
0076         wcid = &dev->mt76.global_wcid;
0077
0078     if ((info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) && msta) {
0079         struct mt7615_phy *phy = &dev->phy;
0080         u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
0081
0082         if (phy_idx && mdev->phys[MT_BAND1])
0083             phy = mdev->phys[MT_BAND1]->priv;
0084
0085         spin_lock_bh(&dev->mt76.lock);
0086         mt7615_mac_set_rates(phy, msta, &info->control.rates[0],
0087                      msta->rates);
0088         spin_unlock_bh(&dev->mt76.lock);
0089     }
0090
0091     t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
0092     t->skb = tx_info->skb;
0093
0094     id = mt76_token_get(mdev, &t);
0095     if (id < 0)
0096         return id;
0097
0098     pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
0099     mt7615_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, sta,
0100                   pid, key, qid, false);
0101
0102     txp = txwi + MT_TXD_SIZE;
0103     memset(txp, 0, sizeof(struct mt76_connac_txp_common));
0104     if (is_mt7615(&dev->mt76))
0105         mt7615_write_fw_txp(dev, tx_info, txp, id);
0106     else
0107         mt76_connac_write_hw_txp(mdev, tx_info, txp, id);
0108
0109     tx_info->skb = DMA_DUMMY_DATA;
0110
0111     return 0;
0112 }
0113
0114 void mt7615_dma_reset(struct mt7615_dev *dev)
0115 {
0116     int i;
0117
0118     mt76_clear(dev, MT_WPDMA_GLO_CFG,
0119            MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
0120            MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
0121
0122     usleep_range(1000, 2000);
0123
0124     for (i = 0; i < __MT_TXQ_MAX; i++)
0125         mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
0126
0127     for (i = 0; i < __MT_MCUQ_MAX; i++)
0128         mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
0129
0130     mt76_for_each_q_rx(&dev->mt76, i)
0131         mt76_queue_rx_reset(dev, i);
0132
0133     mt76_tx_status_check(&dev->mt76, true);
0134
0135     mt7615_dma_start(dev);
0136 }
0137 EXPORT_SYMBOL_GPL(mt7615_dma_reset);
0138
0139 static void
0140 mt7615_hif_int_event_trigger(struct mt7615_dev *dev, u8 event)
0141 {
0142     u32 reg = MT_MCU_INT_EVENT;
0143
0144     if (is_mt7663(&dev->mt76))
0145         reg = MT7663_MCU_INT_EVENT;
0146
0147     mt76_wr(dev, reg, event);
0148
0149     mt7622_trigger_hif_int(dev, true);
0150     mt7622_trigger_hif_int(dev, false);
0151 }
0152
0153 static bool
0154 mt7615_wait_reset_state(struct mt7615_dev *dev, u32 state)
0155 {
0156     bool ret;
0157
0158     ret = wait_event_timeout(dev->reset_wait,
0159                  (READ_ONCE(dev->reset_state) & state),
0160                  MT7615_RESET_TIMEOUT);
0161     WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
0162     return ret;
0163 }
0164
0165 static void
0166 mt7615_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
0167 {
0168     struct ieee80211_hw *hw = priv;
0169     struct mt7615_dev *dev = mt7615_hw_dev(hw);
0170
0171     switch (vif->type) {
0172     case NL80211_IFTYPE_MESH_POINT:
0173     case NL80211_IFTYPE_ADHOC:
0174     case NL80211_IFTYPE_AP:
0175         mt7615_mcu_add_beacon(dev, hw, vif,
0176                       vif->bss_conf.enable_beacon);
0177         break;
0178     default:
0179         break;
0180     }
0181 }
0182
0183 static void
0184 mt7615_update_beacons(struct mt7615_dev *dev)
0185 {
0186     struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1];
0187
0188     ieee80211_iterate_active_interfaces(dev->mt76.hw,
0189         IEEE80211_IFACE_ITER_RESUME_ALL,
0190         mt7615_update_vif_beacon, dev->mt76.hw);
0191
0192     if (!mphy_ext)
0193         return;
0194
0195     ieee80211_iterate_active_interfaces(mphy_ext->hw,
0196         IEEE80211_IFACE_ITER_RESUME_ALL,
0197         mt7615_update_vif_beacon, mphy_ext->hw);
0198 }
0199
0200 void mt7615_mac_reset_work(struct work_struct *work)
0201 {
0202     struct mt7615_phy *phy2;
0203     struct mt76_phy *ext_phy;
0204     struct mt7615_dev *dev;
0205     unsigned long timeout;
0206     int i;
0207
0208     dev = container_of(work, struct mt7615_dev, reset_work);
0209     ext_phy = dev->mt76.phys[MT_BAND1];
0210     phy2 = ext_phy ? ext_phy->priv : NULL;
0211
0212     if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_PDMA))
0213         return;
0214
0215     ieee80211_stop_queues(mt76_hw(dev));
0216     if (ext_phy)
0217         ieee80211_stop_queues(ext_phy->hw);
0218
0219     set_bit(MT76_RESET, &dev->mphy.state);
0220     set_bit(MT76_MCU_RESET, &dev->mphy.state);
0221     wake_up(&dev->mt76.mcu.wait);
0222     cancel_delayed_work_sync(&dev->mphy.mac_work);
0223     del_timer_sync(&dev->phy.roc_timer);
0224     cancel_work_sync(&dev->phy.roc_work);
0225     if (phy2) {
0226         set_bit(MT76_RESET, &phy2->mt76->state);
0227         cancel_delayed_work_sync(&phy2->mt76->mac_work);
0228         del_timer_sync(&phy2->roc_timer);
0229         cancel_work_sync(&phy2->roc_work);
0230     }
0231
0232     /* lock/unlock all queues to ensure that no tx is pending */
0233     mt76_txq_schedule_all(&dev->mphy);
0234     if (ext_phy)
0235         mt76_txq_schedule_all(ext_phy);
0236
0237     mt76_worker_disable(&dev->mt76.tx_worker);
0238     mt76_for_each_q_rx(&dev->mt76, i)
0239         napi_disable(&dev->mt76.napi[i]);
0240     napi_disable(&dev->mt76.tx_napi);
0241
0242     mt7615_mutex_acquire(dev);
0243
0244     mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_PDMA_STOPPED);
0245
0246     if (mt7615_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
0247         mt7615_dma_reset(dev);
0248
0249         mt7615_tx_token_put(dev);
0250         idr_init(&dev->mt76.token);
0251
0252         mt76_wr(dev, MT_WPDMA_MEM_RNG_ERR, 0);
0253
0254         mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_PDMA_INIT);
0255         mt7615_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
0256     }
0257
0258     clear_bit(MT76_MCU_RESET, &dev->mphy.state);
0259     clear_bit(MT76_RESET, &dev->mphy.state);
0260     if (phy2)
0261         clear_bit(MT76_RESET, &phy2->mt76->state);
0262
0263     mt76_worker_enable(&dev->mt76.tx_worker);
0264
0265     local_bh_disable();
0266     napi_enable(&dev->mt76.tx_napi);
0267     napi_schedule(&dev->mt76.tx_napi);
0268
0269     mt76_for_each_q_rx(&dev->mt76, i) {
0270         napi_enable(&dev->mt76.napi[i]);
0271         napi_schedule(&dev->mt76.napi[i]);
0272     }
0273     local_bh_enable();
0274
0275     ieee80211_wake_queues(mt76_hw(dev));
0276     if (ext_phy)
0277         ieee80211_wake_queues(ext_phy->hw);
0278
0279     mt7615_hif_int_event_trigger(dev, MT_MCU_INT_EVENT_RESET_DONE);
0280     mt7615_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
0281
0282     mt7615_update_beacons(dev);
0283
0284     mt7615_mutex_release(dev);
0285
0286     timeout = mt7615_get_macwork_timeout(dev);
0287     ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
0288                      timeout);
0289     if (phy2)
0290         ieee80211_queue_delayed_work(ext_phy->hw,
0291                          &phy2->mt76->mac_work, timeout);
0292
0293 }