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0002
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0004 #include <linux/kernel.h>
0005 #include <linux/module.h>
0006 #include <linux/platform_device.h>
0007 #include <linux/pci.h>
0008
0009 #include "mt7615.h"
0010 #include "regs.h"
0011 #include "mac.h"
0012 #include "../trace.h"
0013
0014 const u32 mt7615e_reg_map[] = {
0015 [MT_TOP_CFG_BASE] = 0x01000,
0016 [MT_HW_BASE] = 0x01000,
0017 [MT_PCIE_REMAP_2] = 0x02504,
0018 [MT_ARB_BASE] = 0x20c00,
0019 [MT_HIF_BASE] = 0x04000,
0020 [MT_CSR_BASE] = 0x07000,
0021 [MT_PLE_BASE] = 0x08000,
0022 [MT_PSE_BASE] = 0x0c000,
0023 [MT_CFG_BASE] = 0x20200,
0024 [MT_AGG_BASE] = 0x20a00,
0025 [MT_TMAC_BASE] = 0x21000,
0026 [MT_RMAC_BASE] = 0x21200,
0027 [MT_DMA_BASE] = 0x21800,
0028 [MT_PF_BASE] = 0x22000,
0029 [MT_WTBL_BASE_ON] = 0x23000,
0030 [MT_WTBL_BASE_OFF] = 0x23400,
0031 [MT_LPON_BASE] = 0x24200,
0032 [MT_MIB_BASE] = 0x24800,
0033 [MT_WTBL_BASE_ADDR] = 0x30000,
0034 [MT_PCIE_REMAP_BASE2] = 0x80000,
0035 [MT_TOP_MISC_BASE] = 0xc0000,
0036 [MT_EFUSE_ADDR_BASE] = 0x81070000,
0037 };
0038
0039 const u32 mt7663e_reg_map[] = {
0040 [MT_TOP_CFG_BASE] = 0x01000,
0041 [MT_HW_BASE] = 0x02000,
0042 [MT_DMA_SHDL_BASE] = 0x06000,
0043 [MT_PCIE_REMAP_2] = 0x0700c,
0044 [MT_ARB_BASE] = 0x20c00,
0045 [MT_HIF_BASE] = 0x04000,
0046 [MT_CSR_BASE] = 0x07000,
0047 [MT_PLE_BASE] = 0x08000,
0048 [MT_PSE_BASE] = 0x0c000,
0049 [MT_PP_BASE] = 0x0e000,
0050 [MT_CFG_BASE] = 0x20000,
0051 [MT_AGG_BASE] = 0x22000,
0052 [MT_TMAC_BASE] = 0x24000,
0053 [MT_RMAC_BASE] = 0x25000,
0054 [MT_DMA_BASE] = 0x27000,
0055 [MT_PF_BASE] = 0x28000,
0056 [MT_WTBL_BASE_ON] = 0x29000,
0057 [MT_WTBL_BASE_OFF] = 0x29800,
0058 [MT_LPON_BASE] = 0x2b000,
0059 [MT_MIB_BASE] = 0x2d000,
0060 [MT_WTBL_BASE_ADDR] = 0x30000,
0061 [MT_PCIE_REMAP_BASE2] = 0x90000,
0062 [MT_TOP_MISC_BASE] = 0xc0000,
0063 [MT_EFUSE_ADDR_BASE] = 0x78011000,
0064 };
0065
0066 u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr)
0067 {
0068 u32 base, offset;
0069
0070 if (is_mt7663(&dev->mt76)) {
0071 base = addr & MT7663_MCU_PCIE_REMAP_2_BASE;
0072 offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET;
0073 } else {
0074 base = addr & MT_MCU_PCIE_REMAP_2_BASE;
0075 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
0076 }
0077 mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base);
0078
0079 return MT_PCIE_REMAP_BASE_2 + offset;
0080 }
0081
0082 static void
0083 mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
0084 {
0085 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0086
0087 mt7615_irq_enable(dev, MT_INT_RX_DONE(q));
0088 }
0089
0090 static irqreturn_t mt7615_irq_handler(int irq, void *dev_instance)
0091 {
0092 struct mt7615_dev *dev = dev_instance;
0093
0094 mt76_wr(dev, MT_INT_MASK_CSR, 0);
0095
0096 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
0097 return IRQ_NONE;
0098
0099 tasklet_schedule(&dev->irq_tasklet);
0100
0101 return IRQ_HANDLED;
0102 }
0103
0104 static void mt7615_irq_tasklet(struct tasklet_struct *t)
0105 {
0106 struct mt7615_dev *dev = from_tasklet(dev, t, irq_tasklet);
0107 u32 intr, mask = 0, tx_mcu_mask = mt7615_tx_mcu_int_mask(dev);
0108 u32 mcu_int;
0109
0110 mt76_wr(dev, MT_INT_MASK_CSR, 0);
0111
0112 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
0113 intr &= dev->mt76.mmio.irqmask;
0114 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
0115
0116 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
0117
0118 mask |= intr & MT_INT_RX_DONE_ALL;
0119 if (intr & tx_mcu_mask)
0120 mask |= tx_mcu_mask;
0121 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
0122
0123 if (intr & tx_mcu_mask)
0124 napi_schedule(&dev->mt76.tx_napi);
0125
0126 if (intr & MT_INT_RX_DONE(0))
0127 napi_schedule(&dev->mt76.napi[0]);
0128
0129 if (intr & MT_INT_RX_DONE(1))
0130 napi_schedule(&dev->mt76.napi[1]);
0131
0132 if (!(intr & (MT_INT_MCU_CMD | MT7663_INT_MCU_CMD)))
0133 return;
0134
0135 if (is_mt7663(&dev->mt76)) {
0136 mcu_int = mt76_rr(dev, MT_MCU2HOST_INT_STATUS);
0137 mcu_int &= MT7663_MCU_CMD_ERROR_MASK;
0138 mt76_wr(dev, MT_MCU2HOST_INT_STATUS, mcu_int);
0139 } else {
0140 mcu_int = mt76_rr(dev, MT_MCU_CMD);
0141 mcu_int &= MT_MCU_CMD_ERROR_MASK;
0142 }
0143
0144 if (!mcu_int)
0145 return;
0146
0147 dev->reset_state = mcu_int;
0148 queue_work(dev->mt76.wq, &dev->reset_work);
0149 wake_up(&dev->reset_wait);
0150 }
0151
0152 static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr)
0153 {
0154 if (addr < 0x100000)
0155 return addr;
0156
0157 return mt7615_reg_map(dev, addr);
0158 }
0159
0160 static u32 mt7615_rr(struct mt76_dev *mdev, u32 offset)
0161 {
0162 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0163 u32 addr = __mt7615_reg_addr(dev, offset);
0164
0165 return dev->bus_ops->rr(mdev, addr);
0166 }
0167
0168 static void mt7615_wr(struct mt76_dev *mdev, u32 offset, u32 val)
0169 {
0170 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0171 u32 addr = __mt7615_reg_addr(dev, offset);
0172
0173 dev->bus_ops->wr(mdev, addr, val);
0174 }
0175
0176 static u32 mt7615_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
0177 {
0178 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0179 u32 addr = __mt7615_reg_addr(dev, offset);
0180
0181 return dev->bus_ops->rmw(mdev, addr, mask, val);
0182 }
0183
0184 int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base,
0185 int irq, const u32 *map)
0186 {
0187 static const struct mt76_driver_ops drv_ops = {
0188
0189 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_txp_common),
0190 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
0191 .survey_flags = SURVEY_INFO_TIME_TX |
0192 SURVEY_INFO_TIME_RX |
0193 SURVEY_INFO_TIME_BSS_RX,
0194 .token_size = MT7615_TOKEN_SIZE,
0195 .tx_prepare_skb = mt7615_tx_prepare_skb,
0196 .tx_complete_skb = mt76_connac_tx_complete_skb,
0197 .rx_check = mt7615_rx_check,
0198 .rx_skb = mt7615_queue_rx_skb,
0199 .rx_poll_complete = mt7615_rx_poll_complete,
0200 .sta_ps = mt7615_sta_ps,
0201 .sta_add = mt7615_mac_sta_add,
0202 .sta_remove = mt7615_mac_sta_remove,
0203 .update_survey = mt7615_update_channel,
0204 };
0205 struct mt76_bus_ops *bus_ops;
0206 struct ieee80211_ops *ops;
0207 struct mt7615_dev *dev;
0208 struct mt76_dev *mdev;
0209 int ret;
0210
0211 ops = devm_kmemdup(pdev, &mt7615_ops, sizeof(mt7615_ops), GFP_KERNEL);
0212 if (!ops)
0213 return -ENOMEM;
0214
0215 mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops);
0216 if (!mdev)
0217 return -ENOMEM;
0218
0219 dev = container_of(mdev, struct mt7615_dev, mt76);
0220 mt76_mmio_init(&dev->mt76, mem_base);
0221 tasklet_setup(&dev->irq_tasklet, mt7615_irq_tasklet);
0222
0223 dev->reg_map = map;
0224 dev->ops = ops;
0225 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
0226 (mt76_rr(dev, MT_HW_REV) & 0xff);
0227 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
0228
0229 dev->bus_ops = dev->mt76.bus;
0230 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
0231 GFP_KERNEL);
0232 if (!bus_ops) {
0233 ret = -ENOMEM;
0234 goto err_free_dev;
0235 }
0236
0237 bus_ops->rr = mt7615_rr;
0238 bus_ops->wr = mt7615_wr;
0239 bus_ops->rmw = mt7615_rmw;
0240 dev->mt76.bus = bus_ops;
0241
0242 mt76_wr(dev, MT_INT_MASK_CSR, 0);
0243
0244 ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler,
0245 IRQF_SHARED, KBUILD_MODNAME, dev);
0246 if (ret)
0247 goto err_free_dev;
0248
0249 if (is_mt7663(mdev))
0250 mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1);
0251
0252 ret = mt7615_register_device(dev);
0253 if (ret)
0254 goto err_free_irq;
0255
0256 return 0;
0257
0258 err_free_irq:
0259 devm_free_irq(pdev, irq, dev);
0260 err_free_dev:
0261 mt76_free_device(&dev->mt76);
0262
0263 return ret;
0264 }
0265
0266 static int __init mt7615_init(void)
0267 {
0268 int ret;
0269
0270 ret = pci_register_driver(&mt7615_pci_driver);
0271 if (ret)
0272 return ret;
0273
0274 if (IS_ENABLED(CONFIG_MT7622_WMAC)) {
0275 ret = platform_driver_register(&mt7622_wmac_driver);
0276 if (ret)
0277 pci_unregister_driver(&mt7615_pci_driver);
0278 }
0279
0280 return ret;
0281 }
0282
0283 static void __exit mt7615_exit(void)
0284 {
0285 if (IS_ENABLED(CONFIG_MT7622_WMAC))
0286 platform_driver_unregister(&mt7622_wmac_driver);
0287 pci_unregister_driver(&mt7615_pci_driver);
0288 }
0289
0290 module_init(mt7615_init);
0291 module_exit(mt7615_exit);
0292 MODULE_LICENSE("Dual BSD/GPL");
