mt76/mt7615/mcu.h

0001 /* SPDX-License-Identifier: ISC */
0002 /* Copyright (C) 2019 MediaTek Inc. */
0003
0004 #ifndef __MT7615_MCU_H
0005 #define __MT7615_MCU_H
0006
0007 #include "../mt76_connac_mcu.h"
0008
0009 struct mt7615_mcu_txd {
0010     __le32 txd[8];
0011
0012     __le16 len;
0013     __le16 pq_id;
0014
0015     u8 cid;
0016     u8 pkt_type;
0017     u8 set_query; /* FW don't care */
0018     u8 seq;
0019
0020     u8 uc_d2b0_rev;
0021     u8 ext_cid;
0022     u8 s2d_index;
0023     u8 ext_cid_ack;
0024
0025     u32 reserved[5];
0026 } __packed __aligned(4);
0027
0028 /**
0029  * struct mt7615_uni_txd - mcu command descriptor for firmware v3
0030  * @txd: hardware descriptor
0031  * @len: total length not including txd
0032  * @cid: command identifier
0033  * @pkt_type: must be 0xa0 (cmd packet by long format)
0034  * @frag_n: fragment number
0035  * @seq: sequence number
0036  * @checksum: 0 mean there is no checksum
0037  * @s2d_index: index for command source and destination
0038  *  Definition              | value | note
0039  *  CMD_S2D_IDX_H2N         | 0x00  | command from HOST to WM
0040  *  CMD_S2D_IDX_C2N         | 0x01  | command from WA to WM
0041  *  CMD_S2D_IDX_H2C         | 0x02  | command from HOST to WA
0042  *  CMD_S2D_IDX_H2N_AND_H2C | 0x03  | command from HOST to WA and WM
0043  *
0044  * @option: command option
0045  *  BIT[0]: UNI_CMD_OPT_BIT_ACK
0046  *          set to 1 to request a fw reply
0047  *          if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
0048  *          is set, mcu firmware will send response event EID = 0x01
0049  *          (UNI_EVENT_ID_CMD_RESULT) to the host.
0050  *  BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
0051  *          0: original command
0052  *          1: unified command
0053  *  BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
0054  *          0: QUERY command
0055  *          1: SET command
0056  */
0057 struct mt7615_uni_txd {
0058     __le32 txd[8];
0059
0060     /* DW1 */
0061     __le16 len;
0062     __le16 cid;
0063
0064     /* DW2 */
0065     u8 reserved;
0066     u8 pkt_type;
0067     u8 frag_n;
0068     u8 seq;
0069
0070     /* DW3 */
0071     __le16 checksum;
0072     u8 s2d_index;
0073     u8 option;
0074
0075     /* DW4 */
0076     u8 reserved2[4];
0077 } __packed __aligned(4);
0078
0079 enum {
0080     MT_SKU_CCK_1_2 = 0,
0081     MT_SKU_CCK_55_11,
0082     MT_SKU_OFDM_6_9,
0083     MT_SKU_OFDM_12_18,
0084     MT_SKU_OFDM_24_36,
0085     MT_SKU_OFDM_48,
0086     MT_SKU_OFDM_54,
0087     MT_SKU_HT20_0_8,
0088     MT_SKU_HT20_32,
0089     MT_SKU_HT20_1_2_9_10,
0090     MT_SKU_HT20_3_4_11_12,
0091     MT_SKU_HT20_5_13,
0092     MT_SKU_HT20_6_14,
0093     MT_SKU_HT20_7_15,
0094     MT_SKU_HT40_0_8,
0095     MT_SKU_HT40_32,
0096     MT_SKU_HT40_1_2_9_10,
0097     MT_SKU_HT40_3_4_11_12,
0098     MT_SKU_HT40_5_13,
0099     MT_SKU_HT40_6_14,
0100     MT_SKU_HT40_7_15,
0101     MT_SKU_VHT20_0,
0102     MT_SKU_VHT20_1_2,
0103     MT_SKU_VHT20_3_4,
0104     MT_SKU_VHT20_5_6,
0105     MT_SKU_VHT20_7,
0106     MT_SKU_VHT20_8,
0107     MT_SKU_VHT20_9,
0108     MT_SKU_VHT40_0,
0109     MT_SKU_VHT40_1_2,
0110     MT_SKU_VHT40_3_4,
0111     MT_SKU_VHT40_5_6,
0112     MT_SKU_VHT40_7,
0113     MT_SKU_VHT40_8,
0114     MT_SKU_VHT40_9,
0115     MT_SKU_VHT80_0,
0116     MT_SKU_VHT80_1_2,
0117     MT_SKU_VHT80_3_4,
0118     MT_SKU_VHT80_5_6,
0119     MT_SKU_VHT80_7,
0120     MT_SKU_VHT80_8,
0121     MT_SKU_VHT80_9,
0122     MT_SKU_VHT160_0,
0123     MT_SKU_VHT160_1_2,
0124     MT_SKU_VHT160_3_4,
0125     MT_SKU_VHT160_5_6,
0126     MT_SKU_VHT160_7,
0127     MT_SKU_VHT160_8,
0128     MT_SKU_VHT160_9,
0129     MT_SKU_1SS_DELTA,
0130     MT_SKU_2SS_DELTA,
0131     MT_SKU_3SS_DELTA,
0132     MT_SKU_4SS_DELTA,
0133 };
0134
0135 struct mt7615_mcu_rxd {
0136     __le32 rxd[4];
0137
0138     __le16 len;
0139     __le16 pkt_type_id;
0140
0141     u8 eid;
0142     u8 seq;
0143     __le16 __rsv;
0144
0145     u8 ext_eid;
0146     u8 __rsv1[2];
0147     u8 s2d_index;
0148 };
0149
0150 struct mt7615_mcu_csa_notify {
0151     struct mt7615_mcu_rxd rxd;
0152
0153     u8 omac_idx;
0154     u8 csa_count;
0155     u8 rsv[2];
0156 } __packed;
0157
0158 struct mt7615_mcu_rdd_report {
0159     struct mt7615_mcu_rxd rxd;
0160
0161     u8 band_idx;
0162     u8 long_detected;
0163     u8 constant_prf_detected;
0164     u8 staggered_prf_detected;
0165     u8 radar_type_idx;
0166     u8 periodic_pulse_num;
0167     u8 long_pulse_num;
0168     u8 hw_pulse_num;
0169
0170     u8 out_lpn;
0171     u8 out_spn;
0172     u8 out_crpn;
0173     u8 out_crpw;
0174     u8 out_crbn;
0175     u8 out_stgpn;
0176     u8 out_stgpw;
0177
0178     u8 _rsv[2];
0179
0180     __le32 out_pri_const;
0181     __le32 out_pri_stg[3];
0182
0183     struct {
0184         __le32 start;
0185         __le16 pulse_width;
0186         __le16 pulse_power;
0187     } long_pulse[32];
0188
0189     struct {
0190         __le32 start;
0191         __le16 pulse_width;
0192         __le16 pulse_power;
0193     } periodic_pulse[32];
0194
0195     struct {
0196         __le32 start;
0197         __le16 pulse_width;
0198         __le16 pulse_power;
0199         u8 sc_pass;
0200         u8 sw_reset;
0201     } hw_pulse[32];
0202 };
0203
0204 enum {
0205     MCU_ATE_SET_FREQ_OFFSET = 0xa,
0206     MCU_ATE_SET_TX_POWER_CONTROL = 0x15,
0207 };
0208
0209 struct mt7615_mcu_uni_event {
0210     u8 cid;
0211     u8 pad[3];
0212     __le32 status; /* 0: success, others: fail */
0213 } __packed;
0214
0215 struct mt7615_mcu_reg_event {
0216     __le32 reg;
0217     __le32 val;
0218 } __packed;
0219
0220 struct mt7615_roc_tlv {
0221     u8 bss_idx;
0222     u8 token;
0223     u8 active;
0224     u8 primary_chan;
0225     u8 sco;
0226     u8 band;
0227     u8 width;   /* To support 80/160MHz bandwidth */
0228     u8 freq_seg1;   /* To support 80/160MHz bandwidth */
0229     u8 freq_seg2;   /* To support 80/160MHz bandwidth */
0230     u8 req_type;
0231     u8 dbdc_band;
0232     u8 rsv0;
0233     __le32 max_interval;    /* ms */
0234     u8 rsv1[8];
0235 } __packed;
0236
0237 enum {
0238     FW_STATE_PWR_ON = 1,
0239     FW_STATE_N9_RDY = 2,
0240 };
0241
0242 enum {
0243     DBDC_TYPE_WMM,
0244     DBDC_TYPE_MGMT,
0245     DBDC_TYPE_BSS,
0246     DBDC_TYPE_MBSS,
0247     DBDC_TYPE_REPEATER,
0248     DBDC_TYPE_MU,
0249     DBDC_TYPE_BF,
0250     DBDC_TYPE_PTA,
0251     __DBDC_TYPE_MAX,
0252 };
0253
0254 #endif