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0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2019 MediaTek Inc.
0003  *
0004  * Author: Roy Luo <royluo@google.com>
0005  *         Ryder Lee <ryder.lee@mediatek.com>
0006  */
0007 
0008 #include <linux/firmware.h>
0009 #include "mt7615.h"
0010 #include "mcu.h"
0011 #include "mac.h"
0012 #include "eeprom.h"
0013 
0014 static bool prefer_offload_fw = true;
0015 module_param(prefer_offload_fw, bool, 0644);
0016 MODULE_PARM_DESC(prefer_offload_fw,
0017          "Prefer client mode offload firmware (MT7663)");
0018 
0019 struct mt7615_patch_hdr {
0020     char build_date[16];
0021     char platform[4];
0022     __be32 hw_sw_ver;
0023     __be32 patch_ver;
0024     __be16 checksum;
0025 } __packed;
0026 
0027 struct mt7615_fw_trailer {
0028     __le32 addr;
0029     u8 chip_id;
0030     u8 feature_set;
0031     u8 eco_code;
0032     char fw_ver[10];
0033     char build_date[15];
0034     __le32 len;
0035 } __packed;
0036 
0037 #define FW_V3_COMMON_TAILER_SIZE    36
0038 #define FW_V3_REGION_TAILER_SIZE    40
0039 #define FW_START_OVERRIDE       BIT(0)
0040 #define FW_START_DLYCAL                 BIT(1)
0041 #define FW_START_WORKING_PDA_CR4    BIT(2)
0042 
0043 struct mt7663_fw_buf {
0044     __le32 crc;
0045     __le32 d_img_size;
0046     __le32 block_size;
0047     u8 rsv[4];
0048     __le32 img_dest_addr;
0049     __le32 img_size;
0050     u8 feature_set;
0051 };
0052 
0053 #define MT7615_PATCH_ADDRESS        0x80000
0054 #define MT7622_PATCH_ADDRESS        0x9c000
0055 #define MT7663_PATCH_ADDRESS        0xdc000
0056 
0057 #define N9_REGION_NUM           2
0058 #define CR4_REGION_NUM          1
0059 
0060 #define IMG_CRC_LEN         4
0061 
0062 void mt7615_mcu_fill_msg(struct mt7615_dev *dev, struct sk_buff *skb,
0063              int cmd, int *wait_seq)
0064 {
0065     int txd_len, mcu_cmd = FIELD_GET(__MCU_CMD_FIELD_ID, cmd);
0066     struct mt7615_uni_txd *uni_txd;
0067     struct mt7615_mcu_txd *mcu_txd;
0068     u8 seq, q_idx, pkt_fmt;
0069     __le32 *txd;
0070     u32 val;
0071 
0072     /* TODO: make dynamic based on msg type */
0073     dev->mt76.mcu.timeout = 20 * HZ;
0074 
0075     seq = ++dev->mt76.mcu.msg_seq & 0xf;
0076     if (!seq)
0077         seq = ++dev->mt76.mcu.msg_seq & 0xf;
0078     if (wait_seq)
0079         *wait_seq = seq;
0080 
0081     txd_len = cmd & __MCU_CMD_FIELD_UNI ? sizeof(*uni_txd) : sizeof(*mcu_txd);
0082     txd = (__le32 *)skb_push(skb, txd_len);
0083 
0084     if (cmd != MCU_CMD(FW_SCATTER)) {
0085         q_idx = MT_TX_MCU_PORT_RX_Q0;
0086         pkt_fmt = MT_TX_TYPE_CMD;
0087     } else {
0088         q_idx = MT_TX_MCU_PORT_RX_FWDL;
0089         pkt_fmt = MT_TX_TYPE_FW;
0090     }
0091 
0092     val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len) |
0093           FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_MCU) |
0094           FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
0095     txd[0] = cpu_to_le32(val);
0096 
0097     val = MT_TXD1_LONG_FORMAT |
0098           FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_CMD) |
0099           FIELD_PREP(MT_TXD1_PKT_FMT, pkt_fmt);
0100     txd[1] = cpu_to_le32(val);
0101 
0102     if (cmd & __MCU_CMD_FIELD_UNI) {
0103         uni_txd = (struct mt7615_uni_txd *)txd;
0104         uni_txd->len = cpu_to_le16(skb->len - sizeof(uni_txd->txd));
0105         uni_txd->option = MCU_CMD_UNI_EXT_ACK;
0106         uni_txd->cid = cpu_to_le16(mcu_cmd);
0107         uni_txd->s2d_index = MCU_S2D_H2N;
0108         uni_txd->pkt_type = MCU_PKT_ID;
0109         uni_txd->seq = seq;
0110 
0111         return;
0112     }
0113 
0114     mcu_txd = (struct mt7615_mcu_txd *)txd;
0115     mcu_txd->len = cpu_to_le16(skb->len - sizeof(mcu_txd->txd));
0116     mcu_txd->pq_id = cpu_to_le16(MCU_PQ_ID(MT_TX_PORT_IDX_MCU, q_idx));
0117     mcu_txd->s2d_index = MCU_S2D_H2N;
0118     mcu_txd->pkt_type = MCU_PKT_ID;
0119     mcu_txd->seq = seq;
0120     mcu_txd->cid = mcu_cmd;
0121     mcu_txd->ext_cid = FIELD_GET(__MCU_CMD_FIELD_EXT_ID, cmd);
0122 
0123     if (mcu_txd->ext_cid || (cmd & __MCU_CMD_FIELD_CE)) {
0124         if (cmd & __MCU_CMD_FIELD_QUERY)
0125             mcu_txd->set_query = MCU_Q_QUERY;
0126         else
0127             mcu_txd->set_query = MCU_Q_SET;
0128         mcu_txd->ext_cid_ack = !!mcu_txd->ext_cid;
0129     } else {
0130         mcu_txd->set_query = MCU_Q_NA;
0131     }
0132 }
0133 EXPORT_SYMBOL_GPL(mt7615_mcu_fill_msg);
0134 
0135 int mt7615_mcu_parse_response(struct mt76_dev *mdev, int cmd,
0136                   struct sk_buff *skb, int seq)
0137 {
0138     struct mt7615_mcu_rxd *rxd;
0139     int ret = 0;
0140 
0141     if (!skb) {
0142         dev_err(mdev->dev, "Message %08x (seq %d) timeout\n",
0143             cmd, seq);
0144         return -ETIMEDOUT;
0145     }
0146 
0147     rxd = (struct mt7615_mcu_rxd *)skb->data;
0148     if (seq != rxd->seq)
0149         return -EAGAIN;
0150 
0151     if (cmd == MCU_CMD(PATCH_SEM_CONTROL)) {
0152         skb_pull(skb, sizeof(*rxd) - 4);
0153         ret = *skb->data;
0154     } else if (cmd == MCU_EXT_CMD(THERMAL_CTRL)) {
0155         skb_pull(skb, sizeof(*rxd));
0156         ret = le32_to_cpu(*(__le32 *)skb->data);
0157     } else if (cmd == MCU_EXT_QUERY(RF_REG_ACCESS)) {
0158         skb_pull(skb, sizeof(*rxd));
0159         ret = le32_to_cpu(*(__le32 *)&skb->data[8]);
0160     } else if (cmd == MCU_UNI_CMD(DEV_INFO_UPDATE) ||
0161            cmd == MCU_UNI_CMD(BSS_INFO_UPDATE) ||
0162            cmd == MCU_UNI_CMD(STA_REC_UPDATE) ||
0163            cmd == MCU_UNI_CMD(HIF_CTRL) ||
0164            cmd == MCU_UNI_CMD(OFFLOAD) ||
0165            cmd == MCU_UNI_CMD(SUSPEND)) {
0166         struct mt7615_mcu_uni_event *event;
0167 
0168         skb_pull(skb, sizeof(*rxd));
0169         event = (struct mt7615_mcu_uni_event *)skb->data;
0170         ret = le32_to_cpu(event->status);
0171     } else if (cmd == MCU_CE_QUERY(REG_READ)) {
0172         struct mt7615_mcu_reg_event *event;
0173 
0174         skb_pull(skb, sizeof(*rxd));
0175         event = (struct mt7615_mcu_reg_event *)skb->data;
0176         ret = (int)le32_to_cpu(event->val);
0177     }
0178 
0179     return ret;
0180 }
0181 EXPORT_SYMBOL_GPL(mt7615_mcu_parse_response);
0182 
0183 static int
0184 mt7615_mcu_send_message(struct mt76_dev *mdev, struct sk_buff *skb,
0185             int cmd, int *seq)
0186 {
0187     struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
0188     enum mt76_mcuq_id qid;
0189 
0190     mt7615_mcu_fill_msg(dev, skb, cmd, seq);
0191     if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state))
0192         qid = MT_MCUQ_WM;
0193     else
0194         qid = MT_MCUQ_FWDL;
0195 
0196     return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0);
0197 }
0198 
0199 u32 mt7615_rf_rr(struct mt7615_dev *dev, u32 wf, u32 reg)
0200 {
0201     struct {
0202         __le32 wifi_stream;
0203         __le32 address;
0204         __le32 data;
0205     } req = {
0206         .wifi_stream = cpu_to_le32(wf),
0207         .address = cpu_to_le32(reg),
0208     };
0209 
0210     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_QUERY(RF_REG_ACCESS),
0211                  &req, sizeof(req), true);
0212 }
0213 
0214 int mt7615_rf_wr(struct mt7615_dev *dev, u32 wf, u32 reg, u32 val)
0215 {
0216     struct {
0217         __le32 wifi_stream;
0218         __le32 address;
0219         __le32 data;
0220     } req = {
0221         .wifi_stream = cpu_to_le32(wf),
0222         .address = cpu_to_le32(reg),
0223         .data = cpu_to_le32(val),
0224     };
0225 
0226     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RF_REG_ACCESS),
0227                  &req, sizeof(req), false);
0228 }
0229 
0230 void mt7622_trigger_hif_int(struct mt7615_dev *dev, bool en)
0231 {
0232     if (!is_mt7622(&dev->mt76))
0233         return;
0234 
0235     regmap_update_bits(dev->infracfg, MT_INFRACFG_MISC,
0236                MT_INFRACFG_MISC_AP2CONN_WAKE,
0237                !en * MT_INFRACFG_MISC_AP2CONN_WAKE);
0238 }
0239 EXPORT_SYMBOL_GPL(mt7622_trigger_hif_int);
0240 
0241 static int mt7615_mcu_drv_pmctrl(struct mt7615_dev *dev)
0242 {
0243     struct mt76_phy *mphy = &dev->mt76.phy;
0244     struct mt76_connac_pm *pm = &dev->pm;
0245     struct mt76_dev *mdev = &dev->mt76;
0246     u32 addr;
0247     int err;
0248 
0249     if (is_mt7663(mdev)) {
0250         /* Clear firmware own via N9 eint */
0251         mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
0252         mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
0253 
0254         addr = MT_CONN_HIF_ON_LPCTL;
0255     } else {
0256         addr = MT_CFG_LPCR_HOST;
0257     }
0258 
0259     mt76_wr(dev, addr, MT_CFG_LPCR_HOST_DRV_OWN);
0260 
0261     mt7622_trigger_hif_int(dev, true);
0262 
0263     err = !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000);
0264 
0265     mt7622_trigger_hif_int(dev, false);
0266 
0267     if (err) {
0268         dev_err(mdev->dev, "driver own failed\n");
0269         return -ETIMEDOUT;
0270     }
0271 
0272     clear_bit(MT76_STATE_PM, &mphy->state);
0273 
0274     pm->stats.last_wake_event = jiffies;
0275     pm->stats.doze_time += pm->stats.last_wake_event -
0276                    pm->stats.last_doze_event;
0277 
0278     return 0;
0279 }
0280 
0281 static int mt7615_mcu_lp_drv_pmctrl(struct mt7615_dev *dev)
0282 {
0283     struct mt76_phy *mphy = &dev->mt76.phy;
0284     struct mt76_connac_pm *pm = &dev->pm;
0285     int i, err = 0;
0286 
0287     mutex_lock(&pm->mutex);
0288 
0289     if (!test_bit(MT76_STATE_PM, &mphy->state))
0290         goto out;
0291 
0292     for (i = 0; i < MT7615_DRV_OWN_RETRY_COUNT; i++) {
0293         mt76_wr(dev, MT_PCIE_DOORBELL_PUSH, MT_CFG_LPCR_HOST_DRV_OWN);
0294         if (mt76_poll_msec(dev, MT_CONN_HIF_ON_LPCTL,
0295                    MT_CFG_LPCR_HOST_FW_OWN, 0, 50))
0296             break;
0297     }
0298 
0299     if (i == MT7615_DRV_OWN_RETRY_COUNT) {
0300         dev_err(dev->mt76.dev, "driver own failed\n");
0301         err = -EIO;
0302         goto out;
0303     }
0304     clear_bit(MT76_STATE_PM, &mphy->state);
0305 
0306     pm->stats.last_wake_event = jiffies;
0307     pm->stats.doze_time += pm->stats.last_wake_event -
0308                    pm->stats.last_doze_event;
0309 out:
0310     mutex_unlock(&pm->mutex);
0311 
0312     return err;
0313 }
0314 
0315 static int mt7615_mcu_fw_pmctrl(struct mt7615_dev *dev)
0316 {
0317     struct mt76_phy *mphy = &dev->mt76.phy;
0318     struct mt76_connac_pm *pm = &dev->pm;
0319     int err = 0;
0320     u32 addr;
0321 
0322     mutex_lock(&pm->mutex);
0323 
0324     if (mt76_connac_skip_fw_pmctrl(mphy, pm))
0325         goto out;
0326 
0327     mt7622_trigger_hif_int(dev, true);
0328 
0329     addr = is_mt7663(&dev->mt76) ? MT_CONN_HIF_ON_LPCTL : MT_CFG_LPCR_HOST;
0330     mt76_wr(dev, addr, MT_CFG_LPCR_HOST_FW_OWN);
0331 
0332     if (is_mt7622(&dev->mt76) &&
0333         !mt76_poll_msec(dev, addr, MT_CFG_LPCR_HOST_FW_OWN,
0334                 MT_CFG_LPCR_HOST_FW_OWN, 3000)) {
0335         dev_err(dev->mt76.dev, "Timeout for firmware own\n");
0336         clear_bit(MT76_STATE_PM, &mphy->state);
0337         err = -EIO;
0338     }
0339 
0340     mt7622_trigger_hif_int(dev, false);
0341     if (!err) {
0342         pm->stats.last_doze_event = jiffies;
0343         pm->stats.awake_time += pm->stats.last_doze_event -
0344                     pm->stats.last_wake_event;
0345     }
0346 out:
0347     mutex_unlock(&pm->mutex);
0348 
0349     return err;
0350 }
0351 
0352 static void
0353 mt7615_mcu_csa_finish(void *priv, u8 *mac, struct ieee80211_vif *vif)
0354 {
0355     if (vif->bss_conf.csa_active)
0356         ieee80211_csa_finish(vif);
0357 }
0358 
0359 static void
0360 mt7615_mcu_rx_csa_notify(struct mt7615_dev *dev, struct sk_buff *skb)
0361 {
0362     struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
0363     struct mt76_phy *mphy = &dev->mt76.phy;
0364     struct mt7615_mcu_csa_notify *c;
0365 
0366     c = (struct mt7615_mcu_csa_notify *)skb->data;
0367 
0368     if (c->omac_idx > EXT_BSSID_MAX)
0369         return;
0370 
0371     if (ext_phy && ext_phy->omac_mask & BIT_ULL(c->omac_idx))
0372         mphy = dev->mt76.phys[MT_BAND1];
0373 
0374     ieee80211_iterate_active_interfaces_atomic(mphy->hw,
0375             IEEE80211_IFACE_ITER_RESUME_ALL,
0376             mt7615_mcu_csa_finish, mphy->hw);
0377 }
0378 
0379 static void
0380 mt7615_mcu_rx_radar_detected(struct mt7615_dev *dev, struct sk_buff *skb)
0381 {
0382     struct mt76_phy *mphy = &dev->mt76.phy;
0383     struct mt7615_mcu_rdd_report *r;
0384 
0385     r = (struct mt7615_mcu_rdd_report *)skb->data;
0386 
0387     if (!dev->radar_pattern.n_pulses && !r->long_detected &&
0388         !r->constant_prf_detected && !r->staggered_prf_detected)
0389         return;
0390 
0391     if (r->band_idx && dev->mt76.phys[MT_BAND1])
0392         mphy = dev->mt76.phys[MT_BAND1];
0393 
0394     if (mt76_phy_dfs_state(mphy) < MT_DFS_STATE_CAC)
0395         return;
0396 
0397     ieee80211_radar_detected(mphy->hw);
0398     dev->hw_pattern++;
0399 }
0400 
0401 static void
0402 mt7615_mcu_rx_log_message(struct mt7615_dev *dev, struct sk_buff *skb)
0403 {
0404     struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
0405     const char *data = (char *)&rxd[1];
0406     const char *type;
0407 
0408     switch (rxd->s2d_index) {
0409     case 0:
0410         type = "N9";
0411         break;
0412     case 2:
0413         type = "CR4";
0414         break;
0415     default:
0416         type = "unknown";
0417         break;
0418     }
0419 
0420     wiphy_info(mt76_hw(dev)->wiphy, "%s: %.*s", type,
0421            (int)(skb->len - sizeof(*rxd)), data);
0422 }
0423 
0424 static void
0425 mt7615_mcu_rx_ext_event(struct mt7615_dev *dev, struct sk_buff *skb)
0426 {
0427     struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
0428 
0429     switch (rxd->ext_eid) {
0430     case MCU_EXT_EVENT_RDD_REPORT:
0431         mt7615_mcu_rx_radar_detected(dev, skb);
0432         break;
0433     case MCU_EXT_EVENT_CSA_NOTIFY:
0434         mt7615_mcu_rx_csa_notify(dev, skb);
0435         break;
0436     case MCU_EXT_EVENT_FW_LOG_2_HOST:
0437         mt7615_mcu_rx_log_message(dev, skb);
0438         break;
0439     default:
0440         break;
0441     }
0442 }
0443 
0444 static void
0445 mt7615_mcu_scan_event(struct mt7615_dev *dev, struct sk_buff *skb)
0446 {
0447     u8 *seq_num = skb->data + sizeof(struct mt7615_mcu_rxd);
0448     struct mt7615_phy *phy;
0449     struct mt76_phy *mphy;
0450 
0451     if (*seq_num & BIT(7) && dev->mt76.phys[MT_BAND1])
0452         mphy = dev->mt76.phys[MT_BAND1];
0453     else
0454         mphy = &dev->mt76.phy;
0455 
0456     phy = (struct mt7615_phy *)mphy->priv;
0457 
0458     spin_lock_bh(&dev->mt76.lock);
0459     __skb_queue_tail(&phy->scan_event_list, skb);
0460     spin_unlock_bh(&dev->mt76.lock);
0461 
0462     ieee80211_queue_delayed_work(mphy->hw, &phy->scan_work,
0463                      MT7615_HW_SCAN_TIMEOUT);
0464 }
0465 
0466 static void
0467 mt7615_mcu_roc_event(struct mt7615_dev *dev, struct sk_buff *skb)
0468 {
0469     struct mt7615_roc_tlv *event;
0470     struct mt7615_phy *phy;
0471     struct mt76_phy *mphy;
0472     int duration;
0473 
0474     skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
0475     event = (struct mt7615_roc_tlv *)skb->data;
0476 
0477     if (event->dbdc_band && dev->mt76.phys[MT_BAND1])
0478         mphy = dev->mt76.phys[MT_BAND1];
0479     else
0480         mphy = &dev->mt76.phy;
0481 
0482     ieee80211_ready_on_channel(mphy->hw);
0483 
0484     phy = (struct mt7615_phy *)mphy->priv;
0485     phy->roc_grant = true;
0486     wake_up(&phy->roc_wait);
0487 
0488     duration = le32_to_cpu(event->max_interval);
0489     mod_timer(&phy->roc_timer,
0490           round_jiffies_up(jiffies + msecs_to_jiffies(duration)));
0491 }
0492 
0493 static void
0494 mt7615_mcu_beacon_loss_event(struct mt7615_dev *dev, struct sk_buff *skb)
0495 {
0496     struct mt76_connac_beacon_loss_event *event;
0497     struct mt76_phy *mphy;
0498     u8 band_idx = 0; /* DBDC support */
0499 
0500     skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
0501     event = (struct mt76_connac_beacon_loss_event *)skb->data;
0502     if (band_idx && dev->mt76.phys[MT_BAND1])
0503         mphy = dev->mt76.phys[MT_BAND1];
0504     else
0505         mphy = &dev->mt76.phy;
0506 
0507     ieee80211_iterate_active_interfaces_atomic(mphy->hw,
0508                     IEEE80211_IFACE_ITER_RESUME_ALL,
0509                     mt76_connac_mcu_beacon_loss_iter,
0510                     event);
0511 }
0512 
0513 static void
0514 mt7615_mcu_bss_event(struct mt7615_dev *dev, struct sk_buff *skb)
0515 {
0516     struct mt76_connac_mcu_bss_event *event;
0517     struct mt76_phy *mphy;
0518     u8 band_idx = 0; /* DBDC support */
0519 
0520     skb_pull(skb, sizeof(struct mt7615_mcu_rxd));
0521     event = (struct mt76_connac_mcu_bss_event *)skb->data;
0522 
0523     if (band_idx && dev->mt76.phys[MT_BAND1])
0524         mphy = dev->mt76.phys[MT_BAND1];
0525     else
0526         mphy = &dev->mt76.phy;
0527 
0528     if (event->is_absent)
0529         ieee80211_stop_queues(mphy->hw);
0530     else
0531         ieee80211_wake_queues(mphy->hw);
0532 }
0533 
0534 static void
0535 mt7615_mcu_rx_unsolicited_event(struct mt7615_dev *dev, struct sk_buff *skb)
0536 {
0537     struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
0538 
0539     switch (rxd->eid) {
0540     case MCU_EVENT_EXT:
0541         mt7615_mcu_rx_ext_event(dev, skb);
0542         break;
0543     case MCU_EVENT_BSS_BEACON_LOSS:
0544         mt7615_mcu_beacon_loss_event(dev, skb);
0545         break;
0546     case MCU_EVENT_ROC:
0547         mt7615_mcu_roc_event(dev, skb);
0548         break;
0549     case MCU_EVENT_SCHED_SCAN_DONE:
0550     case MCU_EVENT_SCAN_DONE:
0551         mt7615_mcu_scan_event(dev, skb);
0552         return;
0553     case MCU_EVENT_BSS_ABSENCE:
0554         mt7615_mcu_bss_event(dev, skb);
0555         break;
0556     case MCU_EVENT_COREDUMP:
0557         mt76_connac_mcu_coredump_event(&dev->mt76, skb,
0558                            &dev->coredump);
0559         return;
0560     default:
0561         break;
0562     }
0563     dev_kfree_skb(skb);
0564 }
0565 
0566 void mt7615_mcu_rx_event(struct mt7615_dev *dev, struct sk_buff *skb)
0567 {
0568     struct mt7615_mcu_rxd *rxd = (struct mt7615_mcu_rxd *)skb->data;
0569 
0570     if (rxd->ext_eid == MCU_EXT_EVENT_THERMAL_PROTECT ||
0571         rxd->ext_eid == MCU_EXT_EVENT_FW_LOG_2_HOST ||
0572         rxd->ext_eid == MCU_EXT_EVENT_ASSERT_DUMP ||
0573         rxd->ext_eid == MCU_EXT_EVENT_PS_SYNC ||
0574         rxd->eid == MCU_EVENT_BSS_BEACON_LOSS ||
0575         rxd->eid == MCU_EVENT_SCHED_SCAN_DONE ||
0576         rxd->eid == MCU_EVENT_BSS_ABSENCE ||
0577         rxd->eid == MCU_EVENT_SCAN_DONE ||
0578         rxd->eid == MCU_EVENT_COREDUMP ||
0579         rxd->eid == MCU_EVENT_ROC ||
0580         !rxd->seq)
0581         mt7615_mcu_rx_unsolicited_event(dev, skb);
0582     else
0583         mt76_mcu_rx_event(&dev->mt76, skb);
0584 }
0585 
0586 static int
0587 mt7615_mcu_muar_config(struct mt7615_dev *dev, struct ieee80211_vif *vif,
0588                bool bssid, bool enable)
0589 {
0590     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0591     u32 idx = mvif->mt76.omac_idx - REPEATER_BSSID_START;
0592     u32 mask = dev->omac_mask >> 32 & ~BIT(idx);
0593     const u8 *addr = vif->addr;
0594     struct {
0595         u8 mode;
0596         u8 force_clear;
0597         u8 clear_bitmap[8];
0598         u8 entry_count;
0599         u8 write;
0600 
0601         u8 index;
0602         u8 bssid;
0603         u8 addr[ETH_ALEN];
0604     } __packed req = {
0605         .mode = !!mask || enable,
0606         .entry_count = 1,
0607         .write = 1,
0608 
0609         .index = idx * 2 + bssid,
0610     };
0611 
0612     if (bssid)
0613         addr = vif->bss_conf.bssid;
0614 
0615     if (enable)
0616         ether_addr_copy(req.addr, addr);
0617 
0618     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(MUAR_UPDATE),
0619                  &req, sizeof(req), true);
0620 }
0621 
0622 static int
0623 mt7615_mcu_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
0624            bool enable)
0625 {
0626     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0627     struct mt7615_dev *dev = phy->dev;
0628     struct {
0629         struct req_hdr {
0630             u8 omac_idx;
0631             u8 band_idx;
0632             __le16 tlv_num;
0633             u8 is_tlv_append;
0634             u8 rsv[3];
0635         } __packed hdr;
0636         struct req_tlv {
0637             __le16 tag;
0638             __le16 len;
0639             u8 active;
0640             u8 band_idx;
0641             u8 omac_addr[ETH_ALEN];
0642         } __packed tlv;
0643     } data = {
0644         .hdr = {
0645             .omac_idx = mvif->mt76.omac_idx,
0646             .band_idx = mvif->mt76.band_idx,
0647             .tlv_num = cpu_to_le16(1),
0648             .is_tlv_append = 1,
0649         },
0650         .tlv = {
0651             .tag = cpu_to_le16(DEV_INFO_ACTIVE),
0652             .len = cpu_to_le16(sizeof(struct req_tlv)),
0653             .active = enable,
0654             .band_idx = mvif->mt76.band_idx,
0655         },
0656     };
0657 
0658     if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
0659         return mt7615_mcu_muar_config(dev, vif, false, enable);
0660 
0661     memcpy(data.tlv.omac_addr, vif->addr, ETH_ALEN);
0662     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DEV_INFO_UPDATE),
0663                  &data, sizeof(data), true);
0664 }
0665 
0666 static int
0667 mt7615_mcu_add_beacon_offload(struct mt7615_dev *dev,
0668                   struct ieee80211_hw *hw,
0669                   struct ieee80211_vif *vif, bool enable)
0670 {
0671     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0672     struct mt76_wcid *wcid = &dev->mt76.global_wcid;
0673     struct ieee80211_mutable_offsets offs;
0674     struct ieee80211_tx_info *info;
0675     struct req {
0676         u8 omac_idx;
0677         u8 enable;
0678         u8 wlan_idx;
0679         u8 band_idx;
0680         u8 pkt_type;
0681         u8 need_pre_tbtt_int;
0682         __le16 csa_ie_pos;
0683         __le16 pkt_len;
0684         __le16 tim_ie_pos;
0685         u8 pkt[512];
0686         u8 csa_cnt;
0687         /* bss color change */
0688         u8 bcc_cnt;
0689         __le16 bcc_ie_pos;
0690     } __packed req = {
0691         .omac_idx = mvif->mt76.omac_idx,
0692         .enable = enable,
0693         .wlan_idx = wcid->idx,
0694         .band_idx = mvif->mt76.band_idx,
0695     };
0696     struct sk_buff *skb;
0697 
0698     if (!enable)
0699         goto out;
0700 
0701     skb = ieee80211_beacon_get_template(hw, vif, &offs, 0);
0702     if (!skb)
0703         return -EINVAL;
0704 
0705     if (skb->len > 512 - MT_TXD_SIZE) {
0706         dev_err(dev->mt76.dev, "Bcn size limit exceed\n");
0707         dev_kfree_skb(skb);
0708         return -EINVAL;
0709     }
0710 
0711     info = IEEE80211_SKB_CB(skb);
0712     info->hw_queue |= FIELD_PREP(MT_TX_HW_QUEUE_PHY, mvif->mt76.band_idx);
0713 
0714     mt7615_mac_write_txwi(dev, (__le32 *)(req.pkt), skb, wcid, NULL,
0715                   0, NULL, 0, true);
0716     memcpy(req.pkt + MT_TXD_SIZE, skb->data, skb->len);
0717     req.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
0718     req.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
0719     if (offs.cntdwn_counter_offs[0]) {
0720         u16 csa_offs;
0721 
0722         csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
0723         req.csa_ie_pos = cpu_to_le16(csa_offs);
0724         req.csa_cnt = skb->data[offs.cntdwn_counter_offs[0]];
0725     }
0726     dev_kfree_skb(skb);
0727 
0728 out:
0729     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(BCN_OFFLOAD), &req,
0730                  sizeof(req), true);
0731 }
0732 
0733 static int
0734 mt7615_mcu_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
0735 {
0736     return mt76_connac_mcu_set_pm(&dev->mt76, band, state);
0737 }
0738 
0739 static int
0740 mt7615_mcu_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
0741            struct ieee80211_sta *sta, bool enable)
0742 {
0743     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0744     struct mt7615_dev *dev = phy->dev;
0745     struct sk_buff *skb;
0746 
0747     if (mvif->mt76.omac_idx >= REPEATER_BSSID_START)
0748         mt7615_mcu_muar_config(dev, vif, true, enable);
0749 
0750     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76, NULL);
0751     if (IS_ERR(skb))
0752         return PTR_ERR(skb);
0753 
0754     if (enable)
0755         mt76_connac_mcu_bss_omac_tlv(skb, vif);
0756 
0757     mt76_connac_mcu_bss_basic_tlv(skb, vif, sta, phy->mt76,
0758                       mvif->sta.wcid.idx, enable);
0759 
0760     if (enable && mvif->mt76.omac_idx >= EXT_BSSID_START &&
0761         mvif->mt76.omac_idx < REPEATER_BSSID_START)
0762         mt76_connac_mcu_bss_ext_tlv(skb, &mvif->mt76);
0763 
0764     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
0765                      MCU_EXT_CMD(BSS_INFO_UPDATE), true);
0766 }
0767 
0768 static int
0769 mt7615_mcu_wtbl_tx_ba(struct mt7615_dev *dev,
0770               struct ieee80211_ampdu_params *params,
0771               bool enable)
0772 {
0773     struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
0774     struct mt7615_vif *mvif = msta->vif;
0775     struct wtbl_req_hdr *wtbl_hdr;
0776     struct sk_buff *skb = NULL;
0777     int err;
0778 
0779     wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
0780                           WTBL_SET, NULL, &skb);
0781     if (IS_ERR(wtbl_hdr))
0782         return PTR_ERR(wtbl_hdr);
0783 
0784     mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, true,
0785                     NULL, wtbl_hdr);
0786 
0787     err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
0788                     MCU_EXT_CMD(WTBL_UPDATE), true);
0789     if (err < 0)
0790         return err;
0791 
0792     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
0793                         &msta->wcid);
0794     if (IS_ERR(skb))
0795         return PTR_ERR(skb);
0796 
0797     mt76_connac_mcu_sta_ba_tlv(skb, params, enable, true);
0798 
0799     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
0800                      MCU_EXT_CMD(STA_REC_UPDATE), true);
0801 }
0802 
0803 static int
0804 mt7615_mcu_wtbl_rx_ba(struct mt7615_dev *dev,
0805               struct ieee80211_ampdu_params *params,
0806               bool enable)
0807 {
0808     struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
0809     struct mt7615_vif *mvif = msta->vif;
0810     struct wtbl_req_hdr *wtbl_hdr;
0811     struct sk_buff *skb;
0812     int err;
0813 
0814     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
0815                         &msta->wcid);
0816     if (IS_ERR(skb))
0817         return PTR_ERR(skb);
0818 
0819     mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
0820 
0821     err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
0822                     MCU_EXT_CMD(STA_REC_UPDATE), true);
0823     if (err < 0 || !enable)
0824         return err;
0825 
0826     skb = NULL;
0827     wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
0828                           WTBL_SET, NULL, &skb);
0829     if (IS_ERR(wtbl_hdr))
0830         return PTR_ERR(wtbl_hdr);
0831 
0832     mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
0833                     NULL, wtbl_hdr);
0834 
0835     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
0836                      MCU_EXT_CMD(WTBL_UPDATE), true);
0837 }
0838 
0839 static int
0840 mt7615_mcu_wtbl_sta_add(struct mt7615_phy *phy, struct ieee80211_vif *vif,
0841             struct ieee80211_sta *sta, bool enable)
0842 {
0843     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0844     struct sk_buff *skb, *sskb, *wskb = NULL;
0845     struct mt7615_dev *dev = phy->dev;
0846     struct wtbl_req_hdr *wtbl_hdr;
0847     struct mt7615_sta *msta;
0848     bool new_entry = true;
0849     int cmd, err;
0850 
0851     msta = sta ? (struct mt7615_sta *)sta->drv_priv : &mvif->sta;
0852 
0853     sskb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
0854                          &msta->wcid);
0855     if (IS_ERR(sskb))
0856         return PTR_ERR(sskb);
0857 
0858     if (!sta) {
0859         if (mvif->sta_added)
0860             new_entry = false;
0861         else
0862             mvif->sta_added = true;
0863     }
0864     mt76_connac_mcu_sta_basic_tlv(sskb, vif, sta, enable, new_entry);
0865     if (enable && sta)
0866         mt76_connac_mcu_sta_tlv(phy->mt76, sskb, sta, vif, 0,
0867                     MT76_STA_INFO_STATE_ASSOC);
0868 
0869     wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
0870                           WTBL_RESET_AND_SET, NULL,
0871                           &wskb);
0872     if (IS_ERR(wtbl_hdr))
0873         return PTR_ERR(wtbl_hdr);
0874 
0875     if (enable) {
0876         mt76_connac_mcu_wtbl_generic_tlv(&dev->mt76, wskb, vif, sta,
0877                          NULL, wtbl_hdr);
0878         if (sta)
0879             mt76_connac_mcu_wtbl_ht_tlv(&dev->mt76, wskb, sta,
0880                             NULL, wtbl_hdr, true, true);
0881         mt76_connac_mcu_wtbl_hdr_trans_tlv(wskb, vif, &msta->wcid,
0882                            NULL, wtbl_hdr);
0883     }
0884 
0885     cmd = enable ? MCU_EXT_CMD(WTBL_UPDATE) : MCU_EXT_CMD(STA_REC_UPDATE);
0886     skb = enable ? wskb : sskb;
0887 
0888     err = mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
0889     if (err < 0) {
0890         skb = enable ? sskb : wskb;
0891         dev_kfree_skb(skb);
0892 
0893         return err;
0894     }
0895 
0896     cmd = enable ? MCU_EXT_CMD(STA_REC_UPDATE) : MCU_EXT_CMD(WTBL_UPDATE);
0897     skb = enable ? sskb : wskb;
0898 
0899     return mt76_mcu_skb_send_msg(&dev->mt76, skb, cmd, true);
0900 }
0901 
0902 static int
0903 mt7615_mcu_wtbl_update_hdr_trans(struct mt7615_dev *dev,
0904                  struct ieee80211_vif *vif,
0905                  struct ieee80211_sta *sta)
0906 {
0907     return mt76_connac_mcu_wtbl_update_hdr_trans(&dev->mt76, vif, sta);
0908 }
0909 
0910 static const struct mt7615_mcu_ops wtbl_update_ops = {
0911     .add_beacon_offload = mt7615_mcu_add_beacon_offload,
0912     .set_pm_state = mt7615_mcu_ctrl_pm_state,
0913     .add_dev_info = mt7615_mcu_add_dev,
0914     .add_bss_info = mt7615_mcu_add_bss,
0915     .add_tx_ba = mt7615_mcu_wtbl_tx_ba,
0916     .add_rx_ba = mt7615_mcu_wtbl_rx_ba,
0917     .sta_add = mt7615_mcu_wtbl_sta_add,
0918     .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
0919     .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
0920     .set_sta_decap_offload = mt7615_mcu_wtbl_update_hdr_trans,
0921 };
0922 
0923 static int
0924 mt7615_mcu_sta_ba(struct mt7615_dev *dev,
0925           struct ieee80211_ampdu_params *params,
0926           bool enable, bool tx)
0927 {
0928     struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
0929     struct mt7615_vif *mvif = msta->vif;
0930     struct wtbl_req_hdr *wtbl_hdr;
0931     struct tlv *sta_wtbl;
0932     struct sk_buff *skb;
0933 
0934     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
0935                         &msta->wcid);
0936     if (IS_ERR(skb))
0937         return PTR_ERR(skb);
0938 
0939     mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx);
0940 
0941     sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL, sizeof(struct tlv));
0942 
0943     wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
0944                           WTBL_SET, sta_wtbl, &skb);
0945     if (IS_ERR(wtbl_hdr))
0946         return PTR_ERR(wtbl_hdr);
0947 
0948     mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, tx,
0949                     sta_wtbl, wtbl_hdr);
0950 
0951     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
0952                      MCU_EXT_CMD(STA_REC_UPDATE), true);
0953 }
0954 
0955 static int
0956 mt7615_mcu_sta_tx_ba(struct mt7615_dev *dev,
0957              struct ieee80211_ampdu_params *params,
0958              bool enable)
0959 {
0960     return mt7615_mcu_sta_ba(dev, params, enable, true);
0961 }
0962 
0963 static int
0964 mt7615_mcu_sta_rx_ba(struct mt7615_dev *dev,
0965              struct ieee80211_ampdu_params *params,
0966              bool enable)
0967 {
0968     return mt7615_mcu_sta_ba(dev, params, enable, false);
0969 }
0970 
0971 static int
0972 __mt7615_mcu_add_sta(struct mt76_phy *phy, struct ieee80211_vif *vif,
0973              struct ieee80211_sta *sta, bool enable, int cmd,
0974              bool offload_fw)
0975 {
0976     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
0977     struct mt76_sta_cmd_info info = {
0978         .sta = sta,
0979         .vif = vif,
0980         .offload_fw = offload_fw,
0981         .enable = enable,
0982         .newly = true,
0983         .cmd = cmd,
0984     };
0985 
0986     info.wcid = sta ? (struct mt76_wcid *)sta->drv_priv : &mvif->sta.wcid;
0987     return mt76_connac_mcu_sta_cmd(phy, &info);
0988 }
0989 
0990 static int
0991 mt7615_mcu_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
0992            struct ieee80211_sta *sta, bool enable)
0993 {
0994     return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
0995                     MCU_EXT_CMD(STA_REC_UPDATE), false);
0996 }
0997 
0998 static int
0999 mt7615_mcu_sta_update_hdr_trans(struct mt7615_dev *dev,
1000                 struct ieee80211_vif *vif,
1001                 struct ieee80211_sta *sta)
1002 {
1003     struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1004 
1005     return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1006                             vif, &msta->wcid,
1007                             MCU_EXT_CMD(STA_REC_UPDATE));
1008 }
1009 
1010 static const struct mt7615_mcu_ops sta_update_ops = {
1011     .add_beacon_offload = mt7615_mcu_add_beacon_offload,
1012     .set_pm_state = mt7615_mcu_ctrl_pm_state,
1013     .add_dev_info = mt7615_mcu_add_dev,
1014     .add_bss_info = mt7615_mcu_add_bss,
1015     .add_tx_ba = mt7615_mcu_sta_tx_ba,
1016     .add_rx_ba = mt7615_mcu_sta_rx_ba,
1017     .sta_add = mt7615_mcu_add_sta,
1018     .set_drv_ctrl = mt7615_mcu_drv_pmctrl,
1019     .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1020     .set_sta_decap_offload = mt7615_mcu_sta_update_hdr_trans,
1021 };
1022 
1023 static int
1024 mt7615_mcu_uni_ctrl_pm_state(struct mt7615_dev *dev, int band, int state)
1025 {
1026     return 0;
1027 }
1028 
1029 static int
1030 mt7615_mcu_uni_add_beacon_offload(struct mt7615_dev *dev,
1031                   struct ieee80211_hw *hw,
1032                   struct ieee80211_vif *vif,
1033                   bool enable)
1034 {
1035     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1036     struct mt76_wcid *wcid = &dev->mt76.global_wcid;
1037     struct ieee80211_mutable_offsets offs;
1038     struct {
1039         struct req_hdr {
1040             u8 bss_idx;
1041             u8 pad[3];
1042         } __packed hdr;
1043         struct bcn_content_tlv {
1044             __le16 tag;
1045             __le16 len;
1046             __le16 tim_ie_pos;
1047             __le16 csa_ie_pos;
1048             __le16 bcc_ie_pos;
1049             /* 0: disable beacon offload
1050              * 1: enable beacon offload
1051              * 2: update probe respond offload
1052              */
1053             u8 enable;
1054             /* 0: legacy format (TXD + payload)
1055              * 1: only cap field IE
1056              */
1057             u8 type;
1058             __le16 pkt_len;
1059             u8 pkt[512];
1060         } __packed beacon_tlv;
1061     } req = {
1062         .hdr = {
1063             .bss_idx = mvif->mt76.idx,
1064         },
1065         .beacon_tlv = {
1066             .tag = cpu_to_le16(UNI_BSS_INFO_BCN_CONTENT),
1067             .len = cpu_to_le16(sizeof(struct bcn_content_tlv)),
1068             .enable = enable,
1069         },
1070     };
1071     struct sk_buff *skb;
1072 
1073     if (!enable)
1074         goto out;
1075 
1076     skb = ieee80211_beacon_get_template(mt76_hw(dev), vif, &offs, 0);
1077     if (!skb)
1078         return -EINVAL;
1079 
1080     if (skb->len > 512 - MT_TXD_SIZE) {
1081         dev_err(dev->mt76.dev, "beacon size limit exceed\n");
1082         dev_kfree_skb(skb);
1083         return -EINVAL;
1084     }
1085 
1086     mt7615_mac_write_txwi(dev, (__le32 *)(req.beacon_tlv.pkt), skb,
1087                   wcid, NULL, 0, NULL, 0, true);
1088     memcpy(req.beacon_tlv.pkt + MT_TXD_SIZE, skb->data, skb->len);
1089     req.beacon_tlv.pkt_len = cpu_to_le16(MT_TXD_SIZE + skb->len);
1090     req.beacon_tlv.tim_ie_pos = cpu_to_le16(MT_TXD_SIZE + offs.tim_offset);
1091 
1092     if (offs.cntdwn_counter_offs[0]) {
1093         u16 csa_offs;
1094 
1095         csa_offs = MT_TXD_SIZE + offs.cntdwn_counter_offs[0] - 4;
1096         req.beacon_tlv.csa_ie_pos = cpu_to_le16(csa_offs);
1097     }
1098     dev_kfree_skb(skb);
1099 
1100 out:
1101     return mt76_mcu_send_msg(&dev->mt76, MCU_UNI_CMD(BSS_INFO_UPDATE),
1102                  &req, sizeof(req), true);
1103 }
1104 
1105 static int
1106 mt7615_mcu_uni_add_dev(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1107                bool enable)
1108 {
1109     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1110 
1111     return mt76_connac_mcu_uni_add_dev(phy->mt76, vif, &mvif->sta.wcid,
1112                        enable);
1113 }
1114 
1115 static int
1116 mt7615_mcu_uni_add_bss(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1117                struct ieee80211_sta *sta, bool enable)
1118 {
1119     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
1120 
1121     return mt76_connac_mcu_uni_add_bss(phy->mt76, vif, &mvif->sta.wcid,
1122                        enable);
1123 }
1124 
1125 static inline int
1126 mt7615_mcu_uni_add_sta(struct mt7615_phy *phy, struct ieee80211_vif *vif,
1127                struct ieee80211_sta *sta, bool enable)
1128 {
1129     return __mt7615_mcu_add_sta(phy->mt76, vif, sta, enable,
1130                     MCU_UNI_CMD(STA_REC_UPDATE), true);
1131 }
1132 
1133 static int
1134 mt7615_mcu_uni_tx_ba(struct mt7615_dev *dev,
1135              struct ieee80211_ampdu_params *params,
1136              bool enable)
1137 {
1138     struct mt7615_sta *sta = (struct mt7615_sta *)params->sta->drv_priv;
1139 
1140     return mt76_connac_mcu_sta_ba(&dev->mt76, &sta->vif->mt76, params,
1141                       MCU_UNI_CMD(STA_REC_UPDATE), enable,
1142                       true);
1143 }
1144 
1145 static int
1146 mt7615_mcu_uni_rx_ba(struct mt7615_dev *dev,
1147              struct ieee80211_ampdu_params *params,
1148              bool enable)
1149 {
1150     struct mt7615_sta *msta = (struct mt7615_sta *)params->sta->drv_priv;
1151     struct mt7615_vif *mvif = msta->vif;
1152     struct wtbl_req_hdr *wtbl_hdr;
1153     struct tlv *sta_wtbl;
1154     struct sk_buff *skb;
1155     int err;
1156 
1157     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1158                         &msta->wcid);
1159     if (IS_ERR(skb))
1160         return PTR_ERR(skb);
1161 
1162     mt76_connac_mcu_sta_ba_tlv(skb, params, enable, false);
1163 
1164     err = mt76_mcu_skb_send_msg(&dev->mt76, skb,
1165                     MCU_UNI_CMD(STA_REC_UPDATE), true);
1166     if (err < 0 || !enable)
1167         return err;
1168 
1169     skb = mt76_connac_mcu_alloc_sta_req(&dev->mt76, &mvif->mt76,
1170                         &msta->wcid);
1171     if (IS_ERR(skb))
1172         return PTR_ERR(skb);
1173 
1174     sta_wtbl = mt76_connac_mcu_add_tlv(skb, STA_REC_WTBL,
1175                        sizeof(struct tlv));
1176 
1177     wtbl_hdr = mt76_connac_mcu_alloc_wtbl_req(&dev->mt76, &msta->wcid,
1178                           WTBL_SET, sta_wtbl, &skb);
1179     if (IS_ERR(wtbl_hdr))
1180         return PTR_ERR(wtbl_hdr);
1181 
1182     mt76_connac_mcu_wtbl_ba_tlv(&dev->mt76, skb, params, enable, false,
1183                     sta_wtbl, wtbl_hdr);
1184 
1185     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1186                      MCU_UNI_CMD(STA_REC_UPDATE), true);
1187 }
1188 
1189 static int
1190 mt7615_mcu_sta_uni_update_hdr_trans(struct mt7615_dev *dev,
1191                     struct ieee80211_vif *vif,
1192                     struct ieee80211_sta *sta)
1193 {
1194     struct mt7615_sta *msta = (struct mt7615_sta *)sta->drv_priv;
1195 
1196     return mt76_connac_mcu_sta_update_hdr_trans(&dev->mt76,
1197                             vif, &msta->wcid,
1198                             MCU_UNI_CMD(STA_REC_UPDATE));
1199 }
1200 
1201 static const struct mt7615_mcu_ops uni_update_ops = {
1202     .add_beacon_offload = mt7615_mcu_uni_add_beacon_offload,
1203     .set_pm_state = mt7615_mcu_uni_ctrl_pm_state,
1204     .add_dev_info = mt7615_mcu_uni_add_dev,
1205     .add_bss_info = mt7615_mcu_uni_add_bss,
1206     .add_tx_ba = mt7615_mcu_uni_tx_ba,
1207     .add_rx_ba = mt7615_mcu_uni_rx_ba,
1208     .sta_add = mt7615_mcu_uni_add_sta,
1209     .set_drv_ctrl = mt7615_mcu_lp_drv_pmctrl,
1210     .set_fw_ctrl = mt7615_mcu_fw_pmctrl,
1211     .set_sta_decap_offload = mt7615_mcu_sta_uni_update_hdr_trans,
1212 };
1213 
1214 int mt7615_mcu_restart(struct mt76_dev *dev)
1215 {
1216     return mt76_mcu_send_msg(dev, MCU_CMD(RESTART_DL_REQ), NULL, 0, true);
1217 }
1218 EXPORT_SYMBOL_GPL(mt7615_mcu_restart);
1219 
1220 static int mt7615_load_patch(struct mt7615_dev *dev, u32 addr, const char *name)
1221 {
1222     const struct mt7615_patch_hdr *hdr;
1223     const struct firmware *fw = NULL;
1224     int len, ret, sem;
1225 
1226     ret = firmware_request_nowarn(&fw, name, dev->mt76.dev);
1227     if (ret)
1228         return ret;
1229 
1230     if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
1231         dev_err(dev->mt76.dev, "Invalid firmware\n");
1232         ret = -EINVAL;
1233         goto release_fw;
1234     }
1235 
1236     sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, true);
1237     switch (sem) {
1238     case PATCH_IS_DL:
1239         goto release_fw;
1240     case PATCH_NOT_DL_SEM_SUCCESS:
1241         break;
1242     default:
1243         dev_err(dev->mt76.dev, "Failed to get patch semaphore\n");
1244         ret = -EAGAIN;
1245         goto release_fw;
1246     }
1247 
1248     hdr = (const struct mt7615_patch_hdr *)(fw->data);
1249 
1250     dev_info(dev->mt76.dev, "HW/SW Version: 0x%x, Build Time: %.16s\n",
1251          be32_to_cpu(hdr->hw_sw_ver), hdr->build_date);
1252 
1253     len = fw->size - sizeof(*hdr);
1254 
1255     ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1256                         DL_MODE_NEED_RSP);
1257     if (ret) {
1258         dev_err(dev->mt76.dev, "Download request failed\n");
1259         goto out;
1260     }
1261 
1262     ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1263                      fw->data + sizeof(*hdr), len);
1264     if (ret) {
1265         dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1266         goto out;
1267     }
1268 
1269     ret = mt76_connac_mcu_start_patch(&dev->mt76);
1270     if (ret)
1271         dev_err(dev->mt76.dev, "Failed to start patch\n");
1272 
1273 out:
1274     sem = mt76_connac_mcu_patch_sem_ctrl(&dev->mt76, false);
1275     switch (sem) {
1276     case PATCH_REL_SEM_SUCCESS:
1277         break;
1278     default:
1279         ret = -EAGAIN;
1280         dev_err(dev->mt76.dev, "Failed to release patch semaphore\n");
1281         break;
1282     }
1283 
1284 release_fw:
1285     release_firmware(fw);
1286 
1287     return ret;
1288 }
1289 
1290 static int
1291 mt7615_mcu_send_ram_firmware(struct mt7615_dev *dev,
1292                  const struct mt7615_fw_trailer *hdr,
1293                  const u8 *data, bool is_cr4)
1294 {
1295     int n_region = is_cr4 ? CR4_REGION_NUM : N9_REGION_NUM;
1296     int err, i, offset = 0;
1297     u32 len, addr, mode;
1298 
1299     for (i = 0; i < n_region; i++) {
1300         mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1301                            hdr[i].feature_set, is_cr4);
1302         len = le32_to_cpu(hdr[i].len) + IMG_CRC_LEN;
1303         addr = le32_to_cpu(hdr[i].addr);
1304 
1305         err = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1306                             mode);
1307         if (err) {
1308             dev_err(dev->mt76.dev, "Download request failed\n");
1309             return err;
1310         }
1311 
1312         err = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1313                          data + offset, len);
1314         if (err) {
1315             dev_err(dev->mt76.dev, "Failed to send firmware to device\n");
1316             return err;
1317         }
1318 
1319         offset += len;
1320     }
1321 
1322     return 0;
1323 }
1324 
1325 static int mt7615_load_n9(struct mt7615_dev *dev, const char *name)
1326 {
1327     const struct mt7615_fw_trailer *hdr;
1328     const struct firmware *fw;
1329     int ret;
1330 
1331     ret = request_firmware(&fw, name, dev->mt76.dev);
1332     if (ret)
1333         return ret;
1334 
1335     if (!fw || !fw->data || fw->size < N9_REGION_NUM * sizeof(*hdr)) {
1336         dev_err(dev->mt76.dev, "Invalid firmware\n");
1337         ret = -EINVAL;
1338         goto out;
1339     }
1340 
1341     hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1342                     N9_REGION_NUM * sizeof(*hdr));
1343 
1344     dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1345          hdr->fw_ver, hdr->build_date);
1346 
1347     ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, false);
1348     if (ret)
1349         goto out;
1350 
1351     ret = mt76_connac_mcu_start_firmware(&dev->mt76,
1352                          le32_to_cpu(hdr->addr),
1353                          FW_START_OVERRIDE);
1354     if (ret) {
1355         dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1356         goto out;
1357     }
1358 
1359     snprintf(dev->mt76.hw->wiphy->fw_version,
1360          sizeof(dev->mt76.hw->wiphy->fw_version),
1361          "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1362 
1363     if (!is_mt7615(&dev->mt76)) {
1364         dev->fw_ver = MT7615_FIRMWARE_V2;
1365         dev->mcu_ops = &sta_update_ops;
1366     } else {
1367         dev->fw_ver = MT7615_FIRMWARE_V1;
1368         dev->mcu_ops = &wtbl_update_ops;
1369     }
1370 
1371 out:
1372     release_firmware(fw);
1373     return ret;
1374 }
1375 
1376 static int mt7615_load_cr4(struct mt7615_dev *dev, const char *name)
1377 {
1378     const struct mt7615_fw_trailer *hdr;
1379     const struct firmware *fw;
1380     int ret;
1381 
1382     ret = request_firmware(&fw, name, dev->mt76.dev);
1383     if (ret)
1384         return ret;
1385 
1386     if (!fw || !fw->data || fw->size < CR4_REGION_NUM * sizeof(*hdr)) {
1387         dev_err(dev->mt76.dev, "Invalid firmware\n");
1388         ret = -EINVAL;
1389         goto out;
1390     }
1391 
1392     hdr = (const struct mt7615_fw_trailer *)(fw->data + fw->size -
1393                     CR4_REGION_NUM * sizeof(*hdr));
1394 
1395     dev_info(dev->mt76.dev, "CR4 Firmware Version: %.10s, Build Time: %.15s\n",
1396          hdr->fw_ver, hdr->build_date);
1397 
1398     ret = mt7615_mcu_send_ram_firmware(dev, hdr, fw->data, true);
1399     if (ret)
1400         goto out;
1401 
1402     ret = mt76_connac_mcu_start_firmware(&dev->mt76, 0,
1403                          FW_START_WORKING_PDA_CR4);
1404     if (ret) {
1405         dev_err(dev->mt76.dev, "Failed to start CR4 firmware\n");
1406         goto out;
1407     }
1408 
1409 out:
1410     release_firmware(fw);
1411 
1412     return ret;
1413 }
1414 
1415 static int mt7615_load_ram(struct mt7615_dev *dev)
1416 {
1417     int ret;
1418 
1419     ret = mt7615_load_n9(dev, MT7615_FIRMWARE_N9);
1420     if (ret)
1421         return ret;
1422 
1423     return mt7615_load_cr4(dev, MT7615_FIRMWARE_CR4);
1424 }
1425 
1426 static int mt7615_load_firmware(struct mt7615_dev *dev)
1427 {
1428     int ret;
1429     u32 val;
1430 
1431     val = mt76_get_field(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE);
1432 
1433     if (val != FW_STATE_FW_DOWNLOAD) {
1434         dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1435         return -EIO;
1436     }
1437 
1438     ret = mt7615_load_patch(dev, MT7615_PATCH_ADDRESS, MT7615_ROM_PATCH);
1439     if (ret)
1440         return ret;
1441 
1442     ret = mt7615_load_ram(dev);
1443     if (ret)
1444         return ret;
1445 
1446     if (!mt76_poll_msec(dev, MT_TOP_MISC2, MT_TOP_MISC2_FW_STATE,
1447                 FIELD_PREP(MT_TOP_MISC2_FW_STATE,
1448                        FW_STATE_RDY), 500)) {
1449         dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1450         return -EIO;
1451     }
1452 
1453     return 0;
1454 }
1455 
1456 static int mt7622_load_firmware(struct mt7615_dev *dev)
1457 {
1458     int ret;
1459     u32 val;
1460 
1461     mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1462 
1463     val = mt76_get_field(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE);
1464     if (val != FW_STATE_FW_DOWNLOAD) {
1465         dev_err(dev->mt76.dev, "Firmware is not ready for download\n");
1466         return -EIO;
1467     }
1468 
1469     ret = mt7615_load_patch(dev, MT7622_PATCH_ADDRESS, MT7622_ROM_PATCH);
1470     if (ret)
1471         return ret;
1472 
1473     ret = mt7615_load_n9(dev, MT7622_FIRMWARE_N9);
1474     if (ret)
1475         return ret;
1476 
1477     if (!mt76_poll_msec(dev, MT_TOP_OFF_RSV, MT_TOP_OFF_RSV_FW_STATE,
1478                 FIELD_PREP(MT_TOP_OFF_RSV_FW_STATE,
1479                        FW_STATE_NORMAL_TRX), 1500)) {
1480         dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1481         return -EIO;
1482     }
1483 
1484     mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1485 
1486     return 0;
1487 }
1488 
1489 int mt7615_mcu_fw_log_2_host(struct mt7615_dev *dev, u8 ctrl)
1490 {
1491     struct {
1492         u8 ctrl_val;
1493         u8 pad[3];
1494     } data = {
1495         .ctrl_val = ctrl
1496     };
1497 
1498     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(FW_LOG_2_HOST),
1499                  &data, sizeof(data), true);
1500 }
1501 
1502 static int mt7615_mcu_cal_cache_apply(struct mt7615_dev *dev)
1503 {
1504     struct {
1505         bool cache_enable;
1506         u8 pad[3];
1507     } data = {
1508         .cache_enable = true
1509     };
1510 
1511     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(CAL_CACHE), &data,
1512                  sizeof(data), false);
1513 }
1514 
1515 static int mt7663_load_n9(struct mt7615_dev *dev, const char *name)
1516 {
1517     u32 offset = 0, override_addr = 0, flag = FW_START_DLYCAL;
1518     const struct mt76_connac2_fw_trailer *hdr;
1519     const struct mt7663_fw_buf *buf;
1520     const struct firmware *fw;
1521     const u8 *base_addr;
1522     int i, ret;
1523 
1524     ret = request_firmware(&fw, name, dev->mt76.dev);
1525     if (ret)
1526         return ret;
1527 
1528     if (!fw || !fw->data || fw->size < FW_V3_COMMON_TAILER_SIZE) {
1529         dev_err(dev->mt76.dev, "Invalid firmware\n");
1530         ret = -EINVAL;
1531         goto out;
1532     }
1533 
1534     hdr = (const void *)(fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE);
1535     dev_info(dev->mt76.dev, "N9 Firmware Version: %.10s, Build Time: %.15s\n",
1536          hdr->fw_ver, hdr->build_date);
1537     dev_info(dev->mt76.dev, "Region number: 0x%x\n", hdr->n_region);
1538 
1539     base_addr = fw->data + fw->size - FW_V3_COMMON_TAILER_SIZE;
1540     for (i = 0; i < hdr->n_region; i++) {
1541         u32 shift = (hdr->n_region - i) * FW_V3_REGION_TAILER_SIZE;
1542         u32 len, addr, mode;
1543 
1544         dev_info(dev->mt76.dev, "Parsing tailer Region: %d\n", i);
1545 
1546         buf = (const struct mt7663_fw_buf *)(base_addr - shift);
1547         mode = mt76_connac_mcu_gen_dl_mode(&dev->mt76,
1548                            buf->feature_set, false);
1549         addr = le32_to_cpu(buf->img_dest_addr);
1550         len = le32_to_cpu(buf->img_size);
1551 
1552         ret = mt76_connac_mcu_init_download(&dev->mt76, addr, len,
1553                             mode);
1554         if (ret) {
1555             dev_err(dev->mt76.dev, "Download request failed\n");
1556             goto out;
1557         }
1558 
1559         ret = mt76_mcu_send_firmware(&dev->mt76, MCU_CMD(FW_SCATTER),
1560                          fw->data + offset, len);
1561         if (ret) {
1562             dev_err(dev->mt76.dev, "Failed to send firmware\n");
1563             goto out;
1564         }
1565 
1566         offset += le32_to_cpu(buf->img_size);
1567         if (buf->feature_set & DL_MODE_VALID_RAM_ENTRY) {
1568             override_addr = le32_to_cpu(buf->img_dest_addr);
1569             dev_info(dev->mt76.dev, "Region %d, override_addr = 0x%08x\n",
1570                  i, override_addr);
1571         }
1572     }
1573 
1574     if (override_addr)
1575         flag |= FW_START_OVERRIDE;
1576 
1577     dev_info(dev->mt76.dev, "override_addr = 0x%08x, option = %d\n",
1578          override_addr, flag);
1579 
1580     ret = mt76_connac_mcu_start_firmware(&dev->mt76, override_addr, flag);
1581     if (ret) {
1582         dev_err(dev->mt76.dev, "Failed to start N9 firmware\n");
1583         goto out;
1584     }
1585 
1586     snprintf(dev->mt76.hw->wiphy->fw_version,
1587          sizeof(dev->mt76.hw->wiphy->fw_version),
1588          "%.10s-%.15s", hdr->fw_ver, hdr->build_date);
1589 
1590 out:
1591     release_firmware(fw);
1592 
1593     return ret;
1594 }
1595 
1596 static int
1597 mt7663_load_rom_patch(struct mt7615_dev *dev, const char **n9_firmware)
1598 {
1599     const char *selected_rom, *secondary_rom = MT7663_ROM_PATCH;
1600     const char *primary_rom = MT7663_OFFLOAD_ROM_PATCH;
1601     int ret;
1602 
1603     if (!prefer_offload_fw) {
1604         secondary_rom = MT7663_OFFLOAD_ROM_PATCH;
1605         primary_rom = MT7663_ROM_PATCH;
1606     }
1607     selected_rom = primary_rom;
1608 
1609     ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS, primary_rom);
1610     if (ret) {
1611         dev_info(dev->mt76.dev, "%s not found, switching to %s",
1612              primary_rom, secondary_rom);
1613         ret = mt7615_load_patch(dev, MT7663_PATCH_ADDRESS,
1614                     secondary_rom);
1615         if (ret) {
1616             dev_err(dev->mt76.dev, "failed to load %s",
1617                 secondary_rom);
1618             return ret;
1619         }
1620         selected_rom = secondary_rom;
1621     }
1622 
1623     if (!strcmp(selected_rom, MT7663_OFFLOAD_ROM_PATCH)) {
1624         *n9_firmware = MT7663_OFFLOAD_FIRMWARE_N9;
1625         dev->fw_ver = MT7615_FIRMWARE_V3;
1626         dev->mcu_ops = &uni_update_ops;
1627     } else {
1628         *n9_firmware = MT7663_FIRMWARE_N9;
1629         dev->fw_ver = MT7615_FIRMWARE_V2;
1630         dev->mcu_ops = &sta_update_ops;
1631     }
1632 
1633     return 0;
1634 }
1635 
1636 int __mt7663_load_firmware(struct mt7615_dev *dev)
1637 {
1638     const char *n9_firmware;
1639     int ret;
1640 
1641     ret = mt76_get_field(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY);
1642     if (ret) {
1643         dev_dbg(dev->mt76.dev, "Firmware is already download\n");
1644         return -EIO;
1645     }
1646 
1647     ret = mt7663_load_rom_patch(dev, &n9_firmware);
1648     if (ret)
1649         return ret;
1650 
1651     ret = mt7663_load_n9(dev, n9_firmware);
1652     if (ret)
1653         return ret;
1654 
1655     if (!mt76_poll_msec(dev, MT_CONN_ON_MISC, MT_TOP_MISC2_FW_N9_RDY,
1656                 MT_TOP_MISC2_FW_N9_RDY, 1500)) {
1657         ret = mt76_get_field(dev, MT_CONN_ON_MISC,
1658                      MT7663_TOP_MISC2_FW_STATE);
1659         dev_err(dev->mt76.dev, "Timeout for initializing firmware\n");
1660         return -EIO;
1661     }
1662 
1663 #ifdef CONFIG_PM
1664     if (mt7615_firmware_offload(dev))
1665         dev->mt76.hw->wiphy->wowlan = &mt76_connac_wowlan_support;
1666 #endif /* CONFIG_PM */
1667 
1668     dev_dbg(dev->mt76.dev, "Firmware init done\n");
1669 
1670     return 0;
1671 }
1672 EXPORT_SYMBOL_GPL(__mt7663_load_firmware);
1673 
1674 static int mt7663_load_firmware(struct mt7615_dev *dev)
1675 {
1676     int ret;
1677 
1678     mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1679 
1680     ret = __mt7663_load_firmware(dev);
1681     if (ret)
1682         return ret;
1683 
1684     mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_BYPASS_TX_SCH);
1685 
1686     return 0;
1687 }
1688 
1689 int mt7615_mcu_init(struct mt7615_dev *dev)
1690 {
1691     static const struct mt76_mcu_ops mt7615_mcu_ops = {
1692         .headroom = sizeof(struct mt7615_mcu_txd),
1693         .mcu_skb_send_msg = mt7615_mcu_send_message,
1694         .mcu_parse_response = mt7615_mcu_parse_response,
1695         .mcu_restart = mt7615_mcu_restart,
1696     };
1697     int ret;
1698 
1699     dev->mt76.mcu_ops = &mt7615_mcu_ops,
1700 
1701     ret = mt7615_mcu_drv_pmctrl(dev);
1702     if (ret)
1703         return ret;
1704 
1705     switch (mt76_chip(&dev->mt76)) {
1706     case 0x7622:
1707         ret = mt7622_load_firmware(dev);
1708         break;
1709     case 0x7663:
1710         ret = mt7663_load_firmware(dev);
1711         break;
1712     default:
1713         ret = mt7615_load_firmware(dev);
1714         break;
1715     }
1716     if (ret)
1717         return ret;
1718 
1719     mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_FWDL], false);
1720     dev_dbg(dev->mt76.dev, "Firmware init done\n");
1721     set_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state);
1722 
1723     if (dev->dbdc_support) {
1724         ret = mt7615_mcu_cal_cache_apply(dev);
1725         if (ret)
1726             return ret;
1727     }
1728 
1729     return mt7615_mcu_fw_log_2_host(dev, 0);
1730 }
1731 EXPORT_SYMBOL_GPL(mt7615_mcu_init);
1732 
1733 void mt7615_mcu_exit(struct mt7615_dev *dev)
1734 {
1735     __mt76_mcu_restart(&dev->mt76);
1736     mt7615_mcu_set_fw_ctrl(dev);
1737     skb_queue_purge(&dev->mt76.mcu.res_q);
1738 }
1739 EXPORT_SYMBOL_GPL(mt7615_mcu_exit);
1740 
1741 int mt7615_mcu_set_eeprom(struct mt7615_dev *dev)
1742 {
1743     struct {
1744         u8 buffer_mode;
1745         u8 content_format;
1746         __le16 len;
1747     } __packed req_hdr = {
1748         .buffer_mode = 1,
1749     };
1750     u8 *eep = (u8 *)dev->mt76.eeprom.data;
1751     struct sk_buff *skb;
1752     int eep_len, offset;
1753 
1754     switch (mt76_chip(&dev->mt76)) {
1755     case 0x7622:
1756         eep_len = MT7622_EE_MAX - MT_EE_NIC_CONF_0;
1757         offset = MT_EE_NIC_CONF_0;
1758         break;
1759     case 0x7663:
1760         eep_len = MT7663_EE_MAX - MT_EE_CHIP_ID;
1761         req_hdr.content_format = 1;
1762         offset = MT_EE_CHIP_ID;
1763         break;
1764     default:
1765         eep_len = MT7615_EE_MAX - MT_EE_NIC_CONF_0;
1766         offset = MT_EE_NIC_CONF_0;
1767         break;
1768     }
1769 
1770     req_hdr.len = cpu_to_le16(eep_len);
1771 
1772     skb = mt76_mcu_msg_alloc(&dev->mt76, NULL, sizeof(req_hdr) + eep_len);
1773     if (!skb)
1774         return -ENOMEM;
1775 
1776     skb_put_data(skb, &req_hdr, sizeof(req_hdr));
1777     skb_put_data(skb, eep + offset, eep_len);
1778 
1779     return mt76_mcu_skb_send_msg(&dev->mt76, skb,
1780                      MCU_EXT_CMD(EFUSE_BUFFER_MODE), true);
1781 }
1782 
1783 int mt7615_mcu_set_wmm(struct mt7615_dev *dev, u8 queue,
1784                const struct ieee80211_tx_queue_params *params)
1785 {
1786 #define WMM_AIFS_SET    BIT(0)
1787 #define WMM_CW_MIN_SET  BIT(1)
1788 #define WMM_CW_MAX_SET  BIT(2)
1789 #define WMM_TXOP_SET    BIT(3)
1790 #define WMM_PARAM_SET   (WMM_AIFS_SET | WMM_CW_MIN_SET | \
1791              WMM_CW_MAX_SET | WMM_TXOP_SET)
1792     struct req_data {
1793         u8 number;
1794         u8 rsv[3];
1795         u8 queue;
1796         u8 valid;
1797         u8 aifs;
1798         u8 cw_min;
1799         __le16 cw_max;
1800         __le16 txop;
1801     } __packed req = {
1802         .number = 1,
1803         .queue = queue,
1804         .valid = WMM_PARAM_SET,
1805         .aifs = params->aifs,
1806         .cw_min = 5,
1807         .cw_max = cpu_to_le16(10),
1808         .txop = cpu_to_le16(params->txop),
1809     };
1810 
1811     if (params->cw_min)
1812         req.cw_min = fls(params->cw_min);
1813     if (params->cw_max)
1814         req.cw_max = cpu_to_le16(fls(params->cw_max));
1815 
1816     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(EDCA_UPDATE),
1817                  &req, sizeof(req), true);
1818 }
1819 
1820 int mt7615_mcu_set_dbdc(struct mt7615_dev *dev)
1821 {
1822     struct mt7615_phy *ext_phy = mt7615_ext_phy(dev);
1823     struct dbdc_entry {
1824         u8 type;
1825         u8 index;
1826         u8 band;
1827         u8 _rsv;
1828     };
1829     struct {
1830         u8 enable;
1831         u8 num;
1832         u8 _rsv[2];
1833         struct dbdc_entry entry[64];
1834     } req = {
1835         .enable = !!ext_phy,
1836     };
1837     int i;
1838 
1839     if (!ext_phy)
1840         goto out;
1841 
1842 #define ADD_DBDC_ENTRY(_type, _idx, _band)      \
1843     do { \
1844         req.entry[req.num].type = _type;        \
1845         req.entry[req.num].index = _idx;        \
1846         req.entry[req.num++].band = _band;      \
1847     } while (0)
1848 
1849     for (i = 0; i < 4; i++) {
1850         bool band = !!(ext_phy->omac_mask & BIT_ULL(i));
1851 
1852         ADD_DBDC_ENTRY(DBDC_TYPE_BSS, i, band);
1853     }
1854 
1855     for (i = 0; i < 14; i++) {
1856         bool band = !!(ext_phy->omac_mask & BIT_ULL(0x11 + i));
1857 
1858         ADD_DBDC_ENTRY(DBDC_TYPE_MBSS, i, band);
1859     }
1860 
1861     ADD_DBDC_ENTRY(DBDC_TYPE_MU, 0, 1);
1862 
1863     for (i = 0; i < 3; i++)
1864         ADD_DBDC_ENTRY(DBDC_TYPE_BF, i, 1);
1865 
1866     ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 0, 0);
1867     ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 1, 0);
1868     ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 2, 1);
1869     ADD_DBDC_ENTRY(DBDC_TYPE_WMM, 3, 1);
1870 
1871     ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 0, 0);
1872     ADD_DBDC_ENTRY(DBDC_TYPE_MGMT, 1, 1);
1873 
1874 out:
1875     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(DBDC_CTRL), &req,
1876                  sizeof(req), true);
1877 }
1878 
1879 int mt7615_mcu_del_wtbl_all(struct mt7615_dev *dev)
1880 {
1881     struct wtbl_req_hdr req = {
1882         .operation = WTBL_RESET_ALL,
1883     };
1884 
1885     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(WTBL_UPDATE),
1886                  &req, sizeof(req), true);
1887 }
1888 
1889 int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val)
1890 {
1891     struct {
1892         __le16 tag;
1893         __le16 min_lpn;
1894     } req = {
1895         .tag = cpu_to_le16(0x1),
1896         .min_lpn = cpu_to_le16(val),
1897     };
1898 
1899     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1900                  &req, sizeof(req), true);
1901 }
1902 
1903 int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
1904                 const struct mt7615_dfs_pulse *pulse)
1905 {
1906     struct {
1907         __le16 tag;
1908         __le32 max_width;   /* us */
1909         __le32 max_pwr;     /* dbm */
1910         __le32 min_pwr;     /* dbm */
1911         __le32 min_stgr_pri;    /* us */
1912         __le32 max_stgr_pri;    /* us */
1913         __le32 min_cr_pri;  /* us */
1914         __le32 max_cr_pri;  /* us */
1915     } req = {
1916         .tag = cpu_to_le16(0x3),
1917 #define __req_field(field) .field = cpu_to_le32(pulse->field)
1918         __req_field(max_width),
1919         __req_field(max_pwr),
1920         __req_field(min_pwr),
1921         __req_field(min_stgr_pri),
1922         __req_field(max_stgr_pri),
1923         __req_field(min_cr_pri),
1924         __req_field(max_cr_pri),
1925 #undef  __req_field
1926     };
1927 
1928     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1929                  &req, sizeof(req), true);
1930 }
1931 
1932 int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
1933                 const struct mt7615_dfs_pattern *pattern)
1934 {
1935     struct {
1936         __le16 tag;
1937         __le16 radar_type;
1938         u8 enb;
1939         u8 stgr;
1940         u8 min_crpn;
1941         u8 max_crpn;
1942         u8 min_crpr;
1943         u8 min_pw;
1944         u8 max_pw;
1945         __le32 min_pri;
1946         __le32 max_pri;
1947         u8 min_crbn;
1948         u8 max_crbn;
1949         u8 min_stgpn;
1950         u8 max_stgpn;
1951         u8 min_stgpr;
1952     } req = {
1953         .tag = cpu_to_le16(0x2),
1954         .radar_type = cpu_to_le16(index),
1955 #define __req_field_u8(field) .field = pattern->field
1956 #define __req_field_u32(field) .field = cpu_to_le32(pattern->field)
1957         __req_field_u8(enb),
1958         __req_field_u8(stgr),
1959         __req_field_u8(min_crpn),
1960         __req_field_u8(max_crpn),
1961         __req_field_u8(min_crpr),
1962         __req_field_u8(min_pw),
1963         __req_field_u8(max_pw),
1964         __req_field_u32(min_pri),
1965         __req_field_u32(max_pri),
1966         __req_field_u8(min_crbn),
1967         __req_field_u8(max_crbn),
1968         __req_field_u8(min_stgpn),
1969         __req_field_u8(max_stgpn),
1970         __req_field_u8(min_stgpr),
1971 #undef __req_field_u8
1972 #undef __req_field_u32
1973     };
1974 
1975     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RADAR_TH),
1976                  &req, sizeof(req), true);
1977 }
1978 
1979 int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev)
1980 {
1981     struct {
1982         u8 pulse_num;
1983         u8 rsv[3];
1984         struct {
1985             __le32 start_time;
1986             __le16 width;
1987             __le16 power;
1988         } pattern[32];
1989     } req = {
1990         .pulse_num = dev->radar_pattern.n_pulses,
1991     };
1992     u32 start_time = ktime_to_ms(ktime_get_boottime());
1993     int i;
1994 
1995     if (dev->radar_pattern.n_pulses > ARRAY_SIZE(req.pattern))
1996         return -EINVAL;
1997 
1998     /* TODO: add some noise here */
1999     for (i = 0; i < dev->radar_pattern.n_pulses; i++) {
2000         u32 ts = start_time + i * dev->radar_pattern.period;
2001 
2002         req.pattern[i].width = cpu_to_le16(dev->radar_pattern.width);
2003         req.pattern[i].power = cpu_to_le16(dev->radar_pattern.power);
2004         req.pattern[i].start_time = cpu_to_le32(ts);
2005     }
2006 
2007     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(SET_RDD_PATTERN),
2008                  &req, sizeof(req), false);
2009 }
2010 
2011 static void mt7615_mcu_set_txpower_sku(struct mt7615_phy *phy, u8 *sku)
2012 {
2013     struct mt76_phy *mphy = phy->mt76;
2014     struct ieee80211_hw *hw = mphy->hw;
2015     struct mt76_power_limits limits;
2016     s8 *limits_array = (s8 *)&limits;
2017     int n_chains = hweight8(mphy->antenna_mask);
2018     int tx_power = hw->conf.power_level * 2;
2019     int i;
2020     static const u8 sku_mapping[] = {
2021 #define SKU_FIELD(_type, _field) \
2022         [MT_SKU_##_type] = offsetof(struct mt76_power_limits, _field)
2023         SKU_FIELD(CCK_1_2, cck[0]),
2024         SKU_FIELD(CCK_55_11, cck[2]),
2025         SKU_FIELD(OFDM_6_9, ofdm[0]),
2026         SKU_FIELD(OFDM_12_18, ofdm[2]),
2027         SKU_FIELD(OFDM_24_36, ofdm[4]),
2028         SKU_FIELD(OFDM_48, ofdm[6]),
2029         SKU_FIELD(OFDM_54, ofdm[7]),
2030         SKU_FIELD(HT20_0_8, mcs[0][0]),
2031         SKU_FIELD(HT20_32, ofdm[0]),
2032         SKU_FIELD(HT20_1_2_9_10, mcs[0][1]),
2033         SKU_FIELD(HT20_3_4_11_12, mcs[0][3]),
2034         SKU_FIELD(HT20_5_13, mcs[0][5]),
2035         SKU_FIELD(HT20_6_14, mcs[0][6]),
2036         SKU_FIELD(HT20_7_15, mcs[0][7]),
2037         SKU_FIELD(HT40_0_8, mcs[1][0]),
2038         SKU_FIELD(HT40_32, ofdm[0]),
2039         SKU_FIELD(HT40_1_2_9_10, mcs[1][1]),
2040         SKU_FIELD(HT40_3_4_11_12, mcs[1][3]),
2041         SKU_FIELD(HT40_5_13, mcs[1][5]),
2042         SKU_FIELD(HT40_6_14, mcs[1][6]),
2043         SKU_FIELD(HT40_7_15, mcs[1][7]),
2044         SKU_FIELD(VHT20_0, mcs[0][0]),
2045         SKU_FIELD(VHT20_1_2, mcs[0][1]),
2046         SKU_FIELD(VHT20_3_4, mcs[0][3]),
2047         SKU_FIELD(VHT20_5_6, mcs[0][5]),
2048         SKU_FIELD(VHT20_7, mcs[0][7]),
2049         SKU_FIELD(VHT20_8, mcs[0][8]),
2050         SKU_FIELD(VHT20_9, mcs[0][9]),
2051         SKU_FIELD(VHT40_0, mcs[1][0]),
2052         SKU_FIELD(VHT40_1_2, mcs[1][1]),
2053         SKU_FIELD(VHT40_3_4, mcs[1][3]),
2054         SKU_FIELD(VHT40_5_6, mcs[1][5]),
2055         SKU_FIELD(VHT40_7, mcs[1][7]),
2056         SKU_FIELD(VHT40_8, mcs[1][8]),
2057         SKU_FIELD(VHT40_9, mcs[1][9]),
2058         SKU_FIELD(VHT80_0, mcs[2][0]),
2059         SKU_FIELD(VHT80_1_2, mcs[2][1]),
2060         SKU_FIELD(VHT80_3_4, mcs[2][3]),
2061         SKU_FIELD(VHT80_5_6, mcs[2][5]),
2062         SKU_FIELD(VHT80_7, mcs[2][7]),
2063         SKU_FIELD(VHT80_8, mcs[2][8]),
2064         SKU_FIELD(VHT80_9, mcs[2][9]),
2065         SKU_FIELD(VHT160_0, mcs[3][0]),
2066         SKU_FIELD(VHT160_1_2, mcs[3][1]),
2067         SKU_FIELD(VHT160_3_4, mcs[3][3]),
2068         SKU_FIELD(VHT160_5_6, mcs[3][5]),
2069         SKU_FIELD(VHT160_7, mcs[3][7]),
2070         SKU_FIELD(VHT160_8, mcs[3][8]),
2071         SKU_FIELD(VHT160_9, mcs[3][9]),
2072 #undef SKU_FIELD
2073     };
2074 
2075     tx_power = mt76_get_sar_power(mphy, mphy->chandef.chan, tx_power);
2076     tx_power -= mt76_tx_power_nss_delta(n_chains);
2077     tx_power = mt76_get_rate_power_limits(mphy, mphy->chandef.chan,
2078                           &limits, tx_power);
2079     mphy->txpower_cur = tx_power;
2080 
2081     if (is_mt7663(mphy->dev)) {
2082         memset(sku, tx_power, MT_SKU_4SS_DELTA + 1);
2083         return;
2084     }
2085 
2086     for (i = 0; i < MT_SKU_1SS_DELTA; i++)
2087         sku[i] = limits_array[sku_mapping[i]];
2088 
2089     for (i = 0; i < 4; i++) {
2090         int delta = 0;
2091 
2092         if (i < n_chains - 1)
2093             delta = mt76_tx_power_nss_delta(n_chains) -
2094                 mt76_tx_power_nss_delta(i + 1);
2095         sku[MT_SKU_1SS_DELTA + i] = delta;
2096     }
2097 }
2098 
2099 static u8 mt7615_mcu_chan_bw(struct cfg80211_chan_def *chandef)
2100 {
2101     static const u8 width_to_bw[] = {
2102         [NL80211_CHAN_WIDTH_40] = CMD_CBW_40MHZ,
2103         [NL80211_CHAN_WIDTH_80] = CMD_CBW_80MHZ,
2104         [NL80211_CHAN_WIDTH_80P80] = CMD_CBW_8080MHZ,
2105         [NL80211_CHAN_WIDTH_160] = CMD_CBW_160MHZ,
2106         [NL80211_CHAN_WIDTH_5] = CMD_CBW_5MHZ,
2107         [NL80211_CHAN_WIDTH_10] = CMD_CBW_10MHZ,
2108         [NL80211_CHAN_WIDTH_20] = CMD_CBW_20MHZ,
2109         [NL80211_CHAN_WIDTH_20_NOHT] = CMD_CBW_20MHZ,
2110     };
2111 
2112     if (chandef->width >= ARRAY_SIZE(width_to_bw))
2113         return 0;
2114 
2115     return width_to_bw[chandef->width];
2116 }
2117 
2118 int mt7615_mcu_set_chan_info(struct mt7615_phy *phy, int cmd)
2119 {
2120     struct mt7615_dev *dev = phy->dev;
2121     struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2122     int freq1 = chandef->center_freq1, freq2 = chandef->center_freq2;
2123     struct {
2124         u8 control_chan;
2125         u8 center_chan;
2126         u8 bw;
2127         u8 tx_streams;
2128         u8 rx_streams_mask;
2129         u8 switch_reason;
2130         u8 band_idx;
2131         /* for 80+80 only */
2132         u8 center_chan2;
2133         __le16 cac_case;
2134         u8 channel_band;
2135         u8 rsv0;
2136         __le32 outband_freq;
2137         u8 txpower_drop;
2138         u8 rsv1[3];
2139         u8 txpower_sku[53];
2140         u8 rsv2[3];
2141     } req = {
2142         .control_chan = chandef->chan->hw_value,
2143         .center_chan = ieee80211_frequency_to_channel(freq1),
2144         .tx_streams = hweight8(phy->mt76->antenna_mask),
2145         .rx_streams_mask = phy->mt76->chainmask,
2146         .center_chan2 = ieee80211_frequency_to_channel(freq2),
2147     };
2148 
2149     if (cmd == MCU_EXT_CMD(SET_RX_PATH) ||
2150         dev->mt76.hw->conf.flags & IEEE80211_CONF_MONITOR)
2151         req.switch_reason = CH_SWITCH_NORMAL;
2152     else if (phy->mt76->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
2153         req.switch_reason = CH_SWITCH_SCAN_BYPASS_DPD;
2154     else if (!cfg80211_reg_can_beacon(phy->mt76->hw->wiphy, chandef,
2155                       NL80211_IFTYPE_AP))
2156         req.switch_reason = CH_SWITCH_DFS;
2157     else
2158         req.switch_reason = CH_SWITCH_NORMAL;
2159 
2160     req.band_idx = phy != &dev->phy;
2161     req.bw = mt7615_mcu_chan_bw(chandef);
2162 
2163     if (mt76_testmode_enabled(phy->mt76))
2164         memset(req.txpower_sku, 0x3f, 49);
2165     else
2166         mt7615_mcu_set_txpower_sku(phy, req.txpower_sku);
2167 
2168     return mt76_mcu_send_msg(&dev->mt76, cmd, &req, sizeof(req), true);
2169 }
2170 
2171 int mt7615_mcu_get_temperature(struct mt7615_dev *dev)
2172 {
2173     struct {
2174         u8 action;
2175         u8 rsv[3];
2176     } req = {};
2177 
2178     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(THERMAL_CTRL),
2179                  &req, sizeof(req), true);
2180 }
2181 
2182 int mt7615_mcu_set_test_param(struct mt7615_dev *dev, u8 param, bool test_mode,
2183                   u32 val)
2184 {
2185     struct {
2186         u8 test_mode_en;
2187         u8 param_idx;
2188         u8 _rsv[2];
2189 
2190         __le32 value;
2191 
2192         u8 pad[8];
2193     } req = {
2194         .test_mode_en = test_mode,
2195         .param_idx = param,
2196         .value = cpu_to_le32(val),
2197     };
2198 
2199     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(ATE_CTRL),
2200                  &req, sizeof(req), false);
2201 }
2202 
2203 int mt7615_mcu_set_sku_en(struct mt7615_phy *phy, bool enable)
2204 {
2205     struct mt7615_dev *dev = phy->dev;
2206     struct {
2207         u8 format_id;
2208         u8 sku_enable;
2209         u8 band_idx;
2210         u8 rsv;
2211     } req = {
2212         .format_id = 0,
2213         .band_idx = phy != &dev->phy,
2214         .sku_enable = enable,
2215     };
2216 
2217     return mt76_mcu_send_msg(&dev->mt76,
2218                  MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
2219                  &req, sizeof(req), true);
2220 }
2221 
2222 static int mt7615_find_freq_idx(const u16 *freqs, int n_freqs, u16 cur)
2223 {
2224     int i;
2225 
2226     for (i = 0; i < n_freqs; i++)
2227         if (cur == freqs[i])
2228             return i;
2229 
2230     return -1;
2231 }
2232 
2233 static int mt7615_dcoc_freq_idx(u16 freq, u8 bw)
2234 {
2235     static const u16 freq_list[] = {
2236         4980, 5805, 5905, 5190,
2237         5230, 5270, 5310, 5350,
2238         5390, 5430, 5470, 5510,
2239         5550, 5590, 5630, 5670,
2240         5710, 5755, 5795, 5835,
2241         5875, 5210, 5290, 5370,
2242         5450, 5530, 5610, 5690,
2243         5775, 5855
2244     };
2245     static const u16 freq_bw40[] = {
2246         5190, 5230, 5270, 5310,
2247         5350, 5390, 5430, 5470,
2248         5510, 5550, 5590, 5630,
2249         5670, 5710, 5755, 5795,
2250         5835, 5875
2251     };
2252     int offset_2g = ARRAY_SIZE(freq_list);
2253     int idx;
2254 
2255     if (freq < 4000) {
2256         if (freq < 2427)
2257             return offset_2g;
2258         if (freq < 2442)
2259             return offset_2g + 1;
2260         if (freq < 2457)
2261             return offset_2g + 2;
2262 
2263         return offset_2g + 3;
2264     }
2265 
2266     switch (bw) {
2267     case NL80211_CHAN_WIDTH_80:
2268     case NL80211_CHAN_WIDTH_80P80:
2269     case NL80211_CHAN_WIDTH_160:
2270         break;
2271     default:
2272         idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2273                        freq + 10);
2274         if (idx >= 0) {
2275             freq = freq_bw40[idx];
2276             break;
2277         }
2278 
2279         idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2280                        freq - 10);
2281         if (idx >= 0) {
2282             freq = freq_bw40[idx];
2283             break;
2284         }
2285         fallthrough;
2286     case NL80211_CHAN_WIDTH_40:
2287         idx = mt7615_find_freq_idx(freq_bw40, ARRAY_SIZE(freq_bw40),
2288                        freq);
2289         if (idx >= 0)
2290             break;
2291 
2292         return -1;
2293 
2294     }
2295 
2296     return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2297 }
2298 
2299 int mt7615_mcu_apply_rx_dcoc(struct mt7615_phy *phy)
2300 {
2301     struct mt7615_dev *dev = phy->dev;
2302     struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2303     int freq2 = chandef->center_freq2;
2304     int ret;
2305     struct {
2306         u8 direction;
2307         u8 runtime_calibration;
2308         u8 _rsv[2];
2309 
2310         __le16 center_freq;
2311         u8 bw;
2312         u8 band;
2313         u8 is_freq2;
2314         u8 success;
2315         u8 dbdc_en;
2316 
2317         u8 _rsv2;
2318 
2319         struct {
2320             __le32 sx0_i_lna[4];
2321             __le32 sx0_q_lna[4];
2322 
2323             __le32 sx2_i_lna[4];
2324             __le32 sx2_q_lna[4];
2325         } dcoc_data[4];
2326     } req = {
2327         .direction = 1,
2328 
2329         .bw = mt7615_mcu_chan_bw(chandef),
2330         .band = chandef->center_freq1 > 4000,
2331         .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2332     };
2333     u16 center_freq = chandef->center_freq1;
2334     int freq_idx;
2335     u8 *eep = dev->mt76.eeprom.data;
2336 
2337     if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_RX_CAL))
2338         return 0;
2339 
2340     if (chandef->width == NL80211_CHAN_WIDTH_160) {
2341         freq2 = center_freq + 40;
2342         center_freq -= 40;
2343     }
2344 
2345 again:
2346     req.runtime_calibration = 1;
2347     freq_idx = mt7615_dcoc_freq_idx(center_freq, chandef->width);
2348     if (freq_idx < 0)
2349         goto out;
2350 
2351     memcpy(req.dcoc_data, eep + MT7615_EEPROM_DCOC_OFFSET +
2352                   freq_idx * MT7615_EEPROM_DCOC_SIZE,
2353            sizeof(req.dcoc_data));
2354     req.runtime_calibration = 0;
2355 
2356 out:
2357     req.center_freq = cpu_to_le16(center_freq);
2358     ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RXDCOC_CAL), &req,
2359                 sizeof(req), true);
2360 
2361     if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2362          chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2363         req.is_freq2 = true;
2364         center_freq = freq2;
2365         goto again;
2366     }
2367 
2368     return ret;
2369 }
2370 
2371 static int mt7615_dpd_freq_idx(u16 freq, u8 bw)
2372 {
2373     static const u16 freq_list[] = {
2374         4920, 4940, 4960, 4980,
2375         5040, 5060, 5080, 5180,
2376         5200, 5220, 5240, 5260,
2377         5280, 5300, 5320, 5340,
2378         5360, 5380, 5400, 5420,
2379         5440, 5460, 5480, 5500,
2380         5520, 5540, 5560, 5580,
2381         5600, 5620, 5640, 5660,
2382         5680, 5700, 5720, 5745,
2383         5765, 5785, 5805, 5825,
2384         5845, 5865, 5885, 5905
2385     };
2386     int offset_2g = ARRAY_SIZE(freq_list);
2387     int idx;
2388 
2389     if (freq < 4000) {
2390         if (freq < 2432)
2391             return offset_2g;
2392         if (freq < 2457)
2393             return offset_2g + 1;
2394 
2395         return offset_2g + 2;
2396     }
2397 
2398     if (bw != NL80211_CHAN_WIDTH_20) {
2399         idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2400                        freq + 10);
2401         if (idx >= 0)
2402             return idx;
2403 
2404         idx = mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list),
2405                        freq - 10);
2406         if (idx >= 0)
2407             return idx;
2408     }
2409 
2410     return mt7615_find_freq_idx(freq_list, ARRAY_SIZE(freq_list), freq);
2411 }
2412 
2413 
2414 int mt7615_mcu_apply_tx_dpd(struct mt7615_phy *phy)
2415 {
2416     struct mt7615_dev *dev = phy->dev;
2417     struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
2418     int freq2 = chandef->center_freq2;
2419     int ret;
2420     struct {
2421         u8 direction;
2422         u8 runtime_calibration;
2423         u8 _rsv[2];
2424 
2425         __le16 center_freq;
2426         u8 bw;
2427         u8 band;
2428         u8 is_freq2;
2429         u8 success;
2430         u8 dbdc_en;
2431 
2432         u8 _rsv2;
2433 
2434         struct {
2435             struct {
2436                 u32 dpd_g0;
2437                 u8 data[32];
2438             } wf0, wf1;
2439 
2440             struct {
2441                 u32 dpd_g0_prim;
2442                 u32 dpd_g0_sec;
2443                 u8 data_prim[32];
2444                 u8 data_sec[32];
2445             } wf2, wf3;
2446         } dpd_data;
2447     } req = {
2448         .direction = 1,
2449 
2450         .bw = mt7615_mcu_chan_bw(chandef),
2451         .band = chandef->center_freq1 > 4000,
2452         .dbdc_en = !!dev->mt76.phys[MT_BAND1],
2453     };
2454     u16 center_freq = chandef->center_freq1;
2455     int freq_idx;
2456     u8 *eep = dev->mt76.eeprom.data;
2457 
2458     if (!(eep[MT_EE_CALDATA_FLASH] & MT_EE_CALDATA_FLASH_TX_DPD))
2459         return 0;
2460 
2461     if (chandef->width == NL80211_CHAN_WIDTH_160) {
2462         freq2 = center_freq + 40;
2463         center_freq -= 40;
2464     }
2465 
2466 again:
2467     req.runtime_calibration = 1;
2468     freq_idx = mt7615_dpd_freq_idx(center_freq, chandef->width);
2469     if (freq_idx < 0)
2470         goto out;
2471 
2472     memcpy(&req.dpd_data, eep + MT7615_EEPROM_TXDPD_OFFSET +
2473                   freq_idx * MT7615_EEPROM_TXDPD_SIZE,
2474            sizeof(req.dpd_data));
2475     req.runtime_calibration = 0;
2476 
2477 out:
2478     req.center_freq = cpu_to_le16(center_freq);
2479     ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TXDPD_CAL),
2480                 &req, sizeof(req), true);
2481 
2482     if ((chandef->width == NL80211_CHAN_WIDTH_80P80 ||
2483          chandef->width == NL80211_CHAN_WIDTH_160) && !req.is_freq2) {
2484         req.is_freq2 = true;
2485         center_freq = freq2;
2486         goto again;
2487     }
2488 
2489     return ret;
2490 }
2491 
2492 int mt7615_mcu_set_rx_hdr_trans_blacklist(struct mt7615_dev *dev)
2493 {
2494     struct {
2495         u8 operation;
2496         u8 count;
2497         u8 _rsv[2];
2498         u8 index;
2499         u8 enable;
2500         __le16 etype;
2501     } req = {
2502         .operation = 1,
2503         .count = 1,
2504         .enable = 1,
2505         .etype = cpu_to_le16(ETH_P_PAE),
2506     };
2507 
2508     return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_HDR_TRANS),
2509                  &req, sizeof(req), false);
2510 }
2511 
2512 int mt7615_mcu_set_bss_pm(struct mt7615_dev *dev, struct ieee80211_vif *vif,
2513               bool enable)
2514 {
2515     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2516     struct {
2517         u8 bss_idx;
2518         u8 dtim_period;
2519         __le16 aid;
2520         __le16 bcn_interval;
2521         __le16 atim_window;
2522         u8 uapsd;
2523         u8 bmc_delivered_ac;
2524         u8 bmc_triggered_ac;
2525         u8 pad;
2526     } req = {
2527         .bss_idx = mvif->mt76.idx,
2528         .aid = cpu_to_le16(vif->cfg.aid),
2529         .dtim_period = vif->bss_conf.dtim_period,
2530         .bcn_interval = cpu_to_le16(vif->bss_conf.beacon_int),
2531     };
2532     struct {
2533         u8 bss_idx;
2534         u8 pad[3];
2535     } req_hdr = {
2536         .bss_idx = mvif->mt76.idx,
2537     };
2538     int err;
2539 
2540     if (vif->type != NL80211_IFTYPE_STATION)
2541         return 0;
2542 
2543     err = mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_ABORT),
2544                 &req_hdr, sizeof(req_hdr), false);
2545     if (err < 0 || !enable)
2546         return err;
2547 
2548     return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_BSS_CONNECTED),
2549                  &req, sizeof(req), false);
2550 }
2551 
2552 int mt7615_mcu_set_roc(struct mt7615_phy *phy, struct ieee80211_vif *vif,
2553                struct ieee80211_channel *chan, int duration)
2554 {
2555     struct mt7615_vif *mvif = (struct mt7615_vif *)vif->drv_priv;
2556     struct mt7615_dev *dev = phy->dev;
2557     struct mt7615_roc_tlv req = {
2558         .bss_idx = mvif->mt76.idx,
2559         .active = !chan,
2560         .max_interval = cpu_to_le32(duration),
2561         .primary_chan = chan ? chan->hw_value : 0,
2562         .band = chan ? chan->band : 0,
2563         .req_type = 2,
2564     };
2565 
2566     phy->roc_grant = false;
2567 
2568     return mt76_mcu_send_msg(&dev->mt76, MCU_CE_CMD(SET_ROC),
2569                  &req, sizeof(req), false);
2570 }
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