mt76/mt7615/dma.c

0001 // SPDX-License-Identifier: ISC
0002 /* Copyright (C) 2019 MediaTek Inc.
0003  *
0004  * Author: Ryder Lee <ryder.lee@mediatek.com>
0005  *         Roy Luo <royluo@google.com>
0006  *         Lorenzo Bianconi <lorenzo@kernel.org>
0007  *         Felix Fietkau <nbd@nbd.name>
0008  */
0009
0010 #include "mt7615.h"
0011 #include "../dma.h"
0012 #include "mac.h"
0013
0014 static int
0015 mt7622_init_tx_queues_multi(struct mt7615_dev *dev)
0016 {
0017     static const u8 wmm_queue_map[] = {
0018         [IEEE80211_AC_BK] = MT7622_TXQ_AC0,
0019         [IEEE80211_AC_BE] = MT7622_TXQ_AC1,
0020         [IEEE80211_AC_VI] = MT7622_TXQ_AC2,
0021         [IEEE80211_AC_VO] = MT7622_TXQ_AC3,
0022     };
0023     int ret;
0024     int i;
0025
0026     for (i = 0; i < ARRAY_SIZE(wmm_queue_map); i++) {
0027         ret = mt76_init_tx_queue(&dev->mphy, i, wmm_queue_map[i],
0028                      MT7615_TX_RING_SIZE / 2,
0029                      MT_TX_RING_BASE, 0);
0030         if (ret)
0031             return ret;
0032     }
0033
0034     ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT7622_TXQ_MGMT,
0035                  MT7615_TX_MGMT_RING_SIZE,
0036                  MT_TX_RING_BASE, 0);
0037     if (ret)
0038         return ret;
0039
0040     return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7622_TXQ_MCU,
0041                    MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
0042 }
0043
0044 static int
0045 mt7615_init_tx_queues(struct mt7615_dev *dev)
0046 {
0047     int ret;
0048
0049     ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7615_TXQ_FWDL,
0050                   MT7615_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
0051     if (ret)
0052         return ret;
0053
0054     if (!is_mt7615(&dev->mt76))
0055         return mt7622_init_tx_queues_multi(dev);
0056
0057     ret = mt76_connac_init_tx_queues(&dev->mphy, 0, MT7615_TX_RING_SIZE,
0058                      MT_TX_RING_BASE, 0);
0059     if (ret)
0060         return ret;
0061
0062     return mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7615_TXQ_MCU,
0063                    MT7615_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
0064 }
0065
0066 static int mt7615_poll_tx(struct napi_struct *napi, int budget)
0067 {
0068     struct mt7615_dev *dev;
0069
0070     dev = container_of(napi, struct mt7615_dev, mt76.tx_napi);
0071     if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
0072         napi_complete(napi);
0073         queue_work(dev->mt76.wq, &dev->pm.wake_work);
0074         return 0;
0075     }
0076
0077     mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
0078     if (napi_complete(napi))
0079         mt7615_irq_enable(dev, mt7615_tx_mcu_int_mask(dev));
0080
0081     mt76_connac_pm_unref(&dev->mphy, &dev->pm);
0082
0083     return 0;
0084 }
0085
0086 static int mt7615_poll_rx(struct napi_struct *napi, int budget)
0087 {
0088     struct mt7615_dev *dev;
0089     int done;
0090
0091     dev = container_of(napi->dev, struct mt7615_dev, mt76.napi_dev);
0092
0093     if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
0094         napi_complete(napi);
0095         queue_work(dev->mt76.wq, &dev->pm.wake_work);
0096         return 0;
0097     }
0098     done = mt76_dma_rx_poll(napi, budget);
0099     mt76_connac_pm_unref(&dev->mphy, &dev->pm);
0100
0101     return done;
0102 }
0103
0104 int mt7615_wait_pdma_busy(struct mt7615_dev *dev)
0105 {
0106     struct mt76_dev *mdev = &dev->mt76;
0107
0108     if (!is_mt7663(mdev)) {
0109         u32 mask = MT_PDMA_TX_BUSY | MT_PDMA_RX_BUSY;
0110         u32 reg = mt7615_reg_map(dev, MT_PDMA_BUSY);
0111
0112         if (!mt76_poll_msec(dev, reg, mask, 0, 1000)) {
0113             dev_err(mdev->dev, "PDMA engine busy\n");
0114             return -EIO;
0115         }
0116
0117         return 0;
0118     }
0119
0120     if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
0121                 MT_PDMA_TX_IDX_BUSY, 0, 1000)) {
0122         dev_err(mdev->dev, "PDMA engine tx busy\n");
0123         return -EIO;
0124     }
0125
0126     if (!mt76_poll_msec(dev, MT_PSE_PG_INFO,
0127                 MT_PSE_SRC_CNT, 0, 1000)) {
0128         dev_err(mdev->dev, "PSE engine busy\n");
0129         return -EIO;
0130     }
0131
0132     if (!mt76_poll_msec(dev, MT_PDMA_BUSY_STATUS,
0133                 MT_PDMA_BUSY_IDX, 0, 1000)) {
0134         dev_err(mdev->dev, "PDMA engine busy\n");
0135         return -EIO;
0136     }
0137
0138     return 0;
0139 }
0140
0141 static void mt7622_dma_sched_init(struct mt7615_dev *dev)
0142 {
0143     u32 reg = mt7615_reg_map(dev, MT_DMASHDL_BASE);
0144     int i;
0145
0146     mt76_rmw(dev, reg + MT_DMASHDL_PKT_MAX_SIZE,
0147          MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
0148          FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
0149          FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
0150
0151     for (i = 0; i <= 5; i++)
0152         mt76_wr(dev, reg + MT_DMASHDL_GROUP_QUOTA(i),
0153             FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x10) |
0154             FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
0155
0156     mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(0), 0x42104210);
0157     mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(1), 0x42104210);
0158     mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(2), 0x5);
0159     mt76_wr(dev, reg + MT_DMASHDL_Q_MAP(3), 0);
0160
0161     mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET0, 0x6012345f);
0162     mt76_wr(dev, reg + MT_DMASHDL_SCHED_SET1, 0xedcba987);
0163 }
0164
0165 static void mt7663_dma_sched_init(struct mt7615_dev *dev)
0166 {
0167     int i;
0168
0169     mt76_rmw(dev, MT_DMA_SHDL(MT_DMASHDL_PKT_MAX_SIZE),
0170          MT_DMASHDL_PKT_MAX_SIZE_PLE | MT_DMASHDL_PKT_MAX_SIZE_PSE,
0171          FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) |
0172          FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8));
0173
0174     /* enable refill control group 0, 1, 2, 4, 5 */
0175     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_REFILL), 0xffc80000);
0176     /* enable group 0, 1, 2, 4, 5, 15 */
0177     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_OPTIONAL), 0x70068037);
0178
0179     /* each group min quota must larger then PLE_PKT_MAX_SIZE_NUM */
0180     for (i = 0; i < 5; i++)
0181         mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(i)),
0182             FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
0183             FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x800));
0184     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(5)),
0185         FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x40) |
0186         FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x40));
0187     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_GROUP_QUOTA(15)),
0188         FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MIN, 0x20) |
0189         FIELD_PREP(MT_DMASHDL_GROUP_QUOTA_MAX, 0x20));
0190
0191     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(0)), 0x42104210);
0192     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(1)), 0x42104210);
0193     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(2)), 0x00050005);
0194     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_Q_MAP(3)), 0);
0195     /* ALTX0 and ALTX1 QID mapping to group 5 */
0196     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET0), 0x6012345f);
0197     mt76_wr(dev, MT_DMA_SHDL(MT_DMASHDL_SCHED_SET1), 0xedcba987);
0198 }
0199
0200 void mt7615_dma_start(struct mt7615_dev *dev)
0201 {
0202     /* start dma engine */
0203     mt76_set(dev, MT_WPDMA_GLO_CFG,
0204          MT_WPDMA_GLO_CFG_TX_DMA_EN |
0205          MT_WPDMA_GLO_CFG_RX_DMA_EN |
0206          MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
0207
0208     if (is_mt7622(&dev->mt76))
0209         mt7622_dma_sched_init(dev);
0210
0211     if (is_mt7663(&dev->mt76)) {
0212         mt7663_dma_sched_init(dev);
0213
0214         mt76_wr(dev, MT_MCU2HOST_INT_ENABLE, MT7663_MCU_CMD_ERROR_MASK);
0215     }
0216
0217 }
0218
0219 int mt7615_dma_init(struct mt7615_dev *dev)
0220 {
0221     int rx_ring_size = MT7615_RX_RING_SIZE;
0222     u32 mask;
0223     int ret;
0224
0225     mt76_dma_attach(&dev->mt76);
0226
0227     mt76_wr(dev, MT_WPDMA_GLO_CFG,
0228         MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE |
0229         MT_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN |
0230         MT_WPDMA_GLO_CFG_OMIT_TX_INFO);
0231
0232     mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
0233                MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT0, 0x1);
0234
0235     mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
0236                MT_WPDMA_GLO_CFG_TX_BT_SIZE_BIT21, 0x1);
0237
0238     mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
0239                MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 0x3);
0240
0241     mt76_rmw_field(dev, MT_WPDMA_GLO_CFG,
0242                MT_WPDMA_GLO_CFG_MULTI_DMA_EN, 0x3);
0243
0244     if (is_mt7615(&dev->mt76)) {
0245         mt76_set(dev, MT_WPDMA_GLO_CFG,
0246              MT_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY);
0247
0248         mt76_wr(dev, MT_WPDMA_GLO_CFG1, 0x1);
0249         mt76_wr(dev, MT_WPDMA_TX_PRE_CFG, 0xf0000);
0250         mt76_wr(dev, MT_WPDMA_RX_PRE_CFG, 0xf7f0000);
0251         mt76_wr(dev, MT_WPDMA_ABT_CFG, 0x4000026);
0252         mt76_wr(dev, MT_WPDMA_ABT_CFG1, 0x18811881);
0253         mt76_set(dev, 0x7158, BIT(16));
0254         mt76_clear(dev, 0x7000, BIT(23));
0255     }
0256
0257     mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
0258
0259     ret = mt7615_init_tx_queues(dev);
0260     if (ret)
0261         return ret;
0262
0263     /* init rx queues */
0264     ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
0265                    MT7615_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE,
0266                    MT_RX_RING_BASE);
0267     if (ret)
0268         return ret;
0269
0270     if (!is_mt7615(&dev->mt76))
0271         rx_ring_size /= 2;
0272
0273     ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 0,
0274                    rx_ring_size, MT_RX_BUF_SIZE, MT_RX_RING_BASE);
0275     if (ret)
0276         return ret;
0277
0278     mt76_wr(dev, MT_DELAY_INT_CFG, 0);
0279
0280     ret = mt76_init_queues(dev, mt7615_poll_rx);
0281     if (ret < 0)
0282         return ret;
0283
0284     netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
0285               mt7615_poll_tx);
0286     napi_enable(&dev->mt76.tx_napi);
0287
0288     mt76_poll(dev, MT_WPDMA_GLO_CFG,
0289           MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
0290           MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 1000);
0291
0292     /* enable interrupts for TX/RX rings */
0293
0294     mask = MT_INT_RX_DONE_ALL | mt7615_tx_mcu_int_mask(dev);
0295     if (is_mt7663(&dev->mt76))
0296         mask |= MT7663_INT_MCU_CMD;
0297     else
0298         mask |= MT_INT_MCU_CMD;
0299
0300     mt7615_irq_enable(dev, mask);
0301
0302     mt7615_dma_start(dev);
0303
0304     return 0;
0305 }
0306
0307 void mt7615_dma_cleanup(struct mt7615_dev *dev)
0308 {
0309     mt76_clear(dev, MT_WPDMA_GLO_CFG,
0310            MT_WPDMA_GLO_CFG_TX_DMA_EN |
0311            MT_WPDMA_GLO_CFG_RX_DMA_EN);
0312     mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
0313
0314     mt76_dma_cleanup(&dev->mt76);
0315 }