mt76/mt7603/init.c

0001 // SPDX-License-Identifier: ISC
0002
0003 #include <linux/etherdevice.h>
0004 #include "mt7603.h"
0005 #include "mac.h"
0006 #include "eeprom.h"
0007
0008 const struct mt76_driver_ops mt7603_drv_ops = {
0009     .txwi_size = MT_TXD_SIZE,
0010     .drv_flags = MT_DRV_SW_RX_AIRTIME,
0011     .survey_flags = SURVEY_INFO_TIME_TX,
0012     .tx_prepare_skb = mt7603_tx_prepare_skb,
0013     .tx_complete_skb = mt7603_tx_complete_skb,
0014     .rx_skb = mt7603_queue_rx_skb,
0015     .rx_poll_complete = mt7603_rx_poll_complete,
0016     .sta_ps = mt7603_sta_ps,
0017     .sta_add = mt7603_sta_add,
0018     .sta_assoc = mt7603_sta_assoc,
0019     .sta_remove = mt7603_sta_remove,
0020     .update_survey = mt7603_update_channel,
0021 };
0022
0023 static void
0024 mt7603_set_tmac_template(struct mt7603_dev *dev)
0025 {
0026     u32 desc[5] = {
0027         [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
0028         [3] = MT_TXD5_SW_POWER_MGMT
0029     };
0030     u32 addr;
0031     int i;
0032
0033     addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
0034     addr += MT_CLIENT_TMAC_INFO_TEMPLATE;
0035     for (i = 0; i < ARRAY_SIZE(desc); i++)
0036         mt76_wr(dev, addr + 4 * i, desc[i]);
0037 }
0038
0039 static void
0040 mt7603_dma_sched_init(struct mt7603_dev *dev)
0041 {
0042     int page_size = 128;
0043     int page_count;
0044     int max_len = 1792;
0045     int max_amsdu_pages = 4096 / page_size;
0046     int max_mcu_len = 4096;
0047     int max_beacon_len = 512 * 4 + max_len;
0048     int max_mcast_pages = 4 * max_len / page_size;
0049     int reserved_count = 0;
0050     int beacon_pages;
0051     int mcu_pages;
0052     int i;
0053
0054     page_count = mt76_get_field(dev, MT_PSE_FC_P0,
0055                     MT_PSE_FC_P0_MAX_QUOTA);
0056     beacon_pages = 4 * (max_beacon_len / page_size);
0057     mcu_pages = max_mcu_len / page_size;
0058
0059     mt76_wr(dev, MT_PSE_FRP,
0060         FIELD_PREP(MT_PSE_FRP_P0, 7) |
0061         FIELD_PREP(MT_PSE_FRP_P1, 6) |
0062         FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));
0063
0064     mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
0065     mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
0066
0067     mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);
0068     mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);
0069
0070     mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);
0071
0072     mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));
0073     mt76_wr(dev, MT_SCH_2, max_amsdu_pages);
0074
0075     for (i = 0; i <= 4; i++)
0076         mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages);
0077     reserved_count += 5 * max_amsdu_pages;
0078
0079     mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);
0080     reserved_count += mcu_pages;
0081
0082     mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);
0083     reserved_count += beacon_pages;
0084
0085     mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages);
0086     reserved_count += max_mcast_pages;
0087
0088     if (is_mt7603(dev))
0089         reserved_count = 0;
0090
0091     mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count);
0092
0093     if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) {
0094         mt76_wr(dev, MT_GROUP_THRESH(0),
0095             page_count - beacon_pages - mcu_pages);
0096         mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);
0097         mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);
0098         mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);
0099         mt76_wr(dev, MT_BMAP_1, 0x00000020);
0100     } else {
0101         mt76_wr(dev, MT_GROUP_THRESH(0), page_count);
0102         mt76_wr(dev, MT_BMAP_0, 0xffff);
0103     }
0104
0105     mt76_wr(dev, MT_SCH_4, 0);
0106
0107     for (i = 0; i <= 15; i++)
0108         mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);
0109
0110     mt76_set(dev, MT_SCH_4, BIT(6));
0111 }
0112
0113 static void
0114 mt7603_phy_init(struct mt7603_dev *dev)
0115 {
0116     int rx_chains = dev->mphy.antenna_mask;
0117     int tx_chains = hweight8(rx_chains) - 1;
0118
0119     mt76_rmw(dev, MT_WF_RMAC_RMCR,
0120          (MT_WF_RMAC_RMCR_SMPS_MODE |
0121           MT_WF_RMAC_RMCR_RX_STREAMS),
0122          (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
0123           FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
0124
0125     mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
0126                tx_chains);
0127
0128     dev->agc0 = mt76_rr(dev, MT_AGC(0));
0129     dev->agc3 = mt76_rr(dev, MT_AGC(3));
0130 }
0131
0132 static void
0133 mt7603_mac_init(struct mt7603_dev *dev)
0134 {
0135     u8 bc_addr[ETH_ALEN];
0136     u32 addr;
0137     int i;
0138
0139     mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0,
0140         (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0141         (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0142         (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0143         (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
0144
0145     mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1,
0146         (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0147         (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0148         (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
0149         (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
0150
0151     mt76_wr(dev, MT_AGG_LIMIT,
0152         FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
0153         FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
0154         FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
0155         FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
0156
0157     mt76_wr(dev, MT_AGG_LIMIT_1,
0158         FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
0159         FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
0160         FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
0161         FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
0162
0163     mt76_wr(dev, MT_AGG_CONTROL,
0164         FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |
0165         FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
0166         MT_AGG_CONTROL_NO_BA_AR_RULE);
0167
0168     mt76_wr(dev, MT_AGG_RETRY_CONTROL,
0169         FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
0170         FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
0171
0172     mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |
0173         FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096));
0174
0175     mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
0176     mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
0177
0178     mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31));
0179
0180     mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT);
0181     mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
0182
0183     mt76_wr(dev, MT_WF_RFCR1, 0);
0184
0185     mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE);
0186
0187     mt7603_set_tmac_template(dev);
0188
0189     /* Enable RX group to HIF */
0190     addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
0191     mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS);
0192
0193     /* Enable RX group to MCU */
0194     mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
0195
0196     mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3);
0197     mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN);
0198
0199     /* include preamble detection in CCA trigger signal */
0200     mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2);
0201
0202     mt76_wr(dev, MT_RXREQ, 4);
0203
0204     /* Configure all rx packets to HIF */
0205     mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);
0206
0207     /* Configure MCU txs selection with aggregation */
0208     mt76_wr(dev, MT_DMA_TCFR0,
0209         FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
0210         MT_DMA_TCFR_TXS_AGGR_COUNT);
0211
0212     /* Configure HIF txs selection with aggregation */
0213     mt76_wr(dev, MT_DMA_TCFR1,
0214         FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) | /* 32 us */
0215         MT_DMA_TCFR_TXS_AGGR_COUNT | /* Maximum count */
0216         MT_DMA_TCFR_TXS_BIT_MAP);
0217
0218     mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);
0219
0220     for (i = 0; i < MT7603_WTBL_SIZE; i++)
0221         mt7603_wtbl_clear(dev, i);
0222
0223     eth_broadcast_addr(bc_addr);
0224     mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr);
0225     dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED;
0226     rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED],
0227                &dev->global_sta.wcid);
0228
0229     mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
0230     mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
0231
0232     mt76_wr(dev, MT_AGG_ARUCR,
0233         FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
0234         FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
0235         FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
0236         FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
0237         FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
0238         FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
0239         FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
0240         FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
0241
0242     mt76_wr(dev, MT_AGG_ARDCR,
0243         FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
0244         FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
0245         FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
0246         FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
0247         FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
0248         FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
0249         FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
0250         FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
0251
0252     mt76_wr(dev, MT_AGG_ARCR,
0253         (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
0254          MT_AGG_ARCR_RATE_DOWN_RATIO_EN |
0255          FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |
0256          FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));
0257
0258     mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);
0259
0260     mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER);
0261     mt76_clear(dev, MT_SEC_SCR, BIT(18));
0262
0263     /* Set secondary beacon time offsets */
0264     for (i = 0; i <= 4; i++)
0265         mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET,
0266                    (i + 1) * (20 + 4096));
0267 }
0268
0269 static int
0270 mt7603_init_hardware(struct mt7603_dev *dev)
0271 {
0272     int i, ret;
0273
0274     mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
0275
0276     ret = mt7603_eeprom_init(dev);
0277     if (ret < 0)
0278         return ret;
0279
0280     ret = mt7603_dma_init(dev);
0281     if (ret)
0282         return ret;
0283
0284     mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
0285     mt7603_mac_dma_start(dev);
0286     dev->rxfilter = mt76_rr(dev, MT_WF_RFCR);
0287     set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
0288
0289     for (i = 0; i < MT7603_WTBL_SIZE; i++) {
0290         mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE |
0291             FIELD_PREP(MT_PSE_RTA_TAG_ID, i));
0292         mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
0293     }
0294
0295     ret = mt7603_mcu_init(dev);
0296     if (ret)
0297         return ret;
0298
0299     mt7603_dma_sched_init(dev);
0300     mt7603_mcu_set_eeprom(dev);
0301     mt7603_phy_init(dev);
0302     mt7603_mac_init(dev);
0303
0304     return 0;
0305 }
0306
0307 static const struct ieee80211_iface_limit if_limits[] = {
0308     {
0309         .max = 1,
0310         .types = BIT(NL80211_IFTYPE_ADHOC)
0311     }, {
0312         .max = MT7603_MAX_INTERFACES,
0313         .types = BIT(NL80211_IFTYPE_STATION) |
0314 #ifdef CONFIG_MAC80211_MESH
0315              BIT(NL80211_IFTYPE_MESH_POINT) |
0316 #endif
0317              BIT(NL80211_IFTYPE_P2P_CLIENT) |
0318              BIT(NL80211_IFTYPE_P2P_GO) |
0319              BIT(NL80211_IFTYPE_AP)
0320      },
0321 };
0322
0323 static const struct ieee80211_iface_combination if_comb[] = {
0324     {
0325         .limits = if_limits,
0326         .n_limits = ARRAY_SIZE(if_limits),
0327         .max_interfaces = 4,
0328         .num_different_channels = 1,
0329         .beacon_int_infra_match = true,
0330     }
0331 };
0332
0333 static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on,
0334                   u8 delay_off)
0335 {
0336     struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev,
0337                           mt76);
0338     u32 val, addr;
0339
0340     val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
0341           FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
0342           FIELD_PREP(MT_LED_STATUS_ON, delay_on);
0343
0344     addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin));
0345     mt76_wr(dev, addr, val);
0346     addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin));
0347     mt76_wr(dev, addr, val);
0348
0349     val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
0350           MT_LED_CTRL_KICK(mt76->led_pin);
0351     if (mt76->led_al)
0352         val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
0353     addr = mt7603_reg_map(dev, MT_LED_CTRL);
0354     mt76_wr(dev, addr, val);
0355 }
0356
0357 static int mt7603_led_set_blink(struct led_classdev *led_cdev,
0358                 unsigned long *delay_on,
0359                 unsigned long *delay_off)
0360 {
0361     struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
0362                          led_cdev);
0363     u8 delta_on, delta_off;
0364
0365     delta_off = max_t(u8, *delay_off / 10, 1);
0366     delta_on = max_t(u8, *delay_on / 10, 1);
0367
0368     mt7603_led_set_config(mt76, delta_on, delta_off);
0369     return 0;
0370 }
0371
0372 static void mt7603_led_set_brightness(struct led_classdev *led_cdev,
0373                       enum led_brightness brightness)
0374 {
0375     struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
0376                          led_cdev);
0377
0378     if (!brightness)
0379         mt7603_led_set_config(mt76, 0, 0xff);
0380     else
0381         mt7603_led_set_config(mt76, 0xff, 0);
0382 }
0383
0384 static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr)
0385 {
0386     if (addr < 0x100000)
0387         return addr;
0388
0389     return mt7603_reg_map(dev, addr);
0390 }
0391
0392 static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset)
0393 {
0394     struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
0395     u32 addr = __mt7603_reg_addr(dev, offset);
0396
0397     return dev->bus_ops->rr(mdev, addr);
0398 }
0399
0400 static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val)
0401 {
0402     struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
0403     u32 addr = __mt7603_reg_addr(dev, offset);
0404
0405     dev->bus_ops->wr(mdev, addr, val);
0406 }
0407
0408 static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
0409 {
0410     struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
0411     u32 addr = __mt7603_reg_addr(dev, offset);
0412
0413     return dev->bus_ops->rmw(mdev, addr, mask, val);
0414 }
0415
0416 static void
0417 mt7603_regd_notifier(struct wiphy *wiphy,
0418              struct regulatory_request *request)
0419 {
0420     struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
0421     struct mt7603_dev *dev = hw->priv;
0422
0423     dev->mt76.region = request->dfs_region;
0424     dev->ed_monitor = dev->ed_monitor_enabled &&
0425               dev->mt76.region == NL80211_DFS_ETSI;
0426 }
0427
0428 static int
0429 mt7603_txpower_signed(int val)
0430 {
0431     bool sign = val & BIT(6);
0432
0433     if (!(val & BIT(7)))
0434         return 0;
0435
0436     val &= GENMASK(5, 0);
0437     if (!sign)
0438         val = -val;
0439
0440     return val;
0441 }
0442
0443 static void
0444 mt7603_init_txpower(struct mt7603_dev *dev,
0445             struct ieee80211_supported_band *sband)
0446 {
0447     struct ieee80211_channel *chan;
0448     u8 *eeprom = (u8 *)dev->mt76.eeprom.data;
0449     int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7);
0450     u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK];
0451     bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1);
0452     int max_offset, cur_offset;
0453     int i;
0454
0455     if (ext_pa && is_mt7603(dev))
0456         target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7);
0457
0458     if (target_power & BIT(6))
0459         target_power = -(target_power & GENMASK(5, 0));
0460
0461     max_offset = 0;
0462     for (i = 0; i < 14; i++) {
0463         cur_offset = mt7603_txpower_signed(rate_power[i]);
0464         max_offset = max(max_offset, cur_offset);
0465     }
0466
0467     target_power += max_offset;
0468
0469     dev->tx_power_limit = target_power;
0470     dev->mphy.txpower_cur = target_power;
0471
0472     target_power = DIV_ROUND_UP(target_power, 2);
0473
0474     /* add 3 dBm for 2SS devices (combined output) */
0475     if (dev->mphy.antenna_mask & BIT(1))
0476         target_power += 3;
0477
0478     for (i = 0; i < sband->n_channels; i++) {
0479         chan = &sband->channels[i];
0480         chan->max_power = min_t(int, chan->max_reg_power, target_power);
0481         chan->orig_mpwr = target_power;
0482     }
0483 }
0484
0485 int mt7603_register_device(struct mt7603_dev *dev)
0486 {
0487     struct mt76_bus_ops *bus_ops;
0488     struct ieee80211_hw *hw = mt76_hw(dev);
0489     struct wiphy *wiphy = hw->wiphy;
0490     int ret;
0491
0492     dev->bus_ops = dev->mt76.bus;
0493     bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
0494                    GFP_KERNEL);
0495     if (!bus_ops)
0496         return -ENOMEM;
0497
0498     bus_ops->rr = mt7603_rr;
0499     bus_ops->wr = mt7603_wr;
0500     bus_ops->rmw = mt7603_rmw;
0501     dev->mt76.bus = bus_ops;
0502
0503     INIT_LIST_HEAD(&dev->sta_poll_list);
0504     spin_lock_init(&dev->sta_poll_lock);
0505     spin_lock_init(&dev->ps_lock);
0506
0507     INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7603_mac_work);
0508     tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet);
0509
0510     dev->slottime = 9;
0511     dev->sensitivity_limit = 28;
0512     dev->dynamic_sensitivity = true;
0513
0514     ret = mt7603_init_hardware(dev);
0515     if (ret)
0516         return ret;
0517
0518     hw->queues = 4;
0519     hw->max_rates = 3;
0520     hw->max_report_rates = 7;
0521     hw->max_rate_tries = 11;
0522
0523     hw->radiotap_timestamp.units_pos =
0524         IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
0525
0526     hw->sta_data_size = sizeof(struct mt7603_sta);
0527     hw->vif_data_size = sizeof(struct mt7603_vif);
0528
0529     wiphy->iface_combinations = if_comb;
0530     wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
0531
0532     ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
0533     ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
0534     ieee80211_hw_set(hw, NEEDS_UNIQUE_STA_ADDR);
0535
0536     /* init led callbacks */
0537     if (IS_ENABLED(CONFIG_MT76_LEDS)) {
0538         dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness;
0539         dev->mt76.led_cdev.blink_set = mt7603_led_set_blink;
0540     }
0541
0542     wiphy->reg_notifier = mt7603_regd_notifier;
0543
0544     ret = mt76_register_device(&dev->mt76, true, mt76_rates,
0545                    ARRAY_SIZE(mt76_rates));
0546     if (ret)
0547         return ret;
0548
0549     mt7603_init_debugfs(dev);
0550     mt7603_init_txpower(dev, &dev->mphy.sband_2g.sband);
0551
0552     return 0;
0553 }
0554
0555 void mt7603_unregister_device(struct mt7603_dev *dev)
0556 {
0557     tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
0558     mt76_unregister_device(&dev->mt76);
0559     mt7603_mcu_exit(dev);
0560     mt7603_dma_cleanup(dev);
0561     mt76_free_device(&dev->mt76);
0562 }