mt76/mt7603/core.c

0001 // SPDX-License-Identifier: ISC
0002
0003 #include "mt7603.h"
0004 #include "../trace.h"
0005
0006 void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
0007 {
0008     struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
0009
0010     mt7603_irq_enable(dev, MT_INT_RX_DONE(q));
0011 }
0012
0013 irqreturn_t mt7603_irq_handler(int irq, void *dev_instance)
0014 {
0015     struct mt7603_dev *dev = dev_instance;
0016     u32 intr;
0017
0018     intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
0019     mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
0020
0021     if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
0022         return IRQ_NONE;
0023
0024     trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
0025
0026     intr &= dev->mt76.mmio.irqmask;
0027
0028     if (intr & MT_INT_MAC_IRQ3) {
0029         u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3));
0030
0031         mt76_wr(dev, MT_HW_INT_STATUS(3), hwintr);
0032         if (hwintr & MT_HW_INT3_PRE_TBTT0)
0033             tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
0034
0035         if ((hwintr & MT_HW_INT3_TBTT0) && dev->mt76.csa_complete)
0036             mt76_csa_finish(&dev->mt76);
0037     }
0038
0039     if (intr & MT_INT_TX_DONE_ALL) {
0040         mt7603_irq_disable(dev, MT_INT_TX_DONE_ALL);
0041         napi_schedule(&dev->mt76.tx_napi);
0042     }
0043
0044     if (intr & MT_INT_RX_DONE(0)) {
0045         mt7603_irq_disable(dev, MT_INT_RX_DONE(0));
0046         napi_schedule(&dev->mt76.napi[0]);
0047     }
0048
0049     if (intr & MT_INT_RX_DONE(1)) {
0050         mt7603_irq_disable(dev, MT_INT_RX_DONE(1));
0051         napi_schedule(&dev->mt76.napi[1]);
0052     }
0053
0054     return IRQ_HANDLED;
0055 }
0056
0057 u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr)
0058 {
0059     u32 base = addr & MT_MCU_PCIE_REMAP_2_BASE;
0060     u32 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET;
0061
0062     dev->bus_ops->wr(&dev->mt76, MT_MCU_PCIE_REMAP_2, base);
0063
0064     return MT_PCIE_REMAP_BASE_2 + offset;
0065 }