0001
0002
0003 #include "mt7603.h"
0004
0005 struct beacon_bc_data {
0006 struct mt7603_dev *dev;
0007 struct sk_buff_head q;
0008 struct sk_buff *tail[MT7603_MAX_INTERFACES];
0009 int count[MT7603_MAX_INTERFACES];
0010 };
0011
0012 static void
0013 mt7603_update_beacon_iter(void *priv, u8 *mac, struct ieee80211_vif *vif)
0014 {
0015 struct mt7603_dev *dev = (struct mt7603_dev *)priv;
0016 struct mt76_dev *mdev = &dev->mt76;
0017 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
0018 struct sk_buff *skb = NULL;
0019
0020 if (!(mdev->beacon_mask & BIT(mvif->idx)))
0021 return;
0022
0023 skb = ieee80211_beacon_get(mt76_hw(dev), vif, 0);
0024 if (!skb)
0025 return;
0026
0027 mt76_tx_queue_skb(dev, dev->mphy.q_tx[MT_TXQ_BEACON],
0028 MT_TXQ_BEACON, skb, &mvif->sta.wcid, NULL);
0029
0030 spin_lock_bh(&dev->ps_lock);
0031 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
0032 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, mvif->sta.wcid.idx) |
0033 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID,
0034 dev->mphy.q_tx[MT_TXQ_CAB]->hw_idx) |
0035 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, 3) |
0036 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, 8));
0037
0038 if (!mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000))
0039 dev->beacon_check = MT7603_WATCHDOG_TIMEOUT;
0040
0041 spin_unlock_bh(&dev->ps_lock);
0042 }
0043
0044 static void
0045 mt7603_add_buffered_bc(void *priv, u8 *mac, struct ieee80211_vif *vif)
0046 {
0047 struct beacon_bc_data *data = priv;
0048 struct mt7603_dev *dev = data->dev;
0049 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
0050 struct ieee80211_tx_info *info;
0051 struct sk_buff *skb;
0052
0053 if (!(dev->mt76.beacon_mask & BIT(mvif->idx)))
0054 return;
0055
0056 skb = ieee80211_get_buffered_bc(mt76_hw(dev), vif);
0057 if (!skb)
0058 return;
0059
0060 info = IEEE80211_SKB_CB(skb);
0061 info->control.vif = vif;
0062 info->flags |= IEEE80211_TX_CTL_ASSIGN_SEQ;
0063 mt76_skb_set_moredata(skb, true);
0064 __skb_queue_tail(&data->q, skb);
0065 data->tail[mvif->idx] = skb;
0066 data->count[mvif->idx]++;
0067 }
0068
0069 void mt7603_pre_tbtt_tasklet(struct tasklet_struct *t)
0070 {
0071 struct mt7603_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
0072 struct mt76_dev *mdev = &dev->mt76;
0073 struct mt76_queue *q;
0074 struct beacon_bc_data data = {};
0075 struct sk_buff *skb;
0076 int i, nframes;
0077
0078 if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
0079 return;
0080
0081 data.dev = dev;
0082 __skb_queue_head_init(&data.q);
0083
0084 q = dev->mphy.q_tx[MT_TXQ_BEACON];
0085 spin_lock(&q->lock);
0086 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
0087 IEEE80211_IFACE_ITER_RESUME_ALL,
0088 mt7603_update_beacon_iter, dev);
0089 mt76_queue_kick(dev, q);
0090 spin_unlock(&q->lock);
0091
0092
0093 mt76_wr(dev, MT_WF_ARB_CAB_FLUSH, GENMASK(30, 16) | BIT(0));
0094
0095 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_CAB], false);
0096
0097 mt76_csa_check(mdev);
0098 if (mdev->csa_complete)
0099 goto out;
0100
0101 q = dev->mphy.q_tx[MT_TXQ_CAB];
0102 do {
0103 nframes = skb_queue_len(&data.q);
0104 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
0105 IEEE80211_IFACE_ITER_RESUME_ALL,
0106 mt7603_add_buffered_bc, &data);
0107 } while (nframes != skb_queue_len(&data.q) &&
0108 skb_queue_len(&data.q) < 8);
0109
0110 if (skb_queue_empty(&data.q))
0111 goto out;
0112
0113 for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
0114 if (!data.tail[i])
0115 continue;
0116
0117 mt76_skb_set_moredata(data.tail[i], false);
0118 }
0119
0120 spin_lock(&q->lock);
0121 while ((skb = __skb_dequeue(&data.q)) != NULL) {
0122 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0123 struct ieee80211_vif *vif = info->control.vif;
0124 struct mt7603_vif *mvif = (struct mt7603_vif *)vif->drv_priv;
0125
0126 mt76_tx_queue_skb(dev, q, MT_TXQ_CAB, skb, &mvif->sta.wcid, NULL);
0127 }
0128 mt76_queue_kick(dev, q);
0129 spin_unlock(&q->lock);
0130
0131 for (i = 0; i < ARRAY_SIZE(data.count); i++)
0132 mt76_wr(dev, MT_WF_ARB_CAB_COUNT_B0_REG(i),
0133 data.count[i] << MT_WF_ARB_CAB_COUNT_B0_SHIFT(i));
0134
0135 mt76_wr(dev, MT_WF_ARB_CAB_START,
0136 MT_WF_ARB_CAB_START_BSSn(0) |
0137 (MT_WF_ARB_CAB_START_BSS0n(1) *
0138 ((1 << (MT7603_MAX_INTERFACES - 1)) - 1)));
0139
0140 out:
0141 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BEACON], false);
0142 if (dev->mphy.q_tx[MT_TXQ_BEACON]->queued > hweight8(mdev->beacon_mask))
0143 dev->beacon_check++;
0144 }
0145
0146 void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval)
0147 {
0148 u32 pre_tbtt = MT7603_PRE_TBTT_TIME / 64;
0149
0150 if (idx >= 0) {
0151 if (intval)
0152 dev->mt76.beacon_mask |= BIT(idx);
0153 else
0154 dev->mt76.beacon_mask &= ~BIT(idx);
0155 }
0156
0157 if (!dev->mt76.beacon_mask || (!intval && idx < 0)) {
0158 mt7603_irq_disable(dev, MT_INT_MAC_IRQ3);
0159 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK);
0160 mt76_wr(dev, MT_HW_INT_MASK(3), 0);
0161 return;
0162 }
0163
0164 dev->mt76.beacon_int = intval;
0165 mt76_wr(dev, MT_TBTT,
0166 FIELD_PREP(MT_TBTT_PERIOD, intval) | MT_TBTT_CAL_ENABLE);
0167
0168 mt76_wr(dev, MT_TBTT_TIMER_CFG, 0x99);
0169
0170 mt76_rmw_field(dev, MT_ARB_SCR, MT_ARB_SCR_BCNQ_OPMODE_MASK,
0171 MT_BCNQ_OPMODE_AP);
0172 mt76_clear(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCN_PRIO);
0173 mt76_set(dev, MT_ARB_SCR, MT_ARB_SCR_TBTT_BCAST_PRIO);
0174
0175 mt76_wr(dev, MT_PRE_TBTT, pre_tbtt);
0176
0177 mt76_set(dev, MT_HW_INT_MASK(3),
0178 MT_HW_INT3_PRE_TBTT0 | MT_HW_INT3_TBTT0);
0179
0180 mt76_set(dev, MT_WF_ARB_BCN_START,
0181 MT_WF_ARB_BCN_START_BSSn(0) |
0182 ((dev->mt76.beacon_mask >> 1) *
0183 MT_WF_ARB_BCN_START_BSS0n(1)));
0184 mt7603_irq_enable(dev, MT_INT_MAC_IRQ3);
0185
0186 if (dev->mt76.beacon_mask & ~BIT(0))
0187 mt76_set(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
0188 else
0189 mt76_clear(dev, MT_LPON_SBTOR(0), MT_LPON_SBTOR_SUB_BSS_EN);
0190 }
