mediatek/mt76/mmio.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  */
0005
0006 #include "mt76.h"
0007 #include "trace.h"
0008
0009 static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset)
0010 {
0011     u32 val;
0012
0013     val = readl(dev->mmio.regs + offset);
0014     trace_reg_rr(dev, offset, val);
0015
0016     return val;
0017 }
0018
0019 static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
0020 {
0021     trace_reg_wr(dev, offset, val);
0022     writel(val, dev->mmio.regs + offset);
0023 }
0024
0025 static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
0026 {
0027     val |= mt76_mmio_rr(dev, offset) & ~mask;
0028     mt76_mmio_wr(dev, offset, val);
0029     return val;
0030 }
0031
0032 static void mt76_mmio_write_copy(struct mt76_dev *dev, u32 offset,
0033                  const void *data, int len)
0034 {
0035     __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));
0036 }
0037
0038 static void mt76_mmio_read_copy(struct mt76_dev *dev, u32 offset,
0039                 void *data, int len)
0040 {
0041     __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));
0042 }
0043
0044 static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base,
0045                const struct mt76_reg_pair *data, int len)
0046 {
0047     while (len > 0) {
0048         mt76_mmio_wr(dev, data->reg, data->value);
0049         data++;
0050         len--;
0051     }
0052
0053     return 0;
0054 }
0055
0056 static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base,
0057                struct mt76_reg_pair *data, int len)
0058 {
0059     while (len > 0) {
0060         data->value = mt76_mmio_rr(dev, data->reg);
0061         data++;
0062         len--;
0063     }
0064
0065     return 0;
0066 }
0067
0068 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
0069                u32 clear, u32 set)
0070 {
0071     unsigned long flags;
0072
0073     spin_lock_irqsave(&dev->mmio.irq_lock, flags);
0074     dev->mmio.irqmask &= ~clear;
0075     dev->mmio.irqmask |= set;
0076     if (addr) {
0077         if (mtk_wed_device_active(&dev->mmio.wed))
0078             mtk_wed_device_irq_set_mask(&dev->mmio.wed,
0079                             dev->mmio.irqmask);
0080         else
0081             mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
0082     }
0083     spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
0084 }
0085 EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
0086
0087 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
0088 {
0089     static const struct mt76_bus_ops mt76_mmio_ops = {
0090         .rr = mt76_mmio_rr,
0091         .rmw = mt76_mmio_rmw,
0092         .wr = mt76_mmio_wr,
0093         .write_copy = mt76_mmio_write_copy,
0094         .read_copy = mt76_mmio_read_copy,
0095         .wr_rp = mt76_mmio_wr_rp,
0096         .rd_rp = mt76_mmio_rd_rp,
0097         .type = MT76_BUS_MMIO,
0098     };
0099
0100     dev->bus = &mt76_mmio_ops;
0101     dev->mmio.regs = regs;
0102
0103     spin_lock_init(&dev->mmio.irq_lock);
0104 }
0105 EXPORT_SYMBOL_GPL(mt76_mmio_init);