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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
0004  */
0005 
0006 #include <linux/dma-mapping.h>
0007 #include "mt76.h"
0008 #include "dma.h"
0009 
0010 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
0011 
0012 #define Q_READ(_dev, _q, _field) ({                 \
0013     u32 _offset = offsetof(struct mt76_queue_regs, _field);     \
0014     u32 _val;                           \
0015     if ((_q)->flags & MT_QFLAG_WED)                 \
0016         _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed,   \
0017                            ((_q)->wed_regs +    \
0018                             _offset));      \
0019     else                                \
0020         _val = readl(&(_q)->regs->_field);          \
0021     _val;                               \
0022 })
0023 
0024 #define Q_WRITE(_dev, _q, _field, _val) do {                \
0025     u32 _offset = offsetof(struct mt76_queue_regs, _field);     \
0026     if ((_q)->flags & MT_QFLAG_WED)                 \
0027         mtk_wed_device_reg_write(&(_dev)->mmio.wed,     \
0028                      ((_q)->wed_regs + _offset),    \
0029                      _val);             \
0030     else                                \
0031         writel(_val, &(_q)->regs->_field);          \
0032 } while (0)
0033 
0034 #else
0035 
0036 #define Q_READ(_dev, _q, _field)    readl(&(_q)->regs->_field)
0037 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field)
0038 
0039 #endif
0040 
0041 static struct mt76_txwi_cache *
0042 mt76_alloc_txwi(struct mt76_dev *dev)
0043 {
0044     struct mt76_txwi_cache *t;
0045     dma_addr_t addr;
0046     u8 *txwi;
0047     int size;
0048 
0049     size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t));
0050     txwi = kzalloc(size, GFP_ATOMIC);
0051     if (!txwi)
0052         return NULL;
0053 
0054     addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size,
0055                   DMA_TO_DEVICE);
0056     t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size);
0057     t->dma_addr = addr;
0058 
0059     return t;
0060 }
0061 
0062 static struct mt76_txwi_cache *
0063 __mt76_get_txwi(struct mt76_dev *dev)
0064 {
0065     struct mt76_txwi_cache *t = NULL;
0066 
0067     spin_lock(&dev->lock);
0068     if (!list_empty(&dev->txwi_cache)) {
0069         t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache,
0070                      list);
0071         list_del(&t->list);
0072     }
0073     spin_unlock(&dev->lock);
0074 
0075     return t;
0076 }
0077 
0078 static struct mt76_txwi_cache *
0079 mt76_get_txwi(struct mt76_dev *dev)
0080 {
0081     struct mt76_txwi_cache *t = __mt76_get_txwi(dev);
0082 
0083     if (t)
0084         return t;
0085 
0086     return mt76_alloc_txwi(dev);
0087 }
0088 
0089 void
0090 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t)
0091 {
0092     if (!t)
0093         return;
0094 
0095     spin_lock(&dev->lock);
0096     list_add(&t->list, &dev->txwi_cache);
0097     spin_unlock(&dev->lock);
0098 }
0099 EXPORT_SYMBOL_GPL(mt76_put_txwi);
0100 
0101 static void
0102 mt76_free_pending_txwi(struct mt76_dev *dev)
0103 {
0104     struct mt76_txwi_cache *t;
0105 
0106     local_bh_disable();
0107     while ((t = __mt76_get_txwi(dev)) != NULL) {
0108         dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
0109                  DMA_TO_DEVICE);
0110         kfree(mt76_get_txwi_ptr(dev, t));
0111     }
0112     local_bh_enable();
0113 }
0114 
0115 static void
0116 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q)
0117 {
0118     Q_WRITE(dev, q, desc_base, q->desc_dma);
0119     Q_WRITE(dev, q, ring_size, q->ndesc);
0120     q->head = Q_READ(dev, q, dma_idx);
0121     q->tail = q->head;
0122 }
0123 
0124 static void
0125 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q)
0126 {
0127     int i;
0128 
0129     if (!q || !q->ndesc)
0130         return;
0131 
0132     /* clear descriptors */
0133     for (i = 0; i < q->ndesc; i++)
0134         q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
0135 
0136     Q_WRITE(dev, q, cpu_idx, 0);
0137     Q_WRITE(dev, q, dma_idx, 0);
0138     mt76_dma_sync_idx(dev, q);
0139 }
0140 
0141 static int
0142 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
0143          struct mt76_queue_buf *buf, int nbufs, u32 info,
0144          struct sk_buff *skb, void *txwi)
0145 {
0146     struct mt76_queue_entry *entry;
0147     struct mt76_desc *desc;
0148     u32 ctrl;
0149     int i, idx = -1;
0150 
0151     if (txwi) {
0152         q->entry[q->head].txwi = DMA_DUMMY_DATA;
0153         q->entry[q->head].skip_buf0 = true;
0154     }
0155 
0156     for (i = 0; i < nbufs; i += 2, buf += 2) {
0157         u32 buf0 = buf[0].addr, buf1 = 0;
0158 
0159         idx = q->head;
0160         q->head = (q->head + 1) % q->ndesc;
0161 
0162         desc = &q->desc[idx];
0163         entry = &q->entry[idx];
0164 
0165         if (buf[0].skip_unmap)
0166             entry->skip_buf0 = true;
0167         entry->skip_buf1 = i == nbufs - 1;
0168 
0169         entry->dma_addr[0] = buf[0].addr;
0170         entry->dma_len[0] = buf[0].len;
0171 
0172         ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len);
0173         if (i < nbufs - 1) {
0174             entry->dma_addr[1] = buf[1].addr;
0175             entry->dma_len[1] = buf[1].len;
0176             buf1 = buf[1].addr;
0177             ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len);
0178             if (buf[1].skip_unmap)
0179                 entry->skip_buf1 = true;
0180         }
0181 
0182         if (i == nbufs - 1)
0183             ctrl |= MT_DMA_CTL_LAST_SEC0;
0184         else if (i == nbufs - 2)
0185             ctrl |= MT_DMA_CTL_LAST_SEC1;
0186 
0187         WRITE_ONCE(desc->buf0, cpu_to_le32(buf0));
0188         WRITE_ONCE(desc->buf1, cpu_to_le32(buf1));
0189         WRITE_ONCE(desc->info, cpu_to_le32(info));
0190         WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
0191 
0192         q->queued++;
0193     }
0194 
0195     q->entry[idx].txwi = txwi;
0196     q->entry[idx].skb = skb;
0197     q->entry[idx].wcid = 0xffff;
0198 
0199     return idx;
0200 }
0201 
0202 static void
0203 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx,
0204             struct mt76_queue_entry *prev_e)
0205 {
0206     struct mt76_queue_entry *e = &q->entry[idx];
0207 
0208     if (!e->skip_buf0)
0209         dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0],
0210                  DMA_TO_DEVICE);
0211 
0212     if (!e->skip_buf1)
0213         dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1],
0214                  DMA_TO_DEVICE);
0215 
0216     if (e->txwi == DMA_DUMMY_DATA)
0217         e->txwi = NULL;
0218 
0219     if (e->skb == DMA_DUMMY_DATA)
0220         e->skb = NULL;
0221 
0222     *prev_e = *e;
0223     memset(e, 0, sizeof(*e));
0224 }
0225 
0226 static void
0227 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q)
0228 {
0229     wmb();
0230     Q_WRITE(dev, q, cpu_idx, q->head);
0231 }
0232 
0233 static void
0234 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush)
0235 {
0236     struct mt76_queue_entry entry;
0237     int last;
0238 
0239     if (!q || !q->ndesc)
0240         return;
0241 
0242     spin_lock_bh(&q->cleanup_lock);
0243     if (flush)
0244         last = -1;
0245     else
0246         last = Q_READ(dev, q, dma_idx);
0247 
0248     while (q->queued > 0 && q->tail != last) {
0249         mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry);
0250         mt76_queue_tx_complete(dev, q, &entry);
0251 
0252         if (entry.txwi) {
0253             if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE))
0254                 mt76_put_txwi(dev, entry.txwi);
0255         }
0256 
0257         if (!flush && q->tail == last)
0258             last = Q_READ(dev, q, dma_idx);
0259     }
0260     spin_unlock_bh(&q->cleanup_lock);
0261 
0262     if (flush) {
0263         spin_lock_bh(&q->lock);
0264         mt76_dma_sync_idx(dev, q);
0265         mt76_dma_kick_queue(dev, q);
0266         spin_unlock_bh(&q->lock);
0267     }
0268 
0269     if (!q->queued)
0270         wake_up(&dev->tx_wait);
0271 }
0272 
0273 static void *
0274 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx,
0275          int *len, u32 *info, bool *more)
0276 {
0277     struct mt76_queue_entry *e = &q->entry[idx];
0278     struct mt76_desc *desc = &q->desc[idx];
0279     dma_addr_t buf_addr;
0280     void *buf = e->buf;
0281     int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
0282 
0283     buf_addr = e->dma_addr[0];
0284     if (len) {
0285         u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl));
0286         *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl);
0287         *more = !(ctl & MT_DMA_CTL_LAST_SEC0);
0288     }
0289 
0290     if (info)
0291         *info = le32_to_cpu(desc->info);
0292 
0293     dma_unmap_single(dev->dma_dev, buf_addr, buf_len, DMA_FROM_DEVICE);
0294     e->buf = NULL;
0295 
0296     return buf;
0297 }
0298 
0299 static void *
0300 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
0301          int *len, u32 *info, bool *more)
0302 {
0303     int idx = q->tail;
0304 
0305     *more = false;
0306     if (!q->queued)
0307         return NULL;
0308 
0309     if (flush)
0310         q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE);
0311     else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE)))
0312         return NULL;
0313 
0314     q->tail = (q->tail + 1) % q->ndesc;
0315     q->queued--;
0316 
0317     return mt76_dma_get_buf(dev, q, idx, len, info, more);
0318 }
0319 
0320 static int
0321 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q,
0322               struct sk_buff *skb, u32 tx_info)
0323 {
0324     struct mt76_queue_buf buf = {};
0325     dma_addr_t addr;
0326 
0327     if (q->queued + 1 >= q->ndesc - 1)
0328         goto error;
0329 
0330     addr = dma_map_single(dev->dma_dev, skb->data, skb->len,
0331                   DMA_TO_DEVICE);
0332     if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
0333         goto error;
0334 
0335     buf.addr = addr;
0336     buf.len = skb->len;
0337 
0338     spin_lock_bh(&q->lock);
0339     mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
0340     mt76_dma_kick_queue(dev, q);
0341     spin_unlock_bh(&q->lock);
0342 
0343     return 0;
0344 
0345 error:
0346     dev_kfree_skb(skb);
0347     return -ENOMEM;
0348 }
0349 
0350 static int
0351 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q,
0352               enum mt76_txq_id qid, struct sk_buff *skb,
0353               struct mt76_wcid *wcid, struct ieee80211_sta *sta)
0354 {
0355     struct ieee80211_tx_status status = {
0356         .sta = sta,
0357     };
0358     struct mt76_tx_info tx_info = {
0359         .skb = skb,
0360     };
0361     struct ieee80211_hw *hw;
0362     int len, n = 0, ret = -ENOMEM;
0363     struct mt76_txwi_cache *t;
0364     struct sk_buff *iter;
0365     dma_addr_t addr;
0366     u8 *txwi;
0367 
0368     t = mt76_get_txwi(dev);
0369     if (!t)
0370         goto free_skb;
0371 
0372     txwi = mt76_get_txwi_ptr(dev, t);
0373 
0374     skb->prev = skb->next = NULL;
0375     if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS)
0376         mt76_insert_hdr_pad(skb);
0377 
0378     len = skb_headlen(skb);
0379     addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE);
0380     if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
0381         goto free;
0382 
0383     tx_info.buf[n].addr = t->dma_addr;
0384     tx_info.buf[n++].len = dev->drv->txwi_size;
0385     tx_info.buf[n].addr = addr;
0386     tx_info.buf[n++].len = len;
0387 
0388     skb_walk_frags(skb, iter) {
0389         if (n == ARRAY_SIZE(tx_info.buf))
0390             goto unmap;
0391 
0392         addr = dma_map_single(dev->dma_dev, iter->data, iter->len,
0393                       DMA_TO_DEVICE);
0394         if (unlikely(dma_mapping_error(dev->dma_dev, addr)))
0395             goto unmap;
0396 
0397         tx_info.buf[n].addr = addr;
0398         tx_info.buf[n++].len = iter->len;
0399     }
0400     tx_info.nbuf = n;
0401 
0402     if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) {
0403         ret = -ENOMEM;
0404         goto unmap;
0405     }
0406 
0407     dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
0408                 DMA_TO_DEVICE);
0409     ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info);
0410     dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size,
0411                    DMA_TO_DEVICE);
0412     if (ret < 0)
0413         goto unmap;
0414 
0415     return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf,
0416                 tx_info.info, tx_info.skb, t);
0417 
0418 unmap:
0419     for (n--; n > 0; n--)
0420         dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr,
0421                  tx_info.buf[n].len, DMA_TO_DEVICE);
0422 
0423 free:
0424 #ifdef CONFIG_NL80211_TESTMODE
0425     /* fix tx_done accounting on queue overflow */
0426     if (mt76_is_testmode_skb(dev, skb, &hw)) {
0427         struct mt76_phy *phy = hw->priv;
0428 
0429         if (tx_info.skb == phy->test.tx_skb)
0430             phy->test.tx_done--;
0431     }
0432 #endif
0433 
0434     mt76_put_txwi(dev, t);
0435 
0436 free_skb:
0437     status.skb = tx_info.skb;
0438     hw = mt76_tx_status_get_hw(dev, tx_info.skb);
0439     ieee80211_tx_status_ext(hw, &status);
0440 
0441     return ret;
0442 }
0443 
0444 static int
0445 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q)
0446 {
0447     dma_addr_t addr;
0448     void *buf;
0449     int frames = 0;
0450     int len = SKB_WITH_OVERHEAD(q->buf_size);
0451     int offset = q->buf_offset;
0452 
0453     if (!q->ndesc)
0454         return 0;
0455 
0456     spin_lock_bh(&q->lock);
0457 
0458     while (q->queued < q->ndesc - 1) {
0459         struct mt76_queue_buf qbuf;
0460 
0461         buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC);
0462         if (!buf)
0463             break;
0464 
0465         addr = dma_map_single(dev->dma_dev, buf, len, DMA_FROM_DEVICE);
0466         if (unlikely(dma_mapping_error(dev->dma_dev, addr))) {
0467             skb_free_frag(buf);
0468             break;
0469         }
0470 
0471         qbuf.addr = addr + offset;
0472         qbuf.len = len - offset;
0473         qbuf.skip_unmap = false;
0474         mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL);
0475         frames++;
0476     }
0477 
0478     if (frames)
0479         mt76_dma_kick_queue(dev, q);
0480 
0481     spin_unlock_bh(&q->lock);
0482 
0483     return frames;
0484 }
0485 
0486 static int
0487 mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q)
0488 {
0489 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
0490     struct mtk_wed_device *wed = &dev->mmio.wed;
0491     int ret, type, ring;
0492     u8 flags = q->flags;
0493 
0494     if (!mtk_wed_device_active(wed))
0495         q->flags &= ~MT_QFLAG_WED;
0496 
0497     if (!(q->flags & MT_QFLAG_WED))
0498         return 0;
0499 
0500     type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags);
0501     ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags);
0502 
0503     switch (type) {
0504     case MT76_WED_Q_TX:
0505         ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs);
0506         if (!ret)
0507             q->wed_regs = wed->tx_ring[ring].reg_base;
0508         break;
0509     case MT76_WED_Q_TXFREE:
0510         /* WED txfree queue needs ring to be initialized before setup */
0511         q->flags = 0;
0512         mt76_dma_queue_reset(dev, q);
0513         mt76_dma_rx_fill(dev, q);
0514         q->flags = flags;
0515 
0516         ret = mtk_wed_device_txfree_ring_setup(wed, q->regs);
0517         if (!ret)
0518             q->wed_regs = wed->txfree_ring.reg_base;
0519         break;
0520     default:
0521         ret = -EINVAL;
0522     }
0523 
0524     return ret;
0525 #else
0526     return 0;
0527 #endif
0528 }
0529 
0530 static int
0531 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q,
0532              int idx, int n_desc, int bufsize,
0533              u32 ring_base)
0534 {
0535     int ret, size;
0536 
0537     spin_lock_init(&q->lock);
0538     spin_lock_init(&q->cleanup_lock);
0539 
0540     q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
0541     q->ndesc = n_desc;
0542     q->buf_size = bufsize;
0543     q->hw_idx = idx;
0544 
0545     size = q->ndesc * sizeof(struct mt76_desc);
0546     q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL);
0547     if (!q->desc)
0548         return -ENOMEM;
0549 
0550     size = q->ndesc * sizeof(*q->entry);
0551     q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL);
0552     if (!q->entry)
0553         return -ENOMEM;
0554 
0555     ret = mt76_dma_wed_setup(dev, q);
0556     if (ret)
0557         return ret;
0558 
0559     if (q->flags != MT_WED_Q_TXFREE)
0560         mt76_dma_queue_reset(dev, q);
0561 
0562     return 0;
0563 }
0564 
0565 static void
0566 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q)
0567 {
0568     struct page *page;
0569     void *buf;
0570     bool more;
0571 
0572     if (!q->ndesc)
0573         return;
0574 
0575     spin_lock_bh(&q->lock);
0576     do {
0577         buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more);
0578         if (!buf)
0579             break;
0580 
0581         skb_free_frag(buf);
0582     } while (1);
0583     spin_unlock_bh(&q->lock);
0584 
0585     if (!q->rx_page.va)
0586         return;
0587 
0588     page = virt_to_page(q->rx_page.va);
0589     __page_frag_cache_drain(page, q->rx_page.pagecnt_bias);
0590     memset(&q->rx_page, 0, sizeof(q->rx_page));
0591 }
0592 
0593 static void
0594 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid)
0595 {
0596     struct mt76_queue *q = &dev->q_rx[qid];
0597     int i;
0598 
0599     if (!q->ndesc)
0600         return;
0601 
0602     for (i = 0; i < q->ndesc; i++)
0603         q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE);
0604 
0605     mt76_dma_rx_cleanup(dev, q);
0606     mt76_dma_sync_idx(dev, q);
0607     mt76_dma_rx_fill(dev, q);
0608 
0609     if (!q->rx_head)
0610         return;
0611 
0612     dev_kfree_skb(q->rx_head);
0613     q->rx_head = NULL;
0614 }
0615 
0616 static void
0617 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data,
0618           int len, bool more)
0619 {
0620     struct sk_buff *skb = q->rx_head;
0621     struct skb_shared_info *shinfo = skb_shinfo(skb);
0622     int nr_frags = shinfo->nr_frags;
0623 
0624     if (nr_frags < ARRAY_SIZE(shinfo->frags)) {
0625         struct page *page = virt_to_head_page(data);
0626         int offset = data - page_address(page) + q->buf_offset;
0627 
0628         skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size);
0629     } else {
0630         skb_free_frag(data);
0631     }
0632 
0633     if (more)
0634         return;
0635 
0636     q->rx_head = NULL;
0637     if (nr_frags < ARRAY_SIZE(shinfo->frags))
0638         dev->drv->rx_skb(dev, q - dev->q_rx, skb);
0639     else
0640         dev_kfree_skb(skb);
0641 }
0642 
0643 static int
0644 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget)
0645 {
0646     int len, data_len, done = 0, dma_idx;
0647     struct sk_buff *skb;
0648     unsigned char *data;
0649     bool check_ddone = false;
0650     bool more;
0651 
0652     if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) &&
0653         q->flags == MT_WED_Q_TXFREE) {
0654         dma_idx = Q_READ(dev, q, dma_idx);
0655         check_ddone = true;
0656     }
0657 
0658     while (done < budget) {
0659         u32 info;
0660 
0661         if (check_ddone) {
0662             if (q->tail == dma_idx)
0663                 dma_idx = Q_READ(dev, q, dma_idx);
0664 
0665             if (q->tail == dma_idx)
0666                 break;
0667         }
0668 
0669         data = mt76_dma_dequeue(dev, q, false, &len, &info, &more);
0670         if (!data)
0671             break;
0672 
0673         if (q->rx_head)
0674             data_len = q->buf_size;
0675         else
0676             data_len = SKB_WITH_OVERHEAD(q->buf_size);
0677 
0678         if (data_len < len + q->buf_offset) {
0679             dev_kfree_skb(q->rx_head);
0680             q->rx_head = NULL;
0681             goto free_frag;
0682         }
0683 
0684         if (q->rx_head) {
0685             mt76_add_fragment(dev, q, data, len, more);
0686             continue;
0687         }
0688 
0689         if (!more && dev->drv->rx_check &&
0690             !(dev->drv->rx_check(dev, data, len)))
0691             goto free_frag;
0692 
0693         skb = build_skb(data, q->buf_size);
0694         if (!skb)
0695             goto free_frag;
0696 
0697         skb_reserve(skb, q->buf_offset);
0698 
0699         if (q == &dev->q_rx[MT_RXQ_MCU]) {
0700             u32 *rxfce = (u32 *)skb->cb;
0701             *rxfce = info;
0702         }
0703 
0704         __skb_put(skb, len);
0705         done++;
0706 
0707         if (more) {
0708             q->rx_head = skb;
0709             continue;
0710         }
0711 
0712         dev->drv->rx_skb(dev, q - dev->q_rx, skb);
0713         continue;
0714 
0715 free_frag:
0716         skb_free_frag(data);
0717     }
0718 
0719     mt76_dma_rx_fill(dev, q);
0720     return done;
0721 }
0722 
0723 int mt76_dma_rx_poll(struct napi_struct *napi, int budget)
0724 {
0725     struct mt76_dev *dev;
0726     int qid, done = 0, cur;
0727 
0728     dev = container_of(napi->dev, struct mt76_dev, napi_dev);
0729     qid = napi - dev->napi;
0730 
0731     rcu_read_lock();
0732 
0733     do {
0734         cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done);
0735         mt76_rx_poll_complete(dev, qid, napi);
0736         done += cur;
0737     } while (cur && done < budget);
0738 
0739     rcu_read_unlock();
0740 
0741     if (done < budget && napi_complete(napi))
0742         dev->drv->rx_poll_complete(dev, qid);
0743 
0744     return done;
0745 }
0746 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll);
0747 
0748 static int
0749 mt76_dma_init(struct mt76_dev *dev,
0750           int (*poll)(struct napi_struct *napi, int budget))
0751 {
0752     int i;
0753 
0754     init_dummy_netdev(&dev->napi_dev);
0755     init_dummy_netdev(&dev->tx_napi_dev);
0756     snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s",
0757          wiphy_name(dev->hw->wiphy));
0758     dev->napi_dev.threaded = 1;
0759 
0760     mt76_for_each_q_rx(dev, i) {
0761         netif_napi_add(&dev->napi_dev, &dev->napi[i], poll, 64);
0762         mt76_dma_rx_fill(dev, &dev->q_rx[i]);
0763         napi_enable(&dev->napi[i]);
0764     }
0765 
0766     return 0;
0767 }
0768 
0769 static const struct mt76_queue_ops mt76_dma_ops = {
0770     .init = mt76_dma_init,
0771     .alloc = mt76_dma_alloc_queue,
0772     .reset_q = mt76_dma_queue_reset,
0773     .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
0774     .tx_queue_skb = mt76_dma_tx_queue_skb,
0775     .tx_cleanup = mt76_dma_tx_cleanup,
0776     .rx_cleanup = mt76_dma_rx_cleanup,
0777     .rx_reset = mt76_dma_rx_reset,
0778     .kick = mt76_dma_kick_queue,
0779 };
0780 
0781 void mt76_dma_attach(struct mt76_dev *dev)
0782 {
0783     dev->queue_ops = &mt76_dma_ops;
0784 }
0785 EXPORT_SYMBOL_GPL(mt76_dma_attach);
0786 
0787 void mt76_dma_cleanup(struct mt76_dev *dev)
0788 {
0789     int i;
0790 
0791     mt76_worker_disable(&dev->tx_worker);
0792     netif_napi_del(&dev->tx_napi);
0793 
0794     for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
0795         struct mt76_phy *phy = dev->phys[i];
0796         int j;
0797 
0798         if (!phy)
0799             continue;
0800 
0801         for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++)
0802             mt76_dma_tx_cleanup(dev, phy->q_tx[j], true);
0803     }
0804 
0805     for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++)
0806         mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true);
0807 
0808     mt76_for_each_q_rx(dev, i) {
0809         netif_napi_del(&dev->napi[i]);
0810         mt76_dma_rx_cleanup(dev, &dev->q_rx[i]);
0811     }
0812 
0813     mt76_free_pending_txwi(dev);
0814 
0815     if (mtk_wed_device_active(&dev->mmio.wed))
0816         mtk_wed_device_detach(&dev->mmio.wed);
0817 }
0818 EXPORT_SYMBOL_GPL(mt76_dma_cleanup);
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