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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * NXP Wireless LAN device driver: SDIO specific definitions
0004  *
0005  * Copyright 2011-2020 NXP
0006  */
0007 
0008 #ifndef _MWIFIEX_SDIO_H
0009 #define _MWIFIEX_SDIO_H
0010 
0011 
0012 #include <linux/completion.h>
0013 #include <linux/mmc/sdio.h>
0014 #include <linux/mmc/sdio_ids.h>
0015 #include <linux/mmc/sdio_func.h>
0016 #include <linux/mmc/card.h>
0017 #include <linux/mmc/host.h>
0018 
0019 #include "main.h"
0020 
0021 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
0022 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
0023 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
0024 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
0025 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
0026 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
0027 #define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
0028 #define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
0029 #define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
0030 #define SD8997_SDIOUART_FW_NAME "mrvl/sdiouart8997_combo_v4.bin"
0031 
0032 #define BLOCK_MODE  1
0033 #define BYTE_MODE   0
0034 
0035 #define MWIFIEX_SDIO_IO_PORT_MASK       0xfffff
0036 
0037 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
0038 
0039 #define MWIFIEX_MAX_FUNC2_REG_NUM   13
0040 #define MWIFIEX_SDIO_SCRATCH_SIZE   10
0041 
0042 #define SDIO_MPA_ADDR_BASE      0x1000
0043 #define CTRL_PORT           0
0044 #define CTRL_PORT_MASK          0x0001
0045 
0046 #define CMD_PORT_UPLD_INT_MASK      (0x1U<<6)
0047 #define CMD_PORT_DNLD_INT_MASK      (0x1U<<7)
0048 #define HOST_TERM_CMD53         (0x1U << 2)
0049 #define REG_PORT            0
0050 #define MEM_PORT            0x10000
0051 
0052 #define CMD53_NEW_MODE          (0x1U << 0)
0053 #define CMD_PORT_RD_LEN_EN      (0x1U << 2)
0054 #define CMD_PORT_AUTO_EN        (0x1U << 0)
0055 #define CMD_PORT_SLCT           0x8000
0056 #define UP_LD_CMD_PORT_HOST_INT_STATUS  (0x40U)
0057 #define DN_LD_CMD_PORT_HOST_INT_STATUS  (0x80U)
0058 
0059 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K    (16384)
0060 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K    (32768)
0061 /* we leave one block of 256 bytes for DMA alignment*/
0062 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX    (65280)
0063 
0064 /* Misc. Config Register : Auto Re-enable interrupts */
0065 #define AUTO_RE_ENABLE_INT              BIT(4)
0066 
0067 /* Host Control Registers : Configuration */
0068 #define CONFIGURATION_REG       0x00
0069 /* Host Control Registers : Host power up */
0070 #define HOST_POWER_UP           (0x1U << 1)
0071 
0072 /* Host Control Registers : Upload host interrupt mask */
0073 #define UP_LD_HOST_INT_MASK     (0x1U)
0074 /* Host Control Registers : Download host interrupt mask */
0075 #define DN_LD_HOST_INT_MASK     (0x2U)
0076 
0077 /* Host Control Registers : Upload host interrupt status */
0078 #define UP_LD_HOST_INT_STATUS       (0x1U)
0079 /* Host Control Registers : Download host interrupt status */
0080 #define DN_LD_HOST_INT_STATUS       (0x2U)
0081 
0082 /* Host Control Registers : Host interrupt status */
0083 #define CARD_INT_STATUS_REG     0x28
0084 
0085 /* Card Control Registers : Card I/O ready */
0086 #define CARD_IO_READY                   (0x1U << 3)
0087 /* Card Control Registers : Download card ready */
0088 #define DN_LD_CARD_RDY                  (0x1U << 0)
0089 
0090 /* Max retry number of CMD53 write */
0091 #define MAX_WRITE_IOMEM_RETRY       2
0092 
0093 /* SDIO Tx aggregation in progress ? */
0094 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
0095 
0096 /* SDIO Tx aggregation buffer room for next packet ? */
0097 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)    \
0098                         <= a->mpa_tx.buf_size)
0099 
0100 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
0101 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {      \
0102     memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],          \
0103             payload, pkt_len);              \
0104     a->mpa_tx.buf_len += pkt_len;                   \
0105     if (!a->mpa_tx.pkt_cnt)                     \
0106         a->mpa_tx.start_port = port;                \
0107     if (a->mpa_tx.start_port <= port)               \
0108         a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));        \
0109     else                                \
0110         a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+        \
0111                         (a->max_ports - \
0112                         a->mp_end_port)));  \
0113     a->mpa_tx.pkt_cnt++;                        \
0114 } while (0)
0115 
0116 /* SDIO Tx aggregation limit ? */
0117 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a)                 \
0118             (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
0119 
0120 /* Reset SDIO Tx aggregation buffer parameters */
0121 #define MP_TX_AGGR_BUF_RESET(a) do {                    \
0122     a->mpa_tx.pkt_cnt = 0;                      \
0123     a->mpa_tx.buf_len = 0;                      \
0124     a->mpa_tx.ports = 0;                        \
0125     a->mpa_tx.start_port = 0;                   \
0126 } while (0)
0127 
0128 /* SDIO Rx aggregation limit ? */
0129 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a)                 \
0130             (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
0131 
0132 /* SDIO Rx aggregation in progress ? */
0133 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
0134 
0135 /* SDIO Rx aggregation buffer room for next packet ? */
0136 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)              \
0137             ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
0138 
0139 /* Reset SDIO Rx aggregation buffer parameters */
0140 #define MP_RX_AGGR_BUF_RESET(a) do {                    \
0141     a->mpa_rx.pkt_cnt = 0;                      \
0142     a->mpa_rx.buf_len = 0;                      \
0143     a->mpa_rx.ports = 0;                        \
0144     a->mpa_rx.start_port = 0;                   \
0145 } while (0)
0146 
0147 /* data structure for SDIO MPA TX */
0148 struct mwifiex_sdio_mpa_tx {
0149     /* multiport tx aggregation buffer pointer */
0150     u8 *buf;
0151     u32 buf_len;
0152     u32 pkt_cnt;
0153     u32 ports;
0154     u16 start_port;
0155     u8 enabled;
0156     u32 buf_size;
0157     u32 pkt_aggr_limit;
0158 };
0159 
0160 struct mwifiex_sdio_mpa_rx {
0161     u8 *buf;
0162     u32 buf_len;
0163     u32 pkt_cnt;
0164     u32 ports;
0165     u16 start_port;
0166 
0167     struct sk_buff **skb_arr;
0168     u32 *len_arr;
0169 
0170     u8 enabled;
0171     u32 buf_size;
0172     u32 pkt_aggr_limit;
0173 };
0174 
0175 int mwifiex_bus_register(void);
0176 void mwifiex_bus_unregister(void);
0177 
0178 struct mwifiex_sdio_card_reg {
0179     u8 start_rd_port;
0180     u8 start_wr_port;
0181     u8 base_0_reg;
0182     u8 base_1_reg;
0183     u8 poll_reg;
0184     u8 host_int_enable;
0185     u8 host_int_rsr_reg;
0186     u8 host_int_status_reg;
0187     u8 host_int_mask_reg;
0188     u8 host_strap_reg;
0189     u8 host_strap_mask;
0190     u8 host_strap_value;
0191     u8 status_reg_0;
0192     u8 status_reg_1;
0193     u8 sdio_int_mask;
0194     u32 data_port_mask;
0195     u8 io_port_0_reg;
0196     u8 io_port_1_reg;
0197     u8 io_port_2_reg;
0198     u8 max_mp_regs;
0199     u8 rd_bitmap_l;
0200     u8 rd_bitmap_u;
0201     u8 rd_bitmap_1l;
0202     u8 rd_bitmap_1u;
0203     u8 wr_bitmap_l;
0204     u8 wr_bitmap_u;
0205     u8 wr_bitmap_1l;
0206     u8 wr_bitmap_1u;
0207     u8 rd_len_p0_l;
0208     u8 rd_len_p0_u;
0209     u8 card_misc_cfg_reg;
0210     u8 card_cfg_2_1_reg;
0211     u8 cmd_rd_len_0;
0212     u8 cmd_rd_len_1;
0213     u8 cmd_rd_len_2;
0214     u8 cmd_rd_len_3;
0215     u8 cmd_cfg_0;
0216     u8 cmd_cfg_1;
0217     u8 cmd_cfg_2;
0218     u8 cmd_cfg_3;
0219     u8 fw_dump_host_ready;
0220     u8 fw_dump_ctrl;
0221     u8 fw_dump_start;
0222     u8 fw_dump_end;
0223     u8 func1_dump_reg_start;
0224     u8 func1_dump_reg_end;
0225     u8 func1_scratch_reg;
0226     u8 func1_spec_reg_num;
0227     u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
0228 };
0229 
0230 struct sdio_mmc_card {
0231     struct sdio_func *func;
0232     struct mwifiex_adapter *adapter;
0233 
0234     struct completion fw_done;
0235     const char *firmware;
0236     const char *firmware_sdiouart;
0237     const struct mwifiex_sdio_card_reg *reg;
0238     u8 max_ports;
0239     u8 mp_agg_pkt_limit;
0240     u16 tx_buf_size;
0241     u32 mp_tx_agg_buf_size;
0242     u32 mp_rx_agg_buf_size;
0243 
0244     u32 mp_rd_bitmap;
0245     u32 mp_wr_bitmap;
0246 
0247     u16 mp_end_port;
0248     u32 mp_data_port_mask;
0249 
0250     u8 curr_rd_port;
0251     u8 curr_wr_port;
0252 
0253     u8 *mp_regs;
0254     bool supports_sdio_new_mode;
0255     bool has_control_mask;
0256     bool can_dump_fw;
0257     bool fw_dump_enh;
0258     bool can_auto_tdls;
0259     bool can_ext_scan;
0260 
0261     struct mwifiex_sdio_mpa_tx mpa_tx;
0262     struct mwifiex_sdio_mpa_rx mpa_rx;
0263 
0264     struct work_struct work;
0265     unsigned long work_flags;
0266 };
0267 
0268 struct mwifiex_sdio_device {
0269     const char *firmware;
0270     const char *firmware_sdiouart;
0271     const struct mwifiex_sdio_card_reg *reg;
0272     u8 max_ports;
0273     u8 mp_agg_pkt_limit;
0274     u16 tx_buf_size;
0275     u32 mp_tx_agg_buf_size;
0276     u32 mp_rx_agg_buf_size;
0277     bool supports_sdio_new_mode;
0278     bool has_control_mask;
0279     bool can_dump_fw;
0280     bool fw_dump_enh;
0281     bool can_auto_tdls;
0282     bool can_ext_scan;
0283 };
0284 
0285 /*
0286  * .cmdrsp_complete handler
0287  */
0288 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
0289                            struct sk_buff *skb)
0290 {
0291     dev_kfree_skb_any(skb);
0292     return 0;
0293 }
0294 
0295 /*
0296  * .event_complete handler
0297  */
0298 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
0299                           struct sk_buff *skb)
0300 {
0301     dev_kfree_skb_any(skb);
0302     return 0;
0303 }
0304 
0305 static inline bool
0306 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
0307 {
0308     u8 tmp;
0309 
0310     if (card->curr_rd_port < card->mpa_rx.start_port) {
0311         if (card->supports_sdio_new_mode)
0312             tmp = card->mp_end_port >> 1;
0313         else
0314             tmp = card->mp_agg_pkt_limit;
0315 
0316         if (((card->max_ports - card->mpa_rx.start_port) +
0317             card->curr_rd_port) >= tmp)
0318             return true;
0319     }
0320 
0321     if (!card->supports_sdio_new_mode)
0322         return false;
0323 
0324     if ((card->curr_rd_port - card->mpa_rx.start_port) >=
0325         (card->mp_end_port >> 1))
0326         return true;
0327 
0328     return false;
0329 }
0330 
0331 static inline bool
0332 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
0333 {
0334     u16 tmp;
0335 
0336     if (card->curr_wr_port < card->mpa_tx.start_port) {
0337         if (card->supports_sdio_new_mode)
0338             tmp = card->mp_end_port >> 1;
0339         else
0340             tmp = card->mp_agg_pkt_limit;
0341 
0342         if (((card->max_ports - card->mpa_tx.start_port) +
0343             card->curr_wr_port) >= tmp)
0344             return true;
0345     }
0346 
0347     if (!card->supports_sdio_new_mode)
0348         return false;
0349 
0350     if ((card->curr_wr_port - card->mpa_tx.start_port) >=
0351         (card->mp_end_port >> 1))
0352         return true;
0353 
0354     return false;
0355 }
0356 
0357 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
0358 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
0359                     u16 rx_len, u8 port)
0360 {
0361     card->mpa_rx.buf_len += rx_len;
0362 
0363     if (!card->mpa_rx.pkt_cnt)
0364         card->mpa_rx.start_port = port;
0365 
0366     if (card->supports_sdio_new_mode) {
0367         card->mpa_rx.ports |= (1 << port);
0368     } else {
0369         if (card->mpa_rx.start_port <= port)
0370             card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
0371         else
0372             card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
0373     }
0374     card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
0375     card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
0376     card->mpa_rx.pkt_cnt++;
0377 }
0378 #endif /* _MWIFIEX_SDIO_H */
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