marvell/mwifiex/pcie.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* @file mwifiex_pcie.h
0003  *
0004  * @brief This file contains definitions for PCI-E interface.
0005  * driver.
0006  *
0007  * Copyright 2011-2020 NXP
0008  */
0009
0010 #ifndef _MWIFIEX_PCIE_H
0011 #define _MWIFIEX_PCIE_H
0012
0013 #include    <linux/completion.h>
0014 #include    <linux/pci.h>
0015 #include    <linux/interrupt.h>
0016
0017 #include    "decl.h"
0018 #include    "main.h"
0019
0020 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
0021 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
0022 #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
0023 #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
0024 #define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin"
0025 #define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin"
0026
0027 #define PCIE_VENDOR_ID_MARVELL              (0x11ab)
0028 #define PCIE_VENDOR_ID_V2_MARVELL           (0x1b4b)
0029 #define PCIE_DEVICE_ID_MARVELL_88W8766P     (0x2b30)
0030 #define PCIE_DEVICE_ID_MARVELL_88W8897      (0x2b38)
0031 #define PCIE_DEVICE_ID_MARVELL_88W8997      (0x2b42)
0032
0033 #define PCIE8897_A0 0x1100
0034 #define PCIE8897_B0 0x1200
0035 #define PCIE8997_A0 0x10
0036 #define PCIE8997_A1 0x11
0037 #define CHIP_VER_PCIEUART   0x3
0038 #define CHIP_MAGIC_VALUE    0x24
0039
0040 /* Constants for Buffer Descriptor (BD) rings */
0041 #define MWIFIEX_MAX_TXRX_BD         0x20
0042 #define MWIFIEX_TXBD_MASK           0x3F
0043 #define MWIFIEX_RXBD_MASK           0x3F
0044
0045 #define MWIFIEX_MAX_EVT_BD          0x08
0046 #define MWIFIEX_EVTBD_MASK          0x0f
0047
0048 /* PCIE INTERNAL REGISTERS */
0049 #define PCIE_SCRATCH_0_REG              0xC10
0050 #define PCIE_SCRATCH_1_REG              0xC14
0051 #define PCIE_CPU_INT_EVENT              0xC18
0052 #define PCIE_CPU_INT_STATUS             0xC1C
0053 #define PCIE_HOST_INT_STATUS                0xC30
0054 #define PCIE_HOST_INT_MASK              0xC34
0055 #define PCIE_HOST_INT_STATUS_MASK           0xC3C
0056 #define PCIE_SCRATCH_2_REG              0xC40
0057 #define PCIE_SCRATCH_3_REG              0xC44
0058 #define PCIE_SCRATCH_4_REG              0xCD0
0059 #define PCIE_SCRATCH_5_REG              0xCD4
0060 #define PCIE_SCRATCH_6_REG              0xCD8
0061 #define PCIE_SCRATCH_7_REG              0xCDC
0062 #define PCIE_SCRATCH_8_REG              0xCE0
0063 #define PCIE_SCRATCH_9_REG              0xCE4
0064 #define PCIE_SCRATCH_10_REG             0xCE8
0065 #define PCIE_SCRATCH_11_REG             0xCEC
0066 #define PCIE_SCRATCH_12_REG             0xCF0
0067 #define PCIE_SCRATCH_13_REG             0xCF4
0068 #define PCIE_SCRATCH_14_REG             0xCF8
0069 #define PCIE_SCRATCH_15_REG             0xCFC
0070 #define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
0071 #define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C
0072
0073 #define CPU_INTR_DNLD_RDY               BIT(0)
0074 #define CPU_INTR_DOOR_BELL              BIT(1)
0075 #define CPU_INTR_SLEEP_CFM_DONE         BIT(2)
0076 #define CPU_INTR_RESET                  BIT(3)
0077 #define CPU_INTR_EVENT_DONE             BIT(5)
0078
0079 #define HOST_INTR_DNLD_DONE             BIT(0)
0080 #define HOST_INTR_UPLD_RDY              BIT(1)
0081 #define HOST_INTR_CMD_DONE              BIT(2)
0082 #define HOST_INTR_EVENT_RDY             BIT(3)
0083 #define HOST_INTR_MASK                  (HOST_INTR_DNLD_DONE | \
0084                              HOST_INTR_UPLD_RDY  | \
0085                              HOST_INTR_CMD_DONE  | \
0086                              HOST_INTR_EVENT_RDY)
0087
0088 #define MWIFIEX_BD_FLAG_ROLLOVER_IND            BIT(7)
0089 #define MWIFIEX_BD_FLAG_FIRST_DESC          BIT(0)
0090 #define MWIFIEX_BD_FLAG_LAST_DESC           BIT(1)
0091 #define MWIFIEX_BD_FLAG_SOP             BIT(0)
0092 #define MWIFIEX_BD_FLAG_EOP             BIT(1)
0093 #define MWIFIEX_BD_FLAG_XS_SOP              BIT(2)
0094 #define MWIFIEX_BD_FLAG_XS_EOP              BIT(3)
0095 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND        BIT(7)
0096 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND         BIT(10)
0097 #define MWIFIEX_BD_FLAG_TX_START_PTR            BIT(16)
0098 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND         BIT(26)
0099
0100 /* Max retry number of command write */
0101 #define MAX_WRITE_IOMEM_RETRY               2
0102 /* Define PCIE block size for firmware download */
0103 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD     256
0104 /* FW awake cookie after FW ready */
0105 #define FW_AWAKE_COOKIE                     (0xAA55AA55)
0106 #define MWIFIEX_DEF_SLEEP_COOKIE            0xBEEFBEEF
0107 #define MWIFIEX_SLEEP_COOKIE_SIZE           4
0108 #define MWIFIEX_MAX_DELAY_COUNT             100
0109
0110 #define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA
0111
0112 struct mwifiex_pcie_card_reg {
0113     u16 cmd_addr_lo;
0114     u16 cmd_addr_hi;
0115     u16 fw_status;
0116     u16 cmd_size;
0117     u16 cmdrsp_addr_lo;
0118     u16 cmdrsp_addr_hi;
0119     u16 tx_rdptr;
0120     u16 tx_wrptr;
0121     u16 rx_rdptr;
0122     u16 rx_wrptr;
0123     u16 evt_rdptr;
0124     u16 evt_wrptr;
0125     u16 drv_rdy;
0126     u16 tx_start_ptr;
0127     u32 tx_mask;
0128     u32 tx_wrap_mask;
0129     u32 rx_mask;
0130     u32 rx_wrap_mask;
0131     u32 tx_rollover_ind;
0132     u32 rx_rollover_ind;
0133     u32 evt_rollover_ind;
0134     u8 ring_flag_sop;
0135     u8 ring_flag_eop;
0136     u8 ring_flag_xs_sop;
0137     u8 ring_flag_xs_eop;
0138     u32 ring_tx_start_ptr;
0139     u8 pfu_enabled;
0140     u8 sleep_cookie;
0141     u16 fw_dump_ctrl;
0142     u16 fw_dump_start;
0143     u16 fw_dump_end;
0144     u8 fw_dump_host_ready;
0145     u8 fw_dump_read_done;
0146     u8 msix_support;
0147 };
0148
0149 struct mwifiex_pcie_device {
0150     const struct mwifiex_pcie_card_reg *reg;
0151     u16 blksz_fw_dl;
0152     u16 tx_buf_size;
0153     bool can_dump_fw;
0154     struct memory_type_mapping *mem_type_mapping_tbl;
0155     u8 num_mem_types;
0156     bool can_ext_scan;
0157 };
0158
0159 struct mwifiex_evt_buf_desc {
0160     u64 paddr;
0161     u16 len;
0162     u16 flags;
0163 } __packed;
0164
0165 struct mwifiex_pcie_buf_desc {
0166     u64 paddr;
0167     u16 len;
0168     u16 flags;
0169 } __packed;
0170
0171 struct mwifiex_pfu_buf_desc {
0172     u16 flags;
0173     u16 offset;
0174     u16 frag_len;
0175     u16 len;
0176     u64 paddr;
0177     u32 reserved;
0178 } __packed;
0179
0180 #define MWIFIEX_NUM_MSIX_VECTORS   4
0181
0182 struct mwifiex_msix_context {
0183     struct pci_dev *dev;
0184     u16 msg_id;
0185 };
0186
0187 struct pcie_service_card {
0188     struct pci_dev *dev;
0189     struct mwifiex_adapter *adapter;
0190     struct mwifiex_pcie_device pcie;
0191     struct completion fw_done;
0192
0193     u8 txbd_flush;
0194     u32 txbd_wrptr;
0195     u32 txbd_rdptr;
0196     u32 txbd_ring_size;
0197     u8 *txbd_ring_vbase;
0198     dma_addr_t txbd_ring_pbase;
0199     void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
0200     struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
0201
0202     u32 rxbd_wrptr;
0203     u32 rxbd_rdptr;
0204     u32 rxbd_ring_size;
0205     u8 *rxbd_ring_vbase;
0206     dma_addr_t rxbd_ring_pbase;
0207     void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
0208     struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
0209
0210     u32 evtbd_wrptr;
0211     u32 evtbd_rdptr;
0212     u32 evtbd_ring_size;
0213     u8 *evtbd_ring_vbase;
0214     dma_addr_t evtbd_ring_pbase;
0215     void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
0216     struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
0217
0218     struct sk_buff *cmd_buf;
0219     struct sk_buff *cmdrsp_buf;
0220     u8 *sleep_cookie_vbase;
0221     dma_addr_t sleep_cookie_pbase;
0222     void __iomem *pci_mmap;
0223     void __iomem *pci_mmap1;
0224     int msi_enable;
0225     int msix_enable;
0226 #ifdef CONFIG_PCI
0227     struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
0228 #endif
0229     struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
0230     struct mwifiex_msix_context share_irq_ctx;
0231     struct work_struct work;
0232     unsigned long work_flags;
0233
0234     bool pci_reset_ongoing;
0235     unsigned long quirks;
0236 };
0237
0238 static inline int
0239 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
0240 {
0241     const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0242
0243     switch (card->dev->device) {
0244     case PCIE_DEVICE_ID_MARVELL_88W8766P:
0245         if (((card->txbd_wrptr & reg->tx_mask) ==
0246              (rdptr & reg->tx_mask)) &&
0247             ((card->txbd_wrptr & reg->tx_rollover_ind) !=
0248              (rdptr & reg->tx_rollover_ind)))
0249             return 1;
0250         break;
0251     case PCIE_DEVICE_ID_MARVELL_88W8897:
0252     case PCIE_DEVICE_ID_MARVELL_88W8997:
0253         if (((card->txbd_wrptr & reg->tx_mask) ==
0254              (rdptr & reg->tx_mask)) &&
0255             ((card->txbd_wrptr & reg->tx_rollover_ind) ==
0256             (rdptr & reg->tx_rollover_ind)))
0257             return 1;
0258         break;
0259     }
0260
0261     return 0;
0262 }
0263
0264 static inline int
0265 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
0266 {
0267     const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
0268
0269     switch (card->dev->device) {
0270     case PCIE_DEVICE_ID_MARVELL_88W8766P:
0271         if (((card->txbd_wrptr & reg->tx_mask) !=
0272              (card->txbd_rdptr & reg->tx_mask)) ||
0273             ((card->txbd_wrptr & reg->tx_rollover_ind) !=
0274              (card->txbd_rdptr & reg->tx_rollover_ind)))
0275             return 1;
0276         break;
0277     case PCIE_DEVICE_ID_MARVELL_88W8897:
0278     case PCIE_DEVICE_ID_MARVELL_88W8997:
0279         if (((card->txbd_wrptr & reg->tx_mask) !=
0280              (card->txbd_rdptr & reg->tx_mask)) ||
0281             ((card->txbd_wrptr & reg->tx_rollover_ind) ==
0282              (card->txbd_rdptr & reg->tx_rollover_ind)))
0283             return 1;
0284         break;
0285     }
0286
0287     return 0;
0288 }
0289
0290 #endif /* _MWIFIEX_PCIE_H */