marvell/libertas/if_spi.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  linux/drivers/net/wireless/libertas/if_spi.c
0004  *
0005  *  Driver for Marvell SPI WLAN cards.
0006  *
0007  *  Copyright 2008 Analog Devices Inc.
0008  *
0009  *  Authors:
0010  *  Andrey Yurovsky <andrey@cozybit.com>
0011  *  Colin McCabe <colin@cozybit.com>
0012  */
0013
0014 #ifndef _LBS_IF_SPI_H_
0015 #define _LBS_IF_SPI_H_
0016
0017 #define IPFIELD_ALIGN_OFFSET 2
0018 #define IF_SPI_CMD_BUF_SIZE 2400
0019
0020 /***************** Firmware *****************/
0021
0022 #define IF_SPI_FW_NAME_MAX 30
0023
0024 #define MAX_MAIN_FW_LOAD_CRC_ERR 10
0025
0026 /* Chunk size when loading the helper firmware */
0027 #define HELPER_FW_LOAD_CHUNK_SZ 64
0028
0029 /* Value to write to indicate end of helper firmware dnld */
0030 #define FIRMWARE_DNLD_OK 0x0000
0031
0032 /* Value to check once the main firmware is downloaded */
0033 #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888
0034
0035 /***************** SPI Interface Unit *****************/
0036 /* Masks used in SPI register read/write operations */
0037 #define IF_SPI_READ_OPERATION_MASK 0x0
0038 #define IF_SPI_WRITE_OPERATION_MASK 0x8000
0039
0040 /* SPI register offsets. 4-byte aligned. */
0041 #define IF_SPI_DEVICEID_CTRL_REG 0x00   /* DeviceID controller reg */
0042 #define IF_SPI_IO_READBASE_REG 0x04     /* Read I/O base reg */
0043 #define IF_SPI_IO_WRITEBASE_REG 0x08    /* Write I/O base reg */
0044 #define IF_SPI_IO_RDWRPORT_REG 0x0C /* Read/Write I/O port reg */
0045
0046 #define IF_SPI_CMD_READBASE_REG 0x10    /* Read command base reg */
0047 #define IF_SPI_CMD_WRITEBASE_REG 0x14   /* Write command base reg */
0048 #define IF_SPI_CMD_RDWRPORT_REG 0x18    /* Read/Write command port reg */
0049
0050 #define IF_SPI_DATA_READBASE_REG 0x1C   /* Read data base reg */
0051 #define IF_SPI_DATA_WRITEBASE_REG 0x20  /* Write data base reg */
0052 #define IF_SPI_DATA_RDWRPORT_REG 0x24   /* Read/Write data port reg */
0053
0054 #define IF_SPI_SCRATCH_1_REG 0x28   /* Scratch reg 1 */
0055 #define IF_SPI_SCRATCH_2_REG 0x2C   /* Scratch reg 2 */
0056 #define IF_SPI_SCRATCH_3_REG 0x30   /* Scratch reg 3 */
0057 #define IF_SPI_SCRATCH_4_REG 0x34   /* Scratch reg 4 */
0058
0059 #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */
0060 #define IF_SPI_TX_FRAME_STATUS_REG 0x3C /* Tx frame status reg */
0061
0062 #define IF_SPI_HOST_INT_CTRL_REG 0x40   /* Host interrupt controller reg */
0063
0064 #define IF_SPI_CARD_INT_CAUSE_REG 0x44  /* Card interrupt cause reg */
0065 #define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */
0066 #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */
0067 #define IF_SPI_CARD_INT_STATUS_MASK_REG 0x50 /* Card interrupt status mask */
0068
0069 #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */
0070
0071 #define IF_SPI_HOST_INT_CAUSE_REG 0x58  /* Host interrupt cause reg */
0072 #define IF_SPI_HOST_INT_STATUS_REG 0x5C /* Host interrupt status reg */
0073 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */
0074 #define IF_SPI_HOST_INT_STATUS_MASK_REG 0x64 /* Host interrupt status mask */
0075 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */
0076
0077 #define IF_SPI_DELAY_READ_REG 0x6C  /* Delay read reg */
0078 #define IF_SPI_SPU_BUS_MODE_REG 0x70    /* SPU BUS mode reg */
0079
0080 /***************** IF_SPI_DEVICEID_CTRL_REG *****************/
0081 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
0082 #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
0083
0084 /***************** IF_SPI_HOST_INT_CTRL_REG *****************/
0085 /* Host Interrupt Control bit : Wake up */
0086 #define IF_SPI_HICT_WAKE_UP             (1<<0)
0087 /* Host Interrupt Control bit : WLAN ready */
0088 #define IF_SPI_HICT_WLAN_READY              (1<<1)
0089 /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY     (1<<2) */
0090 /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY        (1<<3) */
0091 /*#define IF_SPI_HICT_IRQSRC_WLAN           (1<<4) */
0092 /* Host Interrupt Control bit : Tx auto download */
0093 #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO       (1<<5)
0094 /* Host Interrupt Control bit : Rx auto upload */
0095 #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO         (1<<6)
0096 /* Host Interrupt Control bit : Command auto download */
0097 #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO      (1<<7)
0098 /* Host Interrupt Control bit : Command auto upload */
0099 #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO        (1<<8)
0100
0101 /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/
0102 /* Card Interrupt Case bit : Tx download over */
0103 #define IF_SPI_CIC_TX_DOWNLOAD_OVER         (1<<0)
0104 /* Card Interrupt Case bit : Rx upload over */
0105 #define IF_SPI_CIC_RX_UPLOAD_OVER           (1<<1)
0106 /* Card Interrupt Case bit : Command download over */
0107 #define IF_SPI_CIC_CMD_DOWNLOAD_OVER            (1<<2)
0108 /* Card Interrupt Case bit : Host event */
0109 #define IF_SPI_CIC_HOST_EVENT               (1<<3)
0110 /* Card Interrupt Case bit : Command upload over */
0111 #define IF_SPI_CIC_CMD_UPLOAD_OVER          (1<<4)
0112 /* Card Interrupt Case bit : Power down */
0113 #define IF_SPI_CIC_POWER_DOWN               (1<<5)
0114
0115 /***************** IF_SPI_CARD_INT_STATUS_REG *****************/
0116 #define IF_SPI_CIS_TX_DOWNLOAD_OVER         (1<<0)
0117 #define IF_SPI_CIS_RX_UPLOAD_OVER           (1<<1)
0118 #define IF_SPI_CIS_CMD_DOWNLOAD_OVER            (1<<2)
0119 #define IF_SPI_CIS_HOST_EVENT               (1<<3)
0120 #define IF_SPI_CIS_CMD_UPLOAD_OVER          (1<<4)
0121 #define IF_SPI_CIS_POWER_DOWN               (1<<5)
0122
0123 /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/
0124 #define IF_SPI_HICU_TX_DOWNLOAD_RDY         (1<<0)
0125 #define IF_SPI_HICU_RX_UPLOAD_RDY           (1<<1)
0126 #define IF_SPI_HICU_CMD_DOWNLOAD_RDY            (1<<2)
0127 #define IF_SPI_HICU_CARD_EVENT              (1<<3)
0128 #define IF_SPI_HICU_CMD_UPLOAD_RDY          (1<<4)
0129 #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW         (1<<5)
0130 #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW        (1<<6)
0131 #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW       (1<<7)
0132 #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW      (1<<8)
0133 #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW        (1<<9)
0134 #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW       (1<<10)
0135
0136 /***************** IF_SPI_HOST_INT_STATUS_REG *****************/
0137 /* Host Interrupt Status bit : Tx download ready */
0138 #define IF_SPI_HIST_TX_DOWNLOAD_RDY         (1<<0)
0139 /* Host Interrupt Status bit : Rx upload ready */
0140 #define IF_SPI_HIST_RX_UPLOAD_RDY           (1<<1)
0141 /* Host Interrupt Status bit : Command download ready */
0142 #define IF_SPI_HIST_CMD_DOWNLOAD_RDY            (1<<2)
0143 /* Host Interrupt Status bit : Card event */
0144 #define IF_SPI_HIST_CARD_EVENT              (1<<3)
0145 /* Host Interrupt Status bit : Command upload ready */
0146 #define IF_SPI_HIST_CMD_UPLOAD_RDY          (1<<4)
0147 /* Host Interrupt Status bit : I/O write FIFO overflow */
0148 #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW         (1<<5)
0149 /* Host Interrupt Status bit : I/O read FIFO underflow */
0150 #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW         (1<<6)
0151 /* Host Interrupt Status bit : Data write FIFO overflow */
0152 #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW       (1<<7)
0153 /* Host Interrupt Status bit : Data read FIFO underflow */
0154 #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW      (1<<8)
0155 /* Host Interrupt Status bit : Command write FIFO overflow */
0156 #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW        (1<<9)
0157 /* Host Interrupt Status bit : Command read FIFO underflow */
0158 #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW       (1<<10)
0159
0160 /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/
0161 /* Host Interrupt Status Mask bit : Tx download ready */
0162 #define IF_SPI_HISM_TX_DOWNLOAD_RDY         (1<<0)
0163 /* Host Interrupt Status Mask bit : Rx upload ready */
0164 #define IF_SPI_HISM_RX_UPLOAD_RDY           (1<<1)
0165 /* Host Interrupt Status Mask bit : Command download ready */
0166 #define IF_SPI_HISM_CMD_DOWNLOAD_RDY            (1<<2)
0167 /* Host Interrupt Status Mask bit : Card event */
0168 #define IF_SPI_HISM_CARDEVENT               (1<<3)
0169 /* Host Interrupt Status Mask bit : Command upload ready */
0170 #define IF_SPI_HISM_CMD_UPLOAD_RDY          (1<<4)
0171 /* Host Interrupt Status Mask bit : I/O write FIFO overflow */
0172 #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW         (1<<5)
0173 /* Host Interrupt Status Mask bit : I/O read FIFO underflow */
0174 #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW        (1<<6)
0175 /* Host Interrupt Status Mask bit : Data write FIFO overflow */
0176 #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW       (1<<7)
0177 /* Host Interrupt Status Mask bit : Data write FIFO underflow */
0178 #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW      (1<<8)
0179 /* Host Interrupt Status Mask bit : Command write FIFO overflow */
0180 #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW        (1<<9)
0181 /* Host Interrupt Status Mask bit : Command write FIFO underflow */
0182 #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW       (1<<10)
0183
0184 /***************** IF_SPI_SPU_BUS_MODE_REG *****************/
0185 /* SCK edge on which the WLAN module outputs data on MISO */
0186 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8
0187 #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0
0188
0189 /* In a SPU read operation, there is a delay between writing the SPU
0190  * register name and getting back data from the WLAN module.
0191  * This can be specified in terms of nanoseconds or in terms of dummy
0192  * clock cycles which the master must output before receiving a response. */
0193 #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4
0194 #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0
0195
0196 /* Some different modes of SPI operation */
0197 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00
0198 #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01
0199 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02
0200 #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03
0201
0202 #endif