intersil/p54/p54spi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
0004  *
0005  * This driver is a port from stlc45xx:
0006  *  Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
0007  */
0008
0009 #ifndef P54SPI_H
0010 #define P54SPI_H
0011
0012 #include <linux/mutex.h>
0013 #include <linux/list.h>
0014 #include <net/mac80211.h>
0015
0016 #include "p54.h"
0017
0018 /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */
0019 #define SPI_ADRS_READ_BIT_15        0x8000
0020
0021 #define SPI_ADRS_ARM_INTERRUPTS     0x00
0022 #define SPI_ADRS_ARM_INT_EN     0x04
0023
0024 #define SPI_ADRS_HOST_INTERRUPTS    0x08
0025 #define SPI_ADRS_HOST_INT_EN        0x0c
0026 #define SPI_ADRS_HOST_INT_ACK       0x10
0027
0028 #define SPI_ADRS_GEN_PURP_1     0x14
0029 #define SPI_ADRS_GEN_PURP_2     0x18
0030
0031 #define SPI_ADRS_DEV_CTRL_STAT      0x26    /* high word */
0032
0033 #define SPI_ADRS_DMA_DATA       0x28
0034
0035 #define SPI_ADRS_DMA_WRITE_CTRL     0x2c
0036 #define SPI_ADRS_DMA_WRITE_LEN      0x2e
0037 #define SPI_ADRS_DMA_WRITE_BASE     0x30
0038
0039 #define SPI_ADRS_DMA_READ_CTRL      0x34
0040 #define SPI_ADRS_DMA_READ_LEN       0x36
0041 #define SPI_ADRS_DMA_READ_BASE      0x38
0042
0043 #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000
0044 #define SPI_CTRL_STAT_START_HALTED  0x4000
0045 #define SPI_CTRL_STAT_RAM_BOOT      0x2000
0046 #define SPI_CTRL_STAT_HOST_RESET    0x1000
0047 #define SPI_CTRL_STAT_HOST_CPU_EN   0x0800
0048
0049 #define SPI_DMA_WRITE_CTRL_ENABLE   0x0001
0050 #define SPI_DMA_READ_CTRL_ENABLE    0x0001
0051 #define HOST_ALLOWED            (1 << 7)
0052
0053 #define SPI_TIMEOUT         100         /* msec */
0054
0055 #define SPI_MAX_TX_PACKETS      32
0056
0057 #define SPI_MAX_PACKET_SIZE     32767
0058
0059 #define SPI_TARGET_INT_WAKEUP       0x00000001
0060 #define SPI_TARGET_INT_SLEEP        0x00000002
0061 #define SPI_TARGET_INT_RDDONE       0x00000004
0062
0063 #define SPI_TARGET_INT_CTS      0x00004000
0064 #define SPI_TARGET_INT_DR       0x00008000
0065
0066 #define SPI_HOST_INT_READY      0x00000001
0067 #define SPI_HOST_INT_WR_READY       0x00000002
0068 #define SPI_HOST_INT_SW_UPDATE      0x00000004
0069 #define SPI_HOST_INT_UPDATE     0x10000000
0070
0071 /* clear to send */
0072 #define SPI_HOST_INT_CR         0x00004000
0073
0074 /* data ready */
0075 #define SPI_HOST_INT_DR         0x00008000
0076
0077 #define SPI_HOST_INTS_DEFAULT                           \
0078     (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE)
0079
0080 #define TARGET_BOOT_SLEEP 50
0081
0082 struct p54s_dma_regs {
0083     __le16 cmd;
0084     __le16 len;
0085     __le32 addr;
0086 } __packed;
0087
0088 struct p54s_tx_info {
0089     struct list_head tx_list;
0090 };
0091
0092 struct p54s_priv {
0093     /* p54_common has to be the first entry */
0094     struct p54_common common;
0095     struct ieee80211_hw *hw;
0096     struct spi_device *spi;
0097
0098     struct work_struct work;
0099
0100     struct mutex mutex;
0101     struct completion fw_comp;
0102
0103     spinlock_t tx_lock;
0104
0105     /* protected by tx_lock */
0106     struct list_head tx_pending;
0107
0108     enum fw_state fw_state;
0109     const struct firmware *firmware;
0110 };
0111
0112 #endif /* P54SPI_H */