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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
0004  * Copyright 2008       Johannes Berg <johannes@sipsolutions.net>
0005  *
0006  * This driver is a port from stlc45xx:
0007  *  Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/firmware.h>
0014 #include <linux/delay.h>
0015 #include <linux/irq.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/etherdevice.h>
0018 #include <linux/gpio.h>
0019 #include <linux/slab.h>
0020 
0021 #include "p54spi.h"
0022 #include "p54.h"
0023 
0024 #include "lmac.h"
0025 
0026 #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
0027 #include "p54spi_eeprom.h"
0028 #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
0029 
0030 MODULE_FIRMWARE("3826.arm");
0031 
0032 /* gpios should be handled in board files and provided via platform data,
0033  * but because it's currently impossible for p54spi to have a header file
0034  * in include/linux, let's use module paramaters for now
0035  */
0036 
0037 static int p54spi_gpio_power = 97;
0038 module_param(p54spi_gpio_power, int, 0444);
0039 MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
0040 
0041 static int p54spi_gpio_irq = 87;
0042 module_param(p54spi_gpio_irq, int, 0444);
0043 MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
0044 
0045 static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
0046                   void *buf, size_t len)
0047 {
0048     struct spi_transfer t[2];
0049     struct spi_message m;
0050     __le16 addr;
0051 
0052     /* We first push the address */
0053     addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
0054 
0055     spi_message_init(&m);
0056     memset(t, 0, sizeof(t));
0057 
0058     t[0].tx_buf = &addr;
0059     t[0].len = sizeof(addr);
0060     spi_message_add_tail(&t[0], &m);
0061 
0062     t[1].rx_buf = buf;
0063     t[1].len = len;
0064     spi_message_add_tail(&t[1], &m);
0065 
0066     spi_sync(priv->spi, &m);
0067 }
0068 
0069 
0070 static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
0071                  const void *buf, size_t len)
0072 {
0073     struct spi_transfer t[3];
0074     struct spi_message m;
0075     __le16 addr;
0076 
0077     /* We first push the address */
0078     addr = cpu_to_le16(address << 8);
0079 
0080     spi_message_init(&m);
0081     memset(t, 0, sizeof(t));
0082 
0083     t[0].tx_buf = &addr;
0084     t[0].len = sizeof(addr);
0085     spi_message_add_tail(&t[0], &m);
0086 
0087     t[1].tx_buf = buf;
0088     t[1].len = len & ~1;
0089     spi_message_add_tail(&t[1], &m);
0090 
0091     if (len % 2) {
0092         __le16 last_word;
0093         last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
0094 
0095         t[2].tx_buf = &last_word;
0096         t[2].len = sizeof(last_word);
0097         spi_message_add_tail(&t[2], &m);
0098     }
0099 
0100     spi_sync(priv->spi, &m);
0101 }
0102 
0103 static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
0104 {
0105     __le32 val;
0106 
0107     p54spi_spi_read(priv, addr, &val, sizeof(val));
0108 
0109     return le32_to_cpu(val);
0110 }
0111 
0112 static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
0113 {
0114     p54spi_spi_write(priv, addr, &val, sizeof(val));
0115 }
0116 
0117 static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
0118 {
0119     p54spi_spi_write(priv, addr, &val, sizeof(val));
0120 }
0121 
0122 static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
0123 {
0124     int i;
0125 
0126     for (i = 0; i < 2000; i++) {
0127         u32 buffer = p54spi_read32(priv, reg);
0128         if ((buffer & bits) == bits)
0129             return 1;
0130     }
0131     return 0;
0132 }
0133 
0134 static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
0135                 const void *buf, size_t len)
0136 {
0137     if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
0138         dev_err(&priv->spi->dev, "spi_write_dma not allowed "
0139             "to DMA write.\n");
0140         return -EAGAIN;
0141     }
0142 
0143     p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
0144                cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
0145 
0146     p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
0147     p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
0148     p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
0149     return 0;
0150 }
0151 
0152 static int p54spi_request_firmware(struct ieee80211_hw *dev)
0153 {
0154     struct p54s_priv *priv = dev->priv;
0155     int ret;
0156 
0157     /* FIXME: should driver use it's own struct device? */
0158     ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
0159 
0160     if (ret < 0) {
0161         dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
0162         return ret;
0163     }
0164 
0165     ret = p54_parse_firmware(dev, priv->firmware);
0166     if (ret) {
0167         /* the firmware is released by the caller */
0168         return ret;
0169     }
0170 
0171     return 0;
0172 }
0173 
0174 static int p54spi_request_eeprom(struct ieee80211_hw *dev)
0175 {
0176     struct p54s_priv *priv = dev->priv;
0177     const struct firmware *eeprom;
0178     int ret;
0179 
0180     /* allow users to customize their eeprom.
0181      */
0182 
0183     ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
0184     if (ret < 0) {
0185 #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
0186         dev_info(&priv->spi->dev, "loading default eeprom...\n");
0187         ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
0188                        sizeof(p54spi_eeprom));
0189 #else
0190         dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
0191 #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
0192     } else {
0193         dev_info(&priv->spi->dev, "loading user eeprom...\n");
0194         ret = p54_parse_eeprom(dev, (void *) eeprom->data,
0195                        (int)eeprom->size);
0196         release_firmware(eeprom);
0197     }
0198     return ret;
0199 }
0200 
0201 static int p54spi_upload_firmware(struct ieee80211_hw *dev)
0202 {
0203     struct p54s_priv *priv = dev->priv;
0204     unsigned long fw_len, _fw_len;
0205     unsigned int offset = 0;
0206     int err = 0;
0207     u8 *fw;
0208 
0209     fw_len = priv->firmware->size;
0210     fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
0211     if (!fw)
0212         return -ENOMEM;
0213 
0214     /* stop the device */
0215     p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
0216                SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
0217                SPI_CTRL_STAT_START_HALTED));
0218 
0219     msleep(TARGET_BOOT_SLEEP);
0220 
0221     p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
0222                SPI_CTRL_STAT_HOST_OVERRIDE |
0223                SPI_CTRL_STAT_START_HALTED));
0224 
0225     msleep(TARGET_BOOT_SLEEP);
0226 
0227     while (fw_len > 0) {
0228         _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
0229 
0230         err = p54spi_spi_write_dma(priv, cpu_to_le32(
0231                        ISL38XX_DEV_FIRMWARE_ADDR + offset),
0232                        (fw + offset), _fw_len);
0233         if (err < 0)
0234             goto out;
0235 
0236         fw_len -= _fw_len;
0237         offset += _fw_len;
0238     }
0239 
0240     BUG_ON(fw_len != 0);
0241 
0242     /* enable host interrupts */
0243     p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
0244                cpu_to_le32(SPI_HOST_INTS_DEFAULT));
0245 
0246     /* boot the device */
0247     p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
0248                SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
0249                SPI_CTRL_STAT_RAM_BOOT));
0250 
0251     msleep(TARGET_BOOT_SLEEP);
0252 
0253     p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
0254                SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
0255     msleep(TARGET_BOOT_SLEEP);
0256 
0257 out:
0258     kfree(fw);
0259     return err;
0260 }
0261 
0262 static void p54spi_power_off(struct p54s_priv *priv)
0263 {
0264     disable_irq(gpio_to_irq(p54spi_gpio_irq));
0265     gpio_set_value(p54spi_gpio_power, 0);
0266 }
0267 
0268 static void p54spi_power_on(struct p54s_priv *priv)
0269 {
0270     gpio_set_value(p54spi_gpio_power, 1);
0271     enable_irq(gpio_to_irq(p54spi_gpio_irq));
0272 
0273     /* need to wait a while before device can be accessed, the length
0274      * is just a guess
0275      */
0276     msleep(10);
0277 }
0278 
0279 static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
0280 {
0281     p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
0282 }
0283 
0284 static int p54spi_wakeup(struct p54s_priv *priv)
0285 {
0286     /* wake the chip */
0287     p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
0288                cpu_to_le32(SPI_TARGET_INT_WAKEUP));
0289 
0290     /* And wait for the READY interrupt */
0291     if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
0292                  SPI_HOST_INT_READY)) {
0293         dev_err(&priv->spi->dev, "INT_READY timeout\n");
0294         return -EBUSY;
0295     }
0296 
0297     p54spi_int_ack(priv, SPI_HOST_INT_READY);
0298     return 0;
0299 }
0300 
0301 static inline void p54spi_sleep(struct p54s_priv *priv)
0302 {
0303     p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
0304                cpu_to_le32(SPI_TARGET_INT_SLEEP));
0305 }
0306 
0307 static void p54spi_int_ready(struct p54s_priv *priv)
0308 {
0309     p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
0310                SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
0311 
0312     switch (priv->fw_state) {
0313     case FW_STATE_BOOTING:
0314         priv->fw_state = FW_STATE_READY;
0315         complete(&priv->fw_comp);
0316         break;
0317     case FW_STATE_RESETTING:
0318         priv->fw_state = FW_STATE_READY;
0319         /* TODO: reinitialize state */
0320         break;
0321     default:
0322         break;
0323     }
0324 }
0325 
0326 static int p54spi_rx(struct p54s_priv *priv)
0327 {
0328     struct sk_buff *skb;
0329     u16 len;
0330     u16 rx_head[2];
0331 #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
0332 
0333     if (p54spi_wakeup(priv) < 0)
0334         return -EBUSY;
0335 
0336     /* Read data size and first data word in one SPI transaction
0337      * This is workaround for firmware/DMA bug,
0338      * when first data word gets lost under high load.
0339      */
0340     p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
0341     len = rx_head[0];
0342 
0343     if (len == 0) {
0344         p54spi_sleep(priv);
0345         dev_err(&priv->spi->dev, "rx request of zero bytes\n");
0346         return 0;
0347     }
0348 
0349     /* Firmware may insert up to 4 padding bytes after the lmac header,
0350      * but it does not amend the size of SPI data transfer.
0351      * Such packets has correct data size in header, thus referencing
0352      * past the end of allocated skb. Reserve extra 4 bytes for this case
0353      */
0354     skb = dev_alloc_skb(len + 4);
0355     if (!skb) {
0356         p54spi_sleep(priv);
0357         dev_err(&priv->spi->dev, "could not alloc skb");
0358         return -ENOMEM;
0359     }
0360 
0361     if (len <= READAHEAD_SZ) {
0362         skb_put_data(skb, rx_head + 1, len);
0363     } else {
0364         skb_put_data(skb, rx_head + 1, READAHEAD_SZ);
0365         p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
0366                 skb_put(skb, len - READAHEAD_SZ),
0367                 len - READAHEAD_SZ);
0368     }
0369     p54spi_sleep(priv);
0370     /* Put additional bytes to compensate for the possible
0371      * alignment-caused truncation
0372      */
0373     skb_put(skb, 4);
0374 
0375     if (p54_rx(priv->hw, skb) == 0)
0376         dev_kfree_skb(skb);
0377 
0378     return 0;
0379 }
0380 
0381 
0382 static irqreturn_t p54spi_interrupt(int irq, void *config)
0383 {
0384     struct spi_device *spi = config;
0385     struct p54s_priv *priv = spi_get_drvdata(spi);
0386 
0387     ieee80211_queue_work(priv->hw, &priv->work);
0388 
0389     return IRQ_HANDLED;
0390 }
0391 
0392 static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
0393 {
0394     struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
0395     int ret = 0;
0396 
0397     if (p54spi_wakeup(priv) < 0)
0398         return -EBUSY;
0399 
0400     ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
0401     if (ret < 0)
0402         goto out;
0403 
0404     if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
0405                  SPI_HOST_INT_WR_READY)) {
0406         dev_err(&priv->spi->dev, "WR_READY timeout\n");
0407         ret = -EAGAIN;
0408         goto out;
0409     }
0410 
0411     p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
0412 
0413     if (FREE_AFTER_TX(skb))
0414         p54_free_skb(priv->hw, skb);
0415 out:
0416     p54spi_sleep(priv);
0417     return ret;
0418 }
0419 
0420 static int p54spi_wq_tx(struct p54s_priv *priv)
0421 {
0422     struct p54s_tx_info *entry;
0423     struct sk_buff *skb;
0424     struct ieee80211_tx_info *info;
0425     struct p54_tx_info *minfo;
0426     struct p54s_tx_info *dinfo;
0427     unsigned long flags;
0428     int ret = 0;
0429 
0430     spin_lock_irqsave(&priv->tx_lock, flags);
0431 
0432     while (!list_empty(&priv->tx_pending)) {
0433         entry = list_entry(priv->tx_pending.next,
0434                    struct p54s_tx_info, tx_list);
0435 
0436         list_del_init(&entry->tx_list);
0437 
0438         spin_unlock_irqrestore(&priv->tx_lock, flags);
0439 
0440         dinfo = container_of((void *) entry, struct p54s_tx_info,
0441                      tx_list);
0442         minfo = container_of((void *) dinfo, struct p54_tx_info,
0443                      data);
0444         info = container_of((void *) minfo, struct ieee80211_tx_info,
0445                     rate_driver_data);
0446         skb = container_of((void *) info, struct sk_buff, cb);
0447 
0448         ret = p54spi_tx_frame(priv, skb);
0449 
0450         if (ret < 0) {
0451             p54_free_skb(priv->hw, skb);
0452             return ret;
0453         }
0454 
0455         spin_lock_irqsave(&priv->tx_lock, flags);
0456     }
0457     spin_unlock_irqrestore(&priv->tx_lock, flags);
0458     return ret;
0459 }
0460 
0461 static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
0462 {
0463     struct p54s_priv *priv = dev->priv;
0464     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0465     struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
0466     struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
0467     unsigned long flags;
0468 
0469     BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
0470 
0471     spin_lock_irqsave(&priv->tx_lock, flags);
0472     list_add_tail(&di->tx_list, &priv->tx_pending);
0473     spin_unlock_irqrestore(&priv->tx_lock, flags);
0474 
0475     ieee80211_queue_work(priv->hw, &priv->work);
0476 }
0477 
0478 static void p54spi_work(struct work_struct *work)
0479 {
0480     struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
0481     u32 ints;
0482     int ret;
0483 
0484     mutex_lock(&priv->mutex);
0485 
0486     if (priv->fw_state == FW_STATE_OFF)
0487         goto out;
0488 
0489     ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
0490 
0491     if (ints & SPI_HOST_INT_READY) {
0492         p54spi_int_ready(priv);
0493         p54spi_int_ack(priv, SPI_HOST_INT_READY);
0494     }
0495 
0496     if (priv->fw_state != FW_STATE_READY)
0497         goto out;
0498 
0499     if (ints & SPI_HOST_INT_UPDATE) {
0500         p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
0501         ret = p54spi_rx(priv);
0502         if (ret < 0)
0503             goto out;
0504     }
0505     if (ints & SPI_HOST_INT_SW_UPDATE) {
0506         p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
0507         ret = p54spi_rx(priv);
0508         if (ret < 0)
0509             goto out;
0510     }
0511 
0512     ret = p54spi_wq_tx(priv);
0513 out:
0514     mutex_unlock(&priv->mutex);
0515 }
0516 
0517 static int p54spi_op_start(struct ieee80211_hw *dev)
0518 {
0519     struct p54s_priv *priv = dev->priv;
0520     unsigned long timeout;
0521     int ret = 0;
0522 
0523     if (mutex_lock_interruptible(&priv->mutex)) {
0524         ret = -EINTR;
0525         goto out;
0526     }
0527 
0528     priv->fw_state = FW_STATE_BOOTING;
0529 
0530     p54spi_power_on(priv);
0531 
0532     ret = p54spi_upload_firmware(dev);
0533     if (ret < 0) {
0534         p54spi_power_off(priv);
0535         goto out_unlock;
0536     }
0537 
0538     mutex_unlock(&priv->mutex);
0539 
0540     timeout = msecs_to_jiffies(2000);
0541     timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
0542                                 timeout);
0543     if (!timeout) {
0544         dev_err(&priv->spi->dev, "firmware boot failed");
0545         p54spi_power_off(priv);
0546         ret = -1;
0547         goto out;
0548     }
0549 
0550     if (mutex_lock_interruptible(&priv->mutex)) {
0551         ret = -EINTR;
0552         p54spi_power_off(priv);
0553         goto out;
0554     }
0555 
0556     WARN_ON(priv->fw_state != FW_STATE_READY);
0557 
0558 out_unlock:
0559     mutex_unlock(&priv->mutex);
0560 
0561 out:
0562     return ret;
0563 }
0564 
0565 static void p54spi_op_stop(struct ieee80211_hw *dev)
0566 {
0567     struct p54s_priv *priv = dev->priv;
0568     unsigned long flags;
0569 
0570     mutex_lock(&priv->mutex);
0571     WARN_ON(priv->fw_state != FW_STATE_READY);
0572 
0573     p54spi_power_off(priv);
0574     spin_lock_irqsave(&priv->tx_lock, flags);
0575     INIT_LIST_HEAD(&priv->tx_pending);
0576     spin_unlock_irqrestore(&priv->tx_lock, flags);
0577 
0578     priv->fw_state = FW_STATE_OFF;
0579     mutex_unlock(&priv->mutex);
0580 
0581     cancel_work_sync(&priv->work);
0582 }
0583 
0584 static int p54spi_probe(struct spi_device *spi)
0585 {
0586     struct p54s_priv *priv = NULL;
0587     struct ieee80211_hw *hw;
0588     int ret = -EINVAL;
0589 
0590     hw = p54_init_common(sizeof(*priv));
0591     if (!hw) {
0592         dev_err(&spi->dev, "could not alloc ieee80211_hw");
0593         return -ENOMEM;
0594     }
0595 
0596     priv = hw->priv;
0597     priv->hw = hw;
0598     spi_set_drvdata(spi, priv);
0599     priv->spi = spi;
0600 
0601     spi->bits_per_word = 16;
0602     spi->max_speed_hz = 24000000;
0603 
0604     ret = spi_setup(spi);
0605     if (ret < 0) {
0606         dev_err(&priv->spi->dev, "spi_setup failed");
0607         goto err_free;
0608     }
0609 
0610     ret = gpio_request(p54spi_gpio_power, "p54spi power");
0611     if (ret < 0) {
0612         dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
0613         goto err_free;
0614     }
0615 
0616     ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
0617     if (ret < 0) {
0618         dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
0619         goto err_free_gpio_power;
0620     }
0621 
0622     gpio_direction_output(p54spi_gpio_power, 0);
0623     gpio_direction_input(p54spi_gpio_irq);
0624 
0625     ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
0626               p54spi_interrupt, 0, "p54spi",
0627               priv->spi);
0628     if (ret < 0) {
0629         dev_err(&priv->spi->dev, "request_irq() failed");
0630         goto err_free_gpio_irq;
0631     }
0632 
0633     irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
0634 
0635     disable_irq(gpio_to_irq(p54spi_gpio_irq));
0636 
0637     INIT_WORK(&priv->work, p54spi_work);
0638     init_completion(&priv->fw_comp);
0639     INIT_LIST_HEAD(&priv->tx_pending);
0640     mutex_init(&priv->mutex);
0641     spin_lock_init(&priv->tx_lock);
0642     SET_IEEE80211_DEV(hw, &spi->dev);
0643     priv->common.open = p54spi_op_start;
0644     priv->common.stop = p54spi_op_stop;
0645     priv->common.tx = p54spi_op_tx;
0646 
0647     ret = p54spi_request_firmware(hw);
0648     if (ret < 0)
0649         goto err_free_common;
0650 
0651     ret = p54spi_request_eeprom(hw);
0652     if (ret)
0653         goto err_free_common;
0654 
0655     ret = p54_register_common(hw, &priv->spi->dev);
0656     if (ret)
0657         goto err_free_common;
0658 
0659     return 0;
0660 
0661 err_free_common:
0662     release_firmware(priv->firmware);
0663     free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
0664 err_free_gpio_irq:
0665     gpio_free(p54spi_gpio_irq);
0666 err_free_gpio_power:
0667     gpio_free(p54spi_gpio_power);
0668 err_free:
0669     p54_free_common(priv->hw);
0670     return ret;
0671 }
0672 
0673 static void p54spi_remove(struct spi_device *spi)
0674 {
0675     struct p54s_priv *priv = spi_get_drvdata(spi);
0676 
0677     p54_unregister_common(priv->hw);
0678 
0679     free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
0680 
0681     gpio_free(p54spi_gpio_power);
0682     gpio_free(p54spi_gpio_irq);
0683     release_firmware(priv->firmware);
0684 
0685     mutex_destroy(&priv->mutex);
0686 
0687     p54_free_common(priv->hw);
0688 }
0689 
0690 
0691 static struct spi_driver p54spi_driver = {
0692     .driver = {
0693         .name       = "p54spi",
0694     },
0695 
0696     .probe      = p54spi_probe,
0697     .remove     = p54spi_remove,
0698 };
0699 
0700 module_spi_driver(p54spi_driver);
0701 
0702 MODULE_LICENSE("GPL");
0703 MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
0704 MODULE_ALIAS("spi:cx3110x");
0705 MODULE_ALIAS("spi:p54spi");
0706 MODULE_ALIAS("spi:stlc45xx");
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