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0013 #include <linux/pci.h>
0014 #include <linux/slab.h>
0015 #include <linux/firmware.h>
0016 #include <linux/etherdevice.h>
0017 #include <linux/delay.h>
0018 #include <linux/completion.h>
0019 #include <linux/module.h>
0020 #include <net/mac80211.h>
0021
0022 #include "p54.h"
0023 #include "lmac.h"
0024 #include "p54pci.h"
0025
0026 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
0027 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
0028 MODULE_LICENSE("GPL");
0029 MODULE_ALIAS("prism54pci");
0030 MODULE_FIRMWARE("isl3886pci");
0031
0032 static const struct pci_device_id p54p_table[] = {
0033
0034 { PCI_DEVICE(0x1260, 0x3890) },
0035
0036 { PCI_DEVICE(0x10b7, 0x6001) },
0037
0038 { PCI_DEVICE(0x1260, 0x3877) },
0039
0040 { PCI_DEVICE(0x1260, 0x3886) },
0041
0042 { PCI_DEVICE(0x1260, 0xffff) },
0043 { },
0044 };
0045
0046 MODULE_DEVICE_TABLE(pci, p54p_table);
0047
0048 static int p54p_upload_firmware(struct ieee80211_hw *dev)
0049 {
0050 struct p54p_priv *priv = dev->priv;
0051 __le32 reg;
0052 int err;
0053 __le32 *data;
0054 u32 remains, left, device_addr;
0055
0056 P54P_WRITE(int_enable, cpu_to_le32(0));
0057 P54P_READ(int_enable);
0058 udelay(10);
0059
0060 reg = P54P_READ(ctrl_stat);
0061 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
0062 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
0063 P54P_WRITE(ctrl_stat, reg);
0064 P54P_READ(ctrl_stat);
0065 udelay(10);
0066
0067 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
0068 P54P_WRITE(ctrl_stat, reg);
0069 wmb();
0070 udelay(10);
0071
0072 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
0073 P54P_WRITE(ctrl_stat, reg);
0074 wmb();
0075
0076
0077 mdelay(10);
0078
0079 err = p54_parse_firmware(dev, priv->firmware);
0080 if (err)
0081 return err;
0082
0083 if (priv->common.fw_interface != FW_LM86) {
0084 dev_err(&priv->pdev->dev, "wrong firmware, "
0085 "please get a LM86(PCI) firmware a try again.\n");
0086 return -EINVAL;
0087 }
0088
0089 data = (__le32 *) priv->firmware->data;
0090 remains = priv->firmware->size;
0091 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
0092 while (remains) {
0093 u32 i = 0;
0094 left = min((u32)0x1000, remains);
0095 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
0096 P54P_READ(int_enable);
0097
0098 device_addr += 0x1000;
0099 while (i < left) {
0100 P54P_WRITE(direct_mem_win[i], *data++);
0101 i += sizeof(u32);
0102 }
0103
0104 remains -= left;
0105 P54P_READ(int_enable);
0106 }
0107
0108 reg = P54P_READ(ctrl_stat);
0109 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
0110 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
0111 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
0112 P54P_WRITE(ctrl_stat, reg);
0113 P54P_READ(ctrl_stat);
0114 udelay(10);
0115
0116 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
0117 P54P_WRITE(ctrl_stat, reg);
0118 wmb();
0119 udelay(10);
0120
0121 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
0122 P54P_WRITE(ctrl_stat, reg);
0123 wmb();
0124 udelay(10);
0125
0126
0127 mdelay(100);
0128
0129 return 0;
0130 }
0131
0132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
0133 int ring_index, struct p54p_desc *ring, u32 ring_limit,
0134 struct sk_buff **rx_buf, u32 index)
0135 {
0136 struct p54p_priv *priv = dev->priv;
0137 struct p54p_ring_control *ring_control = priv->ring_control;
0138 u32 limit, idx, i;
0139
0140 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
0141 limit = idx;
0142 limit -= index;
0143 limit = ring_limit - limit;
0144
0145 i = idx % ring_limit;
0146 while (limit-- > 1) {
0147 struct p54p_desc *desc = &ring[i];
0148
0149 if (!desc->host_addr) {
0150 struct sk_buff *skb;
0151 dma_addr_t mapping;
0152 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
0153 if (!skb)
0154 break;
0155
0156 mapping = dma_map_single(&priv->pdev->dev,
0157 skb_tail_pointer(skb),
0158 priv->common.rx_mtu + 32,
0159 DMA_FROM_DEVICE);
0160
0161 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
0162 dev_kfree_skb_any(skb);
0163 dev_err(&priv->pdev->dev,
0164 "RX DMA Mapping error\n");
0165 break;
0166 }
0167
0168 desc->host_addr = cpu_to_le32(mapping);
0169 desc->device_addr = 0;
0170 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
0171 desc->flags = 0;
0172 rx_buf[i] = skb;
0173 }
0174
0175 i++;
0176 idx++;
0177 i %= ring_limit;
0178 }
0179
0180 wmb();
0181 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
0182 }
0183
0184 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
0185 int ring_index, struct p54p_desc *ring, u32 ring_limit,
0186 struct sk_buff **rx_buf)
0187 {
0188 struct p54p_priv *priv = dev->priv;
0189 struct p54p_ring_control *ring_control = priv->ring_control;
0190 struct p54p_desc *desc;
0191 u32 idx, i;
0192
0193 i = (*index) % ring_limit;
0194 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
0195 idx %= ring_limit;
0196 while (i != idx) {
0197 u16 len;
0198 struct sk_buff *skb;
0199 dma_addr_t dma_addr;
0200 desc = &ring[i];
0201 len = le16_to_cpu(desc->len);
0202 skb = rx_buf[i];
0203
0204 if (!skb) {
0205 i++;
0206 i %= ring_limit;
0207 continue;
0208 }
0209
0210 if (unlikely(len > priv->common.rx_mtu)) {
0211 if (net_ratelimit())
0212 dev_err(&priv->pdev->dev, "rx'd frame size "
0213 "exceeds length threshold.\n");
0214
0215 len = priv->common.rx_mtu;
0216 }
0217 dma_addr = le32_to_cpu(desc->host_addr);
0218 dma_sync_single_for_cpu(&priv->pdev->dev, dma_addr,
0219 priv->common.rx_mtu + 32,
0220 DMA_FROM_DEVICE);
0221 skb_put(skb, len);
0222
0223 if (p54_rx(dev, skb)) {
0224 dma_unmap_single(&priv->pdev->dev, dma_addr,
0225 priv->common.rx_mtu + 32,
0226 DMA_FROM_DEVICE);
0227 rx_buf[i] = NULL;
0228 desc->host_addr = cpu_to_le32(0);
0229 } else {
0230 skb_trim(skb, 0);
0231 dma_sync_single_for_device(&priv->pdev->dev, dma_addr,
0232 priv->common.rx_mtu + 32,
0233 DMA_FROM_DEVICE);
0234 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
0235 }
0236
0237 i++;
0238 i %= ring_limit;
0239 }
0240
0241 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
0242 }
0243
0244 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
0245 int ring_index, struct p54p_desc *ring, u32 ring_limit,
0246 struct sk_buff **tx_buf)
0247 {
0248 struct p54p_priv *priv = dev->priv;
0249 struct p54p_ring_control *ring_control = priv->ring_control;
0250 struct p54p_desc *desc;
0251 struct sk_buff *skb;
0252 u32 idx, i;
0253
0254 i = (*index) % ring_limit;
0255 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
0256 idx %= ring_limit;
0257
0258 while (i != idx) {
0259 desc = &ring[i];
0260
0261 skb = tx_buf[i];
0262 tx_buf[i] = NULL;
0263
0264 dma_unmap_single(&priv->pdev->dev,
0265 le32_to_cpu(desc->host_addr),
0266 le16_to_cpu(desc->len), DMA_TO_DEVICE);
0267
0268 desc->host_addr = 0;
0269 desc->device_addr = 0;
0270 desc->len = 0;
0271 desc->flags = 0;
0272
0273 if (skb && FREE_AFTER_TX(skb))
0274 p54_free_skb(dev, skb);
0275
0276 i++;
0277 i %= ring_limit;
0278 }
0279 }
0280
0281 static void p54p_tasklet(struct tasklet_struct *t)
0282 {
0283 struct p54p_priv *priv = from_tasklet(priv, t, tasklet);
0284 struct ieee80211_hw *dev = pci_get_drvdata(priv->pdev);
0285 struct p54p_ring_control *ring_control = priv->ring_control;
0286
0287 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
0288 ARRAY_SIZE(ring_control->tx_mgmt),
0289 priv->tx_buf_mgmt);
0290
0291 p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
0292 ARRAY_SIZE(ring_control->tx_data),
0293 priv->tx_buf_data);
0294
0295 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
0296 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
0297
0298 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
0299 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
0300
0301 wmb();
0302 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
0303 }
0304
0305 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
0306 {
0307 struct ieee80211_hw *dev = dev_id;
0308 struct p54p_priv *priv = dev->priv;
0309 __le32 reg;
0310
0311 reg = P54P_READ(int_ident);
0312 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
0313 goto out;
0314 }
0315 P54P_WRITE(int_ack, reg);
0316
0317 reg &= P54P_READ(int_enable);
0318
0319 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
0320 tasklet_schedule(&priv->tasklet);
0321 else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
0322 complete(&priv->boot_comp);
0323
0324 out:
0325 return reg ? IRQ_HANDLED : IRQ_NONE;
0326 }
0327
0328 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
0329 {
0330 unsigned long flags;
0331 struct p54p_priv *priv = dev->priv;
0332 struct p54p_ring_control *ring_control = priv->ring_control;
0333 struct p54p_desc *desc;
0334 dma_addr_t mapping;
0335 u32 idx, i;
0336 __le32 device_addr;
0337
0338 spin_lock_irqsave(&priv->lock, flags);
0339 idx = le32_to_cpu(ring_control->host_idx[1]);
0340 i = idx % ARRAY_SIZE(ring_control->tx_data);
0341 device_addr = ((struct p54_hdr *)skb->data)->req_id;
0342
0343 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
0344 DMA_TO_DEVICE);
0345 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
0346 spin_unlock_irqrestore(&priv->lock, flags);
0347 p54_free_skb(dev, skb);
0348 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
0349 return ;
0350 }
0351 priv->tx_buf_data[i] = skb;
0352
0353 desc = &ring_control->tx_data[i];
0354 desc->host_addr = cpu_to_le32(mapping);
0355 desc->device_addr = device_addr;
0356 desc->len = cpu_to_le16(skb->len);
0357 desc->flags = 0;
0358
0359 wmb();
0360 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
0361 spin_unlock_irqrestore(&priv->lock, flags);
0362
0363 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
0364 P54P_READ(dev_int);
0365 }
0366
0367 static void p54p_stop(struct ieee80211_hw *dev)
0368 {
0369 struct p54p_priv *priv = dev->priv;
0370 struct p54p_ring_control *ring_control = priv->ring_control;
0371 unsigned int i;
0372 struct p54p_desc *desc;
0373
0374 P54P_WRITE(int_enable, cpu_to_le32(0));
0375 P54P_READ(int_enable);
0376 udelay(10);
0377
0378 free_irq(priv->pdev->irq, dev);
0379
0380 tasklet_kill(&priv->tasklet);
0381
0382 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
0383
0384 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
0385 desc = &ring_control->rx_data[i];
0386 if (desc->host_addr)
0387 dma_unmap_single(&priv->pdev->dev,
0388 le32_to_cpu(desc->host_addr),
0389 priv->common.rx_mtu + 32,
0390 DMA_FROM_DEVICE);
0391 kfree_skb(priv->rx_buf_data[i]);
0392 priv->rx_buf_data[i] = NULL;
0393 }
0394
0395 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
0396 desc = &ring_control->rx_mgmt[i];
0397 if (desc->host_addr)
0398 dma_unmap_single(&priv->pdev->dev,
0399 le32_to_cpu(desc->host_addr),
0400 priv->common.rx_mtu + 32,
0401 DMA_FROM_DEVICE);
0402 kfree_skb(priv->rx_buf_mgmt[i]);
0403 priv->rx_buf_mgmt[i] = NULL;
0404 }
0405
0406 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
0407 desc = &ring_control->tx_data[i];
0408 if (desc->host_addr)
0409 dma_unmap_single(&priv->pdev->dev,
0410 le32_to_cpu(desc->host_addr),
0411 le16_to_cpu(desc->len),
0412 DMA_TO_DEVICE);
0413
0414 p54_free_skb(dev, priv->tx_buf_data[i]);
0415 priv->tx_buf_data[i] = NULL;
0416 }
0417
0418 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
0419 desc = &ring_control->tx_mgmt[i];
0420 if (desc->host_addr)
0421 dma_unmap_single(&priv->pdev->dev,
0422 le32_to_cpu(desc->host_addr),
0423 le16_to_cpu(desc->len),
0424 DMA_TO_DEVICE);
0425
0426 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
0427 priv->tx_buf_mgmt[i] = NULL;
0428 }
0429
0430 memset(ring_control, 0, sizeof(*ring_control));
0431 }
0432
0433 static int p54p_open(struct ieee80211_hw *dev)
0434 {
0435 struct p54p_priv *priv = dev->priv;
0436 int err;
0437 long timeout;
0438
0439 init_completion(&priv->boot_comp);
0440 err = request_irq(priv->pdev->irq, p54p_interrupt,
0441 IRQF_SHARED, "p54pci", dev);
0442 if (err) {
0443 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
0444 return err;
0445 }
0446
0447 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
0448 err = p54p_upload_firmware(dev);
0449 if (err) {
0450 free_irq(priv->pdev->irq, dev);
0451 return err;
0452 }
0453 priv->rx_idx_data = priv->tx_idx_data = 0;
0454 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
0455
0456 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
0457 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
0458
0459 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
0460 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
0461
0462 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
0463 P54P_READ(ring_control_base);
0464 wmb();
0465 udelay(10);
0466
0467 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
0468 P54P_READ(int_enable);
0469 wmb();
0470 udelay(10);
0471
0472 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
0473 P54P_READ(dev_int);
0474
0475 timeout = wait_for_completion_interruptible_timeout(
0476 &priv->boot_comp, HZ);
0477 if (timeout <= 0) {
0478 wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
0479 p54p_stop(dev);
0480 return timeout ? -ERESTARTSYS : -ETIMEDOUT;
0481 }
0482
0483 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
0484 P54P_READ(int_enable);
0485 wmb();
0486 udelay(10);
0487
0488 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
0489 P54P_READ(dev_int);
0490 wmb();
0491 udelay(10);
0492
0493 return 0;
0494 }
0495
0496 static void p54p_firmware_step2(const struct firmware *fw,
0497 void *context)
0498 {
0499 struct p54p_priv *priv = context;
0500 struct ieee80211_hw *dev = priv->common.hw;
0501 struct pci_dev *pdev = priv->pdev;
0502 int err;
0503
0504 if (!fw) {
0505 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
0506 err = -ENOENT;
0507 goto out;
0508 }
0509
0510 priv->firmware = fw;
0511
0512 err = p54p_open(dev);
0513 if (err)
0514 goto out;
0515 err = p54_read_eeprom(dev);
0516 p54p_stop(dev);
0517 if (err)
0518 goto out;
0519
0520 err = p54_register_common(dev, &pdev->dev);
0521 if (err)
0522 goto out;
0523
0524 out:
0525
0526 complete(&priv->fw_loaded);
0527
0528 if (err) {
0529 struct device *parent = pdev->dev.parent;
0530
0531 if (parent)
0532 device_lock(parent);
0533
0534
0535
0536
0537
0538
0539 device_release_driver(&pdev->dev);
0540
0541 if (parent)
0542 device_unlock(parent);
0543 }
0544
0545 pci_dev_put(pdev);
0546 }
0547
0548 static int p54p_probe(struct pci_dev *pdev,
0549 const struct pci_device_id *id)
0550 {
0551 struct p54p_priv *priv;
0552 struct ieee80211_hw *dev;
0553 unsigned long mem_addr, mem_len;
0554 int err;
0555
0556 pci_dev_get(pdev);
0557 err = pci_enable_device(pdev);
0558 if (err) {
0559 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
0560 goto err_put;
0561 }
0562
0563 mem_addr = pci_resource_start(pdev, 0);
0564 mem_len = pci_resource_len(pdev, 0);
0565 if (mem_len < sizeof(struct p54p_csr)) {
0566 dev_err(&pdev->dev, "Too short PCI resources\n");
0567 err = -ENODEV;
0568 goto err_disable_dev;
0569 }
0570
0571 err = pci_request_regions(pdev, "p54pci");
0572 if (err) {
0573 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
0574 goto err_disable_dev;
0575 }
0576
0577 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
0578 if (!err)
0579 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0580 if (err) {
0581 dev_err(&pdev->dev, "No suitable DMA available\n");
0582 goto err_free_reg;
0583 }
0584
0585 pci_set_master(pdev);
0586 pci_try_set_mwi(pdev);
0587
0588 pci_write_config_byte(pdev, 0x40, 0);
0589 pci_write_config_byte(pdev, 0x41, 0);
0590
0591 dev = p54_init_common(sizeof(*priv));
0592 if (!dev) {
0593 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
0594 err = -ENOMEM;
0595 goto err_free_reg;
0596 }
0597
0598 priv = dev->priv;
0599 priv->pdev = pdev;
0600
0601 init_completion(&priv->fw_loaded);
0602 SET_IEEE80211_DEV(dev, &pdev->dev);
0603 pci_set_drvdata(pdev, dev);
0604
0605 priv->map = ioremap(mem_addr, mem_len);
0606 if (!priv->map) {
0607 dev_err(&pdev->dev, "Cannot map device memory\n");
0608 err = -ENOMEM;
0609 goto err_free_dev;
0610 }
0611
0612 priv->ring_control = dma_alloc_coherent(&pdev->dev,
0613 sizeof(*priv->ring_control),
0614 &priv->ring_control_dma, GFP_KERNEL);
0615 if (!priv->ring_control) {
0616 dev_err(&pdev->dev, "Cannot allocate rings\n");
0617 err = -ENOMEM;
0618 goto err_iounmap;
0619 }
0620 priv->common.open = p54p_open;
0621 priv->common.stop = p54p_stop;
0622 priv->common.tx = p54p_tx;
0623
0624 spin_lock_init(&priv->lock);
0625 tasklet_setup(&priv->tasklet, p54p_tasklet);
0626
0627 err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
0628 &priv->pdev->dev, GFP_KERNEL,
0629 priv, p54p_firmware_step2);
0630 if (!err)
0631 return 0;
0632
0633 dma_free_coherent(&pdev->dev, sizeof(*priv->ring_control),
0634 priv->ring_control, priv->ring_control_dma);
0635
0636 err_iounmap:
0637 iounmap(priv->map);
0638
0639 err_free_dev:
0640 p54_free_common(dev);
0641
0642 err_free_reg:
0643 pci_release_regions(pdev);
0644 err_disable_dev:
0645 pci_disable_device(pdev);
0646 err_put:
0647 pci_dev_put(pdev);
0648 return err;
0649 }
0650
0651 static void p54p_remove(struct pci_dev *pdev)
0652 {
0653 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
0654 struct p54p_priv *priv;
0655
0656 if (!dev)
0657 return;
0658
0659 priv = dev->priv;
0660 wait_for_completion(&priv->fw_loaded);
0661 p54_unregister_common(dev);
0662 release_firmware(priv->firmware);
0663 dma_free_coherent(&pdev->dev, sizeof(*priv->ring_control),
0664 priv->ring_control, priv->ring_control_dma);
0665 iounmap(priv->map);
0666 pci_release_regions(pdev);
0667 pci_disable_device(pdev);
0668 p54_free_common(dev);
0669 }
0670
0671 #ifdef CONFIG_PM_SLEEP
0672 static int p54p_suspend(struct device *device)
0673 {
0674 struct pci_dev *pdev = to_pci_dev(device);
0675
0676 pci_save_state(pdev);
0677 pci_set_power_state(pdev, PCI_D3hot);
0678 pci_disable_device(pdev);
0679 return 0;
0680 }
0681
0682 static int p54p_resume(struct device *device)
0683 {
0684 struct pci_dev *pdev = to_pci_dev(device);
0685 int err;
0686
0687 err = pci_reenable_device(pdev);
0688 if (err)
0689 return err;
0690 return pci_set_power_state(pdev, PCI_D0);
0691 }
0692
0693 static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
0694
0695 #define P54P_PM_OPS (&p54pci_pm_ops)
0696 #else
0697 #define P54P_PM_OPS (NULL)
0698 #endif
0699
0700 static struct pci_driver p54p_driver = {
0701 .name = "p54pci",
0702 .id_table = p54p_table,
0703 .probe = p54p_probe,
0704 .remove = p54p_remove,
0705 .driver.pm = P54P_PM_OPS,
0706 };
0707
0708 module_pci_driver(p54p_driver);
