Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 /*
0003  * Copyright (C) 2003-2014, 2018-2021 Intel Corporation
0004  * Copyright (C) 2015-2016 Intel Deutschland GmbH
0005  */
0006 #include <linux/delay.h>
0007 #include <linux/device.h>
0008 #include <linux/export.h>
0009 
0010 #include "iwl-drv.h"
0011 #include "iwl-io.h"
0012 #include "iwl-csr.h"
0013 #include "iwl-debug.h"
0014 #include "iwl-prph.h"
0015 #include "iwl-fh.h"
0016 
0017 void iwl_write8(struct iwl_trans *trans, u32 ofs, u8 val)
0018 {
0019     trace_iwlwifi_dev_iowrite8(trans->dev, ofs, val);
0020     iwl_trans_write8(trans, ofs, val);
0021 }
0022 IWL_EXPORT_SYMBOL(iwl_write8);
0023 
0024 void iwl_write32(struct iwl_trans *trans, u32 ofs, u32 val)
0025 {
0026     trace_iwlwifi_dev_iowrite32(trans->dev, ofs, val);
0027     iwl_trans_write32(trans, ofs, val);
0028 }
0029 IWL_EXPORT_SYMBOL(iwl_write32);
0030 
0031 void iwl_write64(struct iwl_trans *trans, u64 ofs, u64 val)
0032 {
0033     trace_iwlwifi_dev_iowrite64(trans->dev, ofs, val);
0034     iwl_trans_write32(trans, ofs, lower_32_bits(val));
0035     iwl_trans_write32(trans, ofs + 4, upper_32_bits(val));
0036 }
0037 IWL_EXPORT_SYMBOL(iwl_write64);
0038 
0039 u32 iwl_read32(struct iwl_trans *trans, u32 ofs)
0040 {
0041     u32 val = iwl_trans_read32(trans, ofs);
0042 
0043     trace_iwlwifi_dev_ioread32(trans->dev, ofs, val);
0044     return val;
0045 }
0046 IWL_EXPORT_SYMBOL(iwl_read32);
0047 
0048 #define IWL_POLL_INTERVAL 10    /* microseconds */
0049 
0050 int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
0051          u32 bits, u32 mask, int timeout)
0052 {
0053     int t = 0;
0054 
0055     do {
0056         if ((iwl_read32(trans, addr) & mask) == (bits & mask))
0057             return t;
0058         udelay(IWL_POLL_INTERVAL);
0059         t += IWL_POLL_INTERVAL;
0060     } while (t < timeout);
0061 
0062     return -ETIMEDOUT;
0063 }
0064 IWL_EXPORT_SYMBOL(iwl_poll_bit);
0065 
0066 u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
0067 {
0068     if (iwl_trans_grab_nic_access(trans)) {
0069         u32 value = iwl_read32(trans, reg);
0070 
0071         iwl_trans_release_nic_access(trans);
0072         return value;
0073     }
0074 
0075     return 0x5a5a5a5a;
0076 }
0077 IWL_EXPORT_SYMBOL(iwl_read_direct32);
0078 
0079 void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
0080 {
0081     if (iwl_trans_grab_nic_access(trans)) {
0082         iwl_write32(trans, reg, value);
0083         iwl_trans_release_nic_access(trans);
0084     }
0085 }
0086 IWL_EXPORT_SYMBOL(iwl_write_direct32);
0087 
0088 void iwl_write_direct64(struct iwl_trans *trans, u64 reg, u64 value)
0089 {
0090     if (iwl_trans_grab_nic_access(trans)) {
0091         iwl_write64(trans, reg, value);
0092         iwl_trans_release_nic_access(trans);
0093     }
0094 }
0095 IWL_EXPORT_SYMBOL(iwl_write_direct64);
0096 
0097 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
0098             int timeout)
0099 {
0100     int t = 0;
0101 
0102     do {
0103         if ((iwl_read_direct32(trans, addr) & mask) == mask)
0104             return t;
0105         udelay(IWL_POLL_INTERVAL);
0106         t += IWL_POLL_INTERVAL;
0107     } while (t < timeout);
0108 
0109     return -ETIMEDOUT;
0110 }
0111 IWL_EXPORT_SYMBOL(iwl_poll_direct_bit);
0112 
0113 u32 iwl_read_prph_no_grab(struct iwl_trans *trans, u32 ofs)
0114 {
0115     u32 val = iwl_trans_read_prph(trans, ofs);
0116     trace_iwlwifi_dev_ioread_prph32(trans->dev, ofs, val);
0117     return val;
0118 }
0119 IWL_EXPORT_SYMBOL(iwl_read_prph_no_grab);
0120 
0121 void iwl_write_prph_no_grab(struct iwl_trans *trans, u32 ofs, u32 val)
0122 {
0123     trace_iwlwifi_dev_iowrite_prph32(trans->dev, ofs, val);
0124     iwl_trans_write_prph(trans, ofs, val);
0125 }
0126 IWL_EXPORT_SYMBOL(iwl_write_prph_no_grab);
0127 
0128 void iwl_write_prph64_no_grab(struct iwl_trans *trans, u64 ofs, u64 val)
0129 {
0130     trace_iwlwifi_dev_iowrite_prph64(trans->dev, ofs, val);
0131     iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
0132     iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
0133 }
0134 IWL_EXPORT_SYMBOL(iwl_write_prph64_no_grab);
0135 
0136 u32 iwl_read_prph(struct iwl_trans *trans, u32 ofs)
0137 {
0138     if (iwl_trans_grab_nic_access(trans)) {
0139         u32 val = iwl_read_prph_no_grab(trans, ofs);
0140 
0141         iwl_trans_release_nic_access(trans);
0142 
0143         return val;
0144     }
0145 
0146     return 0x5a5a5a5a;
0147 }
0148 IWL_EXPORT_SYMBOL(iwl_read_prph);
0149 
0150 void iwl_write_prph_delay(struct iwl_trans *trans, u32 ofs, u32 val, u32 delay_ms)
0151 {
0152     if (iwl_trans_grab_nic_access(trans)) {
0153         mdelay(delay_ms);
0154         iwl_write_prph_no_grab(trans, ofs, val);
0155         iwl_trans_release_nic_access(trans);
0156     }
0157 }
0158 IWL_EXPORT_SYMBOL(iwl_write_prph_delay);
0159 
0160 int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
0161               u32 bits, u32 mask, int timeout)
0162 {
0163     int t = 0;
0164 
0165     do {
0166         if ((iwl_read_prph(trans, addr) & mask) == (bits & mask))
0167             return t;
0168         udelay(IWL_POLL_INTERVAL);
0169         t += IWL_POLL_INTERVAL;
0170     } while (t < timeout);
0171 
0172     return -ETIMEDOUT;
0173 }
0174 
0175 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
0176 {
0177     if (iwl_trans_grab_nic_access(trans)) {
0178         iwl_write_prph_no_grab(trans, ofs,
0179                        iwl_read_prph_no_grab(trans, ofs) |
0180                        mask);
0181         iwl_trans_release_nic_access(trans);
0182     }
0183 }
0184 IWL_EXPORT_SYMBOL(iwl_set_bits_prph);
0185 
0186 void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
0187                 u32 bits, u32 mask)
0188 {
0189     if (iwl_trans_grab_nic_access(trans)) {
0190         iwl_write_prph_no_grab(trans, ofs,
0191                        (iwl_read_prph_no_grab(trans, ofs) &
0192                     mask) | bits);
0193         iwl_trans_release_nic_access(trans);
0194     }
0195 }
0196 IWL_EXPORT_SYMBOL(iwl_set_bits_mask_prph);
0197 
0198 void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
0199 {
0200     u32 val;
0201 
0202     if (iwl_trans_grab_nic_access(trans)) {
0203         val = iwl_read_prph_no_grab(trans, ofs);
0204         iwl_write_prph_no_grab(trans, ofs, (val & ~mask));
0205         iwl_trans_release_nic_access(trans);
0206     }
0207 }
0208 IWL_EXPORT_SYMBOL(iwl_clear_bits_prph);
0209 
0210 void iwl_force_nmi(struct iwl_trans *trans)
0211 {
0212     if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_9000)
0213         iwl_write_prph_delay(trans, DEVICE_SET_NMI_REG,
0214                      DEVICE_SET_NMI_VAL_DRV, 1);
0215     else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
0216         iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
0217                 UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER);
0218     else if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ)
0219         iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
0220                     UREG_DOORBELL_TO_ISR6_NMI_BIT);
0221     else
0222         iwl_write32(trans, CSR_DOORBELL_VECTOR,
0223                 UREG_DOORBELL_TO_ISR6_NMI_BIT);
0224 }
0225 IWL_EXPORT_SYMBOL(iwl_force_nmi);
0226 
0227 static const char *get_rfh_string(int cmd)
0228 {
0229 #define IWL_CMD(x) case x: return #x
0230 #define IWL_CMD_MQ(arg, reg, q) { if (arg == reg(q)) return #reg; }
0231 
0232     int i;
0233 
0234     for (i = 0; i < IWL_MAX_RX_HW_QUEUES; i++) {
0235         IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_BA_LSB, i);
0236         IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_WIDX, i);
0237         IWL_CMD_MQ(cmd, RFH_Q_FRBDCB_RIDX, i);
0238         IWL_CMD_MQ(cmd, RFH_Q_URBD_STTS_WPTR_LSB, i);
0239     }
0240 
0241     switch (cmd) {
0242     IWL_CMD(RFH_RXF_DMA_CFG);
0243     IWL_CMD(RFH_GEN_CFG);
0244     IWL_CMD(RFH_GEN_STATUS);
0245     IWL_CMD(FH_TSSR_TX_STATUS_REG);
0246     IWL_CMD(FH_TSSR_TX_ERROR_REG);
0247     default:
0248         return "UNKNOWN";
0249     }
0250 #undef IWL_CMD_MQ
0251 }
0252 
0253 struct reg {
0254     u32 addr;
0255     bool is64;
0256 };
0257 
0258 static int iwl_dump_rfh(struct iwl_trans *trans, char **buf)
0259 {
0260     int i, q;
0261     int num_q = trans->num_rx_queues;
0262     static const u32 rfh_tbl[] = {
0263         RFH_RXF_DMA_CFG,
0264         RFH_GEN_CFG,
0265         RFH_GEN_STATUS,
0266         FH_TSSR_TX_STATUS_REG,
0267         FH_TSSR_TX_ERROR_REG,
0268     };
0269     static const struct reg rfh_mq_tbl[] = {
0270         { RFH_Q0_FRBDCB_BA_LSB, true },
0271         { RFH_Q0_FRBDCB_WIDX, false },
0272         { RFH_Q0_FRBDCB_RIDX, false },
0273         { RFH_Q0_URBD_STTS_WPTR_LSB, true },
0274     };
0275 
0276 #ifdef CONFIG_IWLWIFI_DEBUGFS
0277     if (buf) {
0278         int pos = 0;
0279         /*
0280          * Register (up to 34 for name + 8 blank/q for MQ): 40 chars
0281          * Colon + space: 2 characters
0282          * 0X%08x: 10 characters
0283          * New line: 1 character
0284          * Total of 53 characters
0285          */
0286         size_t bufsz = ARRAY_SIZE(rfh_tbl) * 53 +
0287                    ARRAY_SIZE(rfh_mq_tbl) * 53 * num_q + 40;
0288 
0289         *buf = kmalloc(bufsz, GFP_KERNEL);
0290         if (!*buf)
0291             return -ENOMEM;
0292 
0293         pos += scnprintf(*buf + pos, bufsz - pos,
0294                 "RFH register values:\n");
0295 
0296         for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
0297             pos += scnprintf(*buf + pos, bufsz - pos,
0298                 "%40s: 0X%08x\n",
0299                 get_rfh_string(rfh_tbl[i]),
0300                 iwl_read_prph(trans, rfh_tbl[i]));
0301 
0302         for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
0303             for (q = 0; q < num_q; q++) {
0304                 u32 addr = rfh_mq_tbl[i].addr;
0305 
0306                 addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
0307                 pos += scnprintf(*buf + pos, bufsz - pos,
0308                     "%34s(q %2d): 0X%08x\n",
0309                     get_rfh_string(addr), q,
0310                     iwl_read_prph(trans, addr));
0311             }
0312 
0313         return pos;
0314     }
0315 #endif
0316 
0317     IWL_ERR(trans, "RFH register values:\n");
0318     for (i = 0; i < ARRAY_SIZE(rfh_tbl); i++)
0319         IWL_ERR(trans, "  %34s: 0X%08x\n",
0320             get_rfh_string(rfh_tbl[i]),
0321             iwl_read_prph(trans, rfh_tbl[i]));
0322 
0323     for (i = 0; i < ARRAY_SIZE(rfh_mq_tbl); i++)
0324         for (q = 0; q < num_q; q++) {
0325             u32 addr = rfh_mq_tbl[i].addr;
0326 
0327             addr += q * (rfh_mq_tbl[i].is64 ? 8 : 4);
0328             IWL_ERR(trans, "  %34s(q %d): 0X%08x\n",
0329                 get_rfh_string(addr), q,
0330                 iwl_read_prph(trans, addr));
0331         }
0332 
0333     return 0;
0334 }
0335 
0336 static const char *get_fh_string(int cmd)
0337 {
0338     switch (cmd) {
0339     IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
0340     IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
0341     IWL_CMD(FH_RSCSR_CHNL0_WPTR);
0342     IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
0343     IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
0344     IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
0345     IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
0346     IWL_CMD(FH_TSSR_TX_STATUS_REG);
0347     IWL_CMD(FH_TSSR_TX_ERROR_REG);
0348     default:
0349         return "UNKNOWN";
0350     }
0351 #undef IWL_CMD
0352 }
0353 
0354 int iwl_dump_fh(struct iwl_trans *trans, char **buf)
0355 {
0356     int i;
0357     static const u32 fh_tbl[] = {
0358         FH_RSCSR_CHNL0_STTS_WPTR_REG,
0359         FH_RSCSR_CHNL0_RBDCB_BASE_REG,
0360         FH_RSCSR_CHNL0_WPTR,
0361         FH_MEM_RCSR_CHNL0_CONFIG_REG,
0362         FH_MEM_RSSR_SHARED_CTRL_REG,
0363         FH_MEM_RSSR_RX_STATUS_REG,
0364         FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
0365         FH_TSSR_TX_STATUS_REG,
0366         FH_TSSR_TX_ERROR_REG
0367     };
0368 
0369     if (trans->trans_cfg->mq_rx_supported)
0370         return iwl_dump_rfh(trans, buf);
0371 
0372 #ifdef CONFIG_IWLWIFI_DEBUGFS
0373     if (buf) {
0374         int pos = 0;
0375         size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
0376 
0377         *buf = kmalloc(bufsz, GFP_KERNEL);
0378         if (!*buf)
0379             return -ENOMEM;
0380 
0381         pos += scnprintf(*buf + pos, bufsz - pos,
0382                 "FH register values:\n");
0383 
0384         for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
0385             pos += scnprintf(*buf + pos, bufsz - pos,
0386                 "  %34s: 0X%08x\n",
0387                 get_fh_string(fh_tbl[i]),
0388                 iwl_read_direct32(trans, fh_tbl[i]));
0389 
0390         return pos;
0391     }
0392 #endif
0393 
0394     IWL_ERR(trans, "FH register values:\n");
0395     for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
0396         IWL_ERR(trans, "  %34s: 0X%08x\n",
0397             get_fh_string(fh_tbl[i]),
0398             iwl_read_direct32(trans, fh_tbl[i]));
0399 
0400     return 0;
0401 }
0402 
0403 #define IWL_HOST_MON_BLOCK_PEMON    0x00
0404 #define IWL_HOST_MON_BLOCK_HIPM     0x22
0405 
0406 #define IWL_HOST_MON_BLOCK_PEMON_VEC0   0x00
0407 #define IWL_HOST_MON_BLOCK_PEMON_VEC1   0x01
0408 #define IWL_HOST_MON_BLOCK_PEMON_WFPM   0x06
0409 
0410 static void iwl_dump_host_monitor_block(struct iwl_trans *trans,
0411                     u32 block, u32 vec, u32 iter)
0412 {
0413     int i;
0414 
0415     IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec);
0416     iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec);
0417     for (i = 0; i < iter; i++)
0418         IWL_ERR(trans, "    value [iter %d]: 0x%08x\n",
0419             i, iwl_read32(trans, CSR_MONITOR_STATUS_REG));
0420 }
0421 
0422 static void iwl_dump_host_monitor(struct iwl_trans *trans)
0423 {
0424     switch (trans->trans_cfg->device_family) {
0425     case IWL_DEVICE_FAMILY_22000:
0426     case IWL_DEVICE_FAMILY_AX210:
0427         IWL_ERR(trans, "CSR_RESET = 0x%x\n",
0428             iwl_read32(trans, CSR_RESET));
0429         iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
0430                         IWL_HOST_MON_BLOCK_PEMON_VEC0, 15);
0431         iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
0432                         IWL_HOST_MON_BLOCK_PEMON_VEC1, 15);
0433         iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON,
0434                         IWL_HOST_MON_BLOCK_PEMON_WFPM, 15);
0435         iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM,
0436                         IWL_HOST_MON_BLOCK_PEMON_VEC0, 1);
0437         break;
0438     default:
0439         /* not supported yet */
0440         return;
0441     }
0442 }
0443 
0444 int iwl_finish_nic_init(struct iwl_trans *trans)
0445 {
0446     const struct iwl_cfg_trans_params *cfg_trans = trans->trans_cfg;
0447     u32 poll_ready;
0448     int err;
0449 
0450     if (cfg_trans->bisr_workaround) {
0451         /* ensure the TOP FSM isn't still in previous reset */
0452         mdelay(2);
0453     }
0454 
0455     /*
0456      * Set "initialization complete" bit to move adapter from
0457      * D0U* --> D0A* (powered-up active) state.
0458      */
0459     if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_BZ) {
0460         iwl_set_bit(trans, CSR_GP_CNTRL,
0461                 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
0462                 CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
0463         poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
0464     } else {
0465         iwl_set_bit(trans, CSR_GP_CNTRL,
0466                 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
0467         poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY;
0468     }
0469 
0470     if (cfg_trans->device_family == IWL_DEVICE_FAMILY_8000)
0471         udelay(2);
0472 
0473     /*
0474      * Wait for clock stabilization; once stabilized, access to
0475      * device-internal resources is supported, e.g. iwl_write_prph()
0476      * and accesses to uCode SRAM.
0477      */
0478     err = iwl_poll_bit(trans, CSR_GP_CNTRL, poll_ready, poll_ready, 25000);
0479     if (err < 0) {
0480         IWL_DEBUG_INFO(trans, "Failed to wake NIC\n");
0481 
0482         iwl_dump_host_monitor(trans);
0483     }
0484 
0485     if (cfg_trans->bisr_workaround) {
0486         /* ensure BISR shift has finished */
0487         udelay(200);
0488     }
0489 
0490     return err < 0 ? err : 0;
0491 }
0492 IWL_EXPORT_SYMBOL(iwl_finish_nic_init);
0493 
0494 void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr,
0495                   u32 sw_err_bit)
0496 {
0497     unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT;
0498     bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status);
0499 
0500     /* if the interrupts were already disabled, there is no point in
0501      * calling iwl_disable_interrupts
0502      */
0503     if (interrupts_enabled)
0504         iwl_trans_interrupts(trans, false);
0505 
0506     iwl_force_nmi(trans);
0507     while (time_after(timeout, jiffies)) {
0508         u32 inta_hw = iwl_read32(trans, inta_addr);
0509 
0510         /* Error detected by uCode */
0511         if (inta_hw & sw_err_bit) {
0512             /* Clear causes register */
0513             iwl_write32(trans, inta_addr, inta_hw & sw_err_bit);
0514             break;
0515         }
0516 
0517         mdelay(1);
0518     }
0519 
0520     /* enable interrupts only if there were already enabled before this
0521      * function to avoid a case were the driver enable interrupts before
0522      * proper configurations were made
0523      */
0524     if (interrupts_enabled)
0525         iwl_trans_interrupts(trans, true);
0526 
0527     iwl_trans_fw_error(trans, false);
0528 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!